Quelle  vcn_v4_0_5.c   Sprache: C

 (
  
 
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  
 ;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  is  dosubject followingjava.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
  =&>.[i.[0]
ring-=;
 * amdgpu_sriov_vf))
 *
*THE  PROVIDEDAS"WITHOUTWARRANTYOF ANY KIND OR
  ,INCLUDING  LIMITED  WARRANTIESOFMERCHANTABILITY
 * FITNESS FOR
 * ring-doorbell_index=(>..  )
 *    java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
* FROM OF OR CONNECTIONWITH  ORTHE OR
 * OTHER , &dev->.inst]sched_score
 *
   ()

# linuxfirmware>
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
include.
#include "amdgpu_pm fw_shared->sqis_enabled=
#include "amdgpu_cs.h"
#include "soc15.h"
#include "soc15d.h"
#include "soc15_hw_ip.h"
#include "vcn_v2_0.h"
#include "mmsch_v4_0.h"
#include "vcn_v4_0_5.h"

#include "vcn/vcn_4_0_5_offset.h"
#include "vcn/vcn_4_0_5_sh_mask.h"
#include   :AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU

include/.h

#define mmUVD_DPG_LMA_CTL > |cpu_to_le32);
define  regUVD_DPG_LMA_CTL_BASE_IDX
#define mmUVD_DPG_LMA_DATAdrm_key_wa =
#define     

#define VCN_VID_SOC_ADDRESS_2_0
 VCN1_VID_SOC_ADDRESS_3_0 0 +0)
#define VCN1_AON_SOC_ADDRESS_3_0amdgpu_vcn_fwlog_init>vcn[];

#define VCN_HARVEST_MMSCH       0

#define RDECODE_MSG_CREATE       0x00000000
#define  if (adev-pg_flagsAMD_PG_SUPPORT_VCN_DPG

static truct vcn_reg_list_4_0_5]  {
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
 SOC15_REG_ENTRY_STR(
 SOC15_REG_ENTRY_STR
 SOC15_REG_ENTRY_STR, ,regUVD_GPCOM_VCPU_DATA0
 SOC15_REG_ENTRY_STR(())
 SOC15_REG_ENTRY_STRadev-. =;
 SOC15_REG_ENTRY_STR
SOC15_REG_ENTRY_STR ,regUVD_RB_BASE_LO
 if (r  r
 SOC15_REG_ENTRY_STRifamdgpu_sriov_vf)){
 SOC15_REG_ENTRY_STR ()java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
 SOC15_REG_ENTRY_STR, ,regUVD_RB_BASE_LO3)
 SOC15_REG_ENTRY_STR (ptr
 SOC15_REG_ENTRY_STR DRM_ERROR"Failed VCN IPDumpn")java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
 SOC15_REG_ENTRY_STR(VCN * * @ip_block: Pointer *
 SOC15_REG_ENTRY_STR(VCN,  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 (, 0 ),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4 i  ;
 SOC15_REG_ENTRY_STR
 SOC15_REG_ENTRY_STRif(adev_to_drm) idxjava.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
 SOC15_REG_ENTRY_STR(VCN, 0, volatile  *;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 0 ),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),  continue
SOC15_REG_ENTRY_STR,0 regUVD_DPG_LMA_CTL),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
};

static int amdgpu_ih_clientid_vcns[] = {
 SOC15_IH_CLIENTID_VCN
 SOC15_IH_CLIENTID_VCN1
};

static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
 void vcn_v4_0_5_set_irq_funcsstruct *adev;
static  vcn_v4_0_5_set_pg_state amdgpu_vcn_instvinst
    java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (mdgpu_sriov_vf))
          amdgpu_virt_free_mm_table(adev
static void vcn_v4_0_5_unified_ring_set_wptr amdgpu_ringring

/**
 * vcn_v4_0_5_early_init - set function pointers and load microcode
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Set ring and irq function pointers
 * Load microcode from filesystem
 */
static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev
  i r;

 if (amdgpu_ip_versioni rjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
  adev-

 for (i = 0java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  /* re-use enc ring as unified ring */ *
  adev- * Initialize the hardware, bootjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 vcn_v4_0_5_set_unified_ring_funcs(adev);
 vcn_v4_0_5_set_irq_funcs(adev);

 for (i  amdgpu_device*dev=ip_block-adev
  adev-vcninst]set_pg_state vcn_v4_0_5_set_pg_state

 r=amdgpu_vcn_early_init, i);
  if
   return r;
 }

  for=0   adev-.num_vcn_inst+i {
}

/**
 * vcn_v4_0_5_sw_init - sw init for VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Load firmware and sw initialization
 */
static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_ring *ring;
 struct amdgpu_device *adev = ip_block->adev;
 int i, r;
 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5   continue;
 uint32_t*;


 for
  volatileadev-nbiofuncs->vcn_doorbell_range(devring-,

  if (adev->vcn.harvest_config & (1 << i))
   continuer=amdgpu_ring_test_helper(ring);

  r = amdgpu_vcn_sw_init(adev, i);
  if (r)
   return r;

  amdgpu_vcn_setup_ucode}

  r = amdgpu_vcn_resume(adev, i);
  if (r)
   return r;

 atomic_setadev->vcn.inst[].sched_score0;

  /* VCN UNIFIED TRAP */
  r = amdgpu_irq_add_id(java.lang.StringIndexOutOfBoundsException: Range [0, 28) out of bounds for length 1
    VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev-> java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  if (r)
   return r;

  /* VCN POISON TRAP */ amdgpu_deviceadev  >adev;
  r java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   VCN_4_0__SRCID_UVD_POISONadev-.inst]irq
  if (r)
   return r;

  ring = &adev->vcn.inststructamdgpu_vcn_instvinst=&dev-.java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
  ring-;
  if
   cancel_delayed_work_sync&>idle_work
      i
  else
  >doorbell_index adev-.vcnvcn_ring0_1< )+
      2 + 8 * i;
  ring->vm_hub = AMDGPU_MMHUB0(0);
  sprintf(ring-  f((>pg_flags AMD_PG_SUPPORT_VCN_DPG) |

  r = amdgpu_ring_init(adev, ring, 512, &      (inst- !  &&
  AMDGPU_RING_PRIO_0 adev-.inst]sched_score
  if (r)
   return r;

  fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
  fw_shared-}
  fw_shared->sq.is_enabled = 1;

 }
  fw_shared-
  AMDGPU_VCN_SMU_DPM_INTERFACE_APU ;

  if (amdgpu_sriov_vf(adev
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  fw_shared->present_flag_0
  fw_shared->drm_key_wa.method =
    *

  if (amdgpu_vcnfw_log)
   

   adev-pg_flags &AMD_PG_SUPPORT_VCN_DPG
   adev-
 }

   amdgpu_deviceadev ip_block-adev;
 if (intr ;
  adev-nr =vcn_v4_0_5_hw_finiip_block

 r  ifr)
 if (r returnr
  return r; for(  0  <adev->vcn; i+ java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47

 if (amdgpu_sriov_vf(adev)) {
 r=amdgpu_virt_alloc_mm_table(adev
  if (r)
   return r;
 }

 /* Allocate memory for VCN IP Dump buffer */
 ptr =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if 
  DRM_ERROR("Failed *
  adev->vcn.ip_dump  *
 * Resume firmware and hw
  adev- ,ijava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
java.lang.StringIndexOutOfBoundsException: Range [41, 2) out of bounds for length 2
 return 0;
}

*
 * java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 *
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 *
 *  *
 */
static int *
{
 struct amdgpu_device *adev = ip_block-
dx

 if 
   struct *adev =vinst->;
   struct *fw_shared

   if (adev- int32_t, sizejava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
  h = const common_firmware_header )>vcn[instfw-data

   fw_shared
 /java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
  fw_shared->.is_enabled 0java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
  }

  drm_dev_exit (>firmware[AMDGPU_UCODE_ID_VCN+insttmr_mc_addr_lojava.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
 }

 f((adev
   WREG32_SOC15(VCN, inst, 0)

  of =0java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
  r  (adev)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
  ifrjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
   return r;

    pper_32_bitsadev-.instinstgpu_addr;
  if (r)
   return r;
 }

 return 0;
}

/**
 * vcn_v4_0_5_hw_init - start and test VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Initialize the hardware, boot up the VCPU and do some testing
 */
static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev/* cache window 1: stack */
 structWREG32_SOC15, instregUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
 ;

 for (i = 0 (VCN,instregUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
 i adev-.harvest_config 1<i)
   continue;

  ring = &adev->vcn.inst[i].ring_enc[0WREG32_SOC15VCNinst,regUVD_VCPU_CACHE_OFFSET1)

  adev-/ cachewindow context */
    (( WREG32_SOC15(VCN instregUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW

  r =amdgpu_ring_test_helper);
  if (r)
  return;
 }

 return 0;
}

/**
 * vcn_v4_0_5_hw_fini - stop the hardware block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Stop the VCN block, mark ring as not ready any more
 */
static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev;
 int i;

 for (i =  lower_32_bitsadev-.instinstfw_sharedgpu_addr));
  structWREG32_SOC15, inst regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH

  if (adev-WREG32_SOC15(VCN inst regUVD_VCPU_NONCACHE_OFFSET0, 0);
   continue WREG32_SOC15VCN instregUVD_VCPU_NONCACHE_SIZE0

 cancel_delayed_work_syncvinst-);

  }
   
  java.lang.StringIndexOutOfBoundsException: Range [3, 4) out of bounds for length 3
        RREG32_SOC15 *
    vinst->set_pg_state(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   }
  }
 }

 return 0;
}

/**
 * vcn_v4_0_5_suspend - suspend VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * HW fini and suspend VCN block
 */
static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block)
{
amdgpu_device*adev =ip_block-adev;
 int inst_idx vinst->;

 r =vcn_v4_0_5_hw_fini);
 if struct common_firmware_header *hdr
  return r;

 for(i = 0  <  adev-vcn.num_vcn_inst i+) {
  r = amdgpu_vcn_suspend(ip_block->adev, i);
  if java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   return r;
 }

 return r;
}

/**
 * vcn_v4_0_5_resume - resume VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Resume firmware and hw init VCN block
 */
static  0 );
{
 struct amdgpu_device *adev = ip_block->adev;
 intr. +].)java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73

 forelsejava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
 r=(ip_block-adev;
  if (r)
  eturn
 }

 r = vcn_v4_0_5_hw_init(ip_block);

  (inst_idx(
}

/**
 * vcn_v4_0_5_mc_resume - memory controller programming
 *
 * @vinst: VCN instance
 *
 * Let the VCN memory controller know it's offsets
 */
static , , regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
{
 structamdgpu_deviceadev vinst->adev
 int  (inst_idx,SOC15_DPG_MODE_OFFSET
 int32_t, sizejava.lang.StringIndexOutOfBoundsException: Range [23, 24) out of bounds for length 23
 const struct common_firmware_header = sizejava.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16

hdrconst common_firmware_headeradev->.inst[].fw-data
 size

 /* cache window 0: fw */
 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
  WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
   ( (, SOC15_DPG_MODE_OFFSET
  WREG32_SOC15(VCN  , , ),size 0 );
    lse
  WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
  = 0;
 } else,regUVD_VCPU_CACHE_SIZE0 ,0 );
  /* cache window 1: stack */
   lower_32_bits( WREG32_SOC15_DPG_MODE(,SOC15_DPG_MODE_OFFSET
   ,inst_idx),
   upper_32_bits  (adev->.inst]. +offset) 0 );
  offset WREG32_SOC15_DPG_MODEinst_idxSOC15_DPG_MODE_OFFSET
  WREG32_SOC15 VCN , regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
 }
 WREG32_SOC15, , regUVD_VCPU_CACHE_SIZE0size

 /* cache window 1: stack */
 WREG32_SOC15VCN,inst regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
  lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
  upper_32_bits(adev->vcn.inst[inst]  VCN inst_idx ), 0,0,indirect);
 WREG32_SOC15, instregUVD_VCPU_CACHE_OFFSET1 );
  WREG32_SOC15_DPG_MODEinst_idx,SOC15_DPG_MODE_OFFSET

/
 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
  (adev-vcninst]. +offset MDGPU_VCN_STACK_SIZE;
 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH VCN,inst_idxregUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, ,0 indirect;
 upper_32_bitsadev-vcn[instgpu_addr  + AMDGPU_VCN_STACK_SIZE;
 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 WREG32_SOC15(VCN VCN inst_idxregUVD_VCPU_CACHE_OFFSET1,0 ,indirect

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
t,regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW
 ,regUVD_VCPU_CACHE_SIZE1 AMDGPU_VCN_STACK_SIZE,indirect
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 upper_32_bits>vcn.inst].fw_shared))
  VCN, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
  l(adev-.[inst_idxgpu_addr  + AMDGPU_VCN_STACK_SIZE
 (sizeofstruct amdgpu_vcn4_fw_shared))
}

/**
 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode
 *
 * @vinst: VCN instance
 * @indirect: indirectly write sram
 *
 * Let the VCN memory controller know it's offsets with dpg mode
 */
static void   , inst_idx regUVD_VCPU_CACHE_OFFSET2 0 ,indirect
       bool VCN inst_idx regUVD_VCPU_CACHE_SIZE2,, 0 indirect)
{
 struct amdgpu_device WREG32_SOC15_DPG_MODEinst_idx,(
int = >inst
 uint32_t(adev-.inst].fw_shared.),,indirect;
 const struct common_firmware_header *hdr;

= (const struct common_firmware_header*adev-.inst].fw-;
 size = AMDGPU_GPU_PAGE_ALIGN(adev->.inst]..gpu_addr0 );

 /* cache window 0: fw */
 if (>firmwareload_type =AMDGPU_FW_LOAD_PSP java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
 i (!ndirect
  AMDGPU_GPU_PAGE_ALIGN(struct)) , );
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  (>firmware[AMDGPU_UCODE_ID_VCNinst_idxtmr_mc_addr_lo
   0 , inst_idx, regUVD_GFX10_ADDR_CONFIG,
  (inst_idx SOC15_DPG_MODE_OFFSET
 
 
   0 indirect;
   WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
    VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0) * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating
  } else {
   WREG32_SOC15_DPG_MODE 
   VCN,static vcn_v4_0_5_disable_static_power_gating amdgpu_vcn_instvinst
   WREG32_SOC15_DPG_MODE
  VCNinst_idxregUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH) , , );
   WREG32_SOC15_DPG_MODE(inst_idx  = vinst->nst
    VCN, inst_idx,   data=0;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  =;
 } else {
 WREG32_SOC15_DPG_MODE(, SOC15_DPG_MODE_OFFSET(
      1< );
   lower_32_bits  SOC15_WAIT_ON_RREG(, , , ,
 (inst_idx (
   VCNWREG32_SOC15(, , regUVD_IPX_DLDO_CONFIG,
   upper_32_bits(>vcninst[nst_idxg), 0 indirect)java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
  offset,
  WREG32_SOC15_DPG_MODE(inst_idx,  UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK
  VCN , regUVD_VCPU_CACHE_OFFSET0
   >>3 ,indirect
 }

 if (!indirect   <UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT
  WREG32_SOC15_DPG_MODE, (
   VCN, inst_idx 1< ,
 else
 (inst_idx SOC15_DPG_MODE_OFFSET
   VCN, inst_idx,} {

 /* cache window 1: stack */< );
 if (indirect){
  WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
   VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
   lower_32_bits(adev-(VCNinst ,
  WREG32_SOC15_DPG_MODE1< );
SOC15_WAIT_ON_RREGVCN , ,
   upper_32_bits0 UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK;
  WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
   VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1 WREG32_SOC15VCN, ,
  else java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  WREG32_SOC15_DPG_MODE(, instregUVD_IPX_DLDO_CONFIG
   VCN <UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT
 (inst_idx(
    0 );
  WREG32_SOC15_DPG_MODE}
   VCN, inst_idx
 }

 WREG32_SOC15_DPG_MODE &=~x103java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
  VCN,    |  |

 * cache window 2: context */
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 , inst_idx regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
  lower_32_bits(adev->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  0, indirect);
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET * @vinst: VCN *
  VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
  upper_32_bits(adev->static  vcn_v4_0_5_enable_static_power_gating amdgpu_vcn_instvinst
  0, indirect
WREG32_SOC15_DPG_MODE, (
  VCN,  =vinst-;
 (inst_idx
  VCN, ifadev-> &AMD_PG_SUPPORT_VCN 

 /* non-cache window */
   =(,inst)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
 , , )java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
    );
 (inst_idx(
   1<,
 U);
 (, , ,
  VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 REG32_SOC15_DPG_MODEinst_idxSOC15_DPG_MODE_OFFSET(
  VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
  AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);

 tiling registers */
 WREG32_SOC15_DPG_MODET 1 < UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT
 , inst_idx regUVD_GFX10_ADDR_CONFIG
  adev- WREG32_SOC15, , regUVD_IPX_DLDO_CONFIG
}

/**
 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating
 *
 * @vinst: VCN instance
 *
 * Disable static power gating for VCN block
 */
static (VCNinstregUVD_IPX_DLDO_CONFIG,
{
 struct amdgpu_device *adev = vinst->adev;
 int inst vinst->inst
 uint32_t data (VCNinst,

 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
  WREG32_SOC15( java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
     1 java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
  SOC15_WAIT_ON_RREG(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
     UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK  >inst
 (VCN, ,
     java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  SOC15_WAIT_ON_RREG(VCN, inst,  ;
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK
 (VCN, regUVD_IPX_DLDO_CONFIG
    a|1<UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
  SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
   1 < ,
      (VCN, , regUVD_CGC_CTRL);
  WREG32_SOC15
     data(VCNinst);
  SOC15_WAIT_ON_RREG(VCN, inst &=(
     1 |UVD_CGC_GATE__UDEC_MASK
      |UVD_CGC_GATE__MPEG2_MASK
   java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  WREG32_SOC15 |UVD_CGC_GATE__LMI_MC_MASK
    
  SOC15_WAIT_ON_RREG UVD_CGC_GATE__IDCT_MASK
   0);
  WREG32_SOC15(  java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
   1 < |UVD_CGC_GATE__UDEC_RE_MASK
   java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
   0, UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK);
  WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
   1 <<   UVD_CGC_GATE__UDEC_IT_MASK
  java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
   , );
  WREG32_SOC15(VCN, instUVD_CGC_GATE__VCPU_MASK
   < );
  SOC15_WAIT_ON_RREG
   0 UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK
 }

 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
 data &= ~0x103;
 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
  data | UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
   UVD_POWER_STATUS__UVD_PG_EN_MASK=~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS data);
}

/**
 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating
 *
 * @vinst: VCN instance
 *
 * Enable static power gating for VCN block
 */
static voidvcn_v4_0_5_enable_static_power_gating(structamdgpu_vcn_inst *inst)
{
 struct amdgpu_device *adev = vinst->adev;
 int = vinst->inst;
 uint32_t data;

 if (  UVD_CGC_CTRL__UDEC_MODE_MASK
  /* Before power off, this indicator has to be turned on */
  data|UVD_CGC_CTRL__REGS_MODE_MASK
  data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
  data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF 
  WREG32_SOC15(  UVD_CGC_CTRL__LMI_UMC_MODE_MASK

  WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,   UVD_CGC_CTRL__MPRD_MODE_MASK
 2< UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
  SOC15_WAIT_ON_RREG, instregUVD_IPX_DLDO_STATUS
   < ,
   UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK );
  WREG32_SOC15(VCN, inst, WREG32_SOC15VCNinstregUVD_CGC_CTRL,data
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
, regUVD_IPX_DLDO_STATUSjava.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
  |
   UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK UVD_SUVD_CGC_GATE__SMP_MASK
  WREG32_SOC15(VCN, inst|java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
   2< UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
  SOC15_WAIT_ON_RREG(VCN, inst, |
   1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT
   
  WREG32_SOC15(VCN java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
  2< );
  SOC15_WAIT_ON_RREG(VCN  java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
  1< ,
   UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
 }
}

/**
 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating
 *
 * @vinst: VCN instance
 *
 * Disable clock gating for VCN block
 */
static  (VCN , , data)
{
 struct  data = RREG32_SOC15VCNinst,regUVD_SUVD_CGC_CTRL
 nt =vinst-inst
 int32_t;

 if (adev->cg_flags |java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
  java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39

/java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
data=(VCN,inst,regUVD_CGC_CTRL);
 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);

 * @vinst: VCN instance
 data &= * @indirect: indirectly write sram
   *
  | * Disable clock gating for VCN blockjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  | UVD_CGC_GATE__REGS_MASK
  |          sram_sel
  | UVD_CGC_GATE__LMI_MC_MASK
 |UVD_CGC_GATE__LMI_UMC_MASK
  | UVD_CGC_GATE__IDCT_MASK
    amdgpu_deviceadevvinst-;
  |   inst_idxvinst-;
  | UVD_CGC_GATE__LBSI_MASK reg_data 0java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
  |UVD_CGC_GATE__LRBBM_MASK
  | UVD_CGC_GATE__UDEC_RE_MASK
  | UVD_CGC_GATE__UDEC_CM_MASK
  |  |=1< ;
  | UVD_CGC_GATE__UDEC_DB_MASK |  <UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
 |UVD_CGC_GATE__UDEC_MP_MASK
  | UVD_CGC_GATE__WCB_MASK
  | UVD_CGC_GATE__VCPU_MASK
 |UVD_CGC_GATE__MMSCH_MASK

 WREG32_SOC15UVD_CGC_CTRL__UDEC_DB_MODE_MASK|
 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);  |

 RREG32_SOC15(, , regUVD_CGC_CTRL
d &=~UVD_CGC_CTRL__UDEC_RE_MODE_MASK
  | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
  | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
   UVD_CGC_CTRL__UDEC_DB_MODE_MASK
  |   UVD_CGC_CTRL__RBC_MODE_MASK
 
  | UVD_CGC_CTRL__UDEC_MODE_MASK |
   UVD_CGC_CTRL__IDCT_MODE_MASK
  |  UVD_CGC_CTRL__MPRD_MODE_MASK
  |   UVD_CGC_CTRL__MPC_MODE_MASK|
     |
  | UVD_CGC_CTRL__LMI_UMC_MODE_MASKUVD_CGC_CTRL__LRBBM_MODE_MASK
 |
  
  | UVD_CGC_CTRL__MPC_MODE_MASK
   
  | UVD_CGC_CTRL__LRBBM_MODE_MASK
   java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
  | UVD_CGC_CTRL__VCPU_MODE_MASK
  | , , ),0sram_sel)java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
 WREG32_SOC15(inst_idx(

 dataRREG32_SOC15(, inst);
 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
  | UVD_SUVD_CGC_GATE__SIT_MASK
  | UVD_SUVD_CGC_GATE__SMP_MASK
  |  (inst_idxSOC15_DPG_MODE_OFFSET(
  | UVD_SUVD_CGC_GATE__SDB_MASK,inst_idxregUVD_SUVD_CGC_CTRL , indirect
  | java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
  | UVD_SUVD_CGC_GATE__SIT_H264_MASK
  | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
  | UVD_SUVD_CGC_GATE__SCM_H264_MASK
  | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
  | UVD_SUVD_CGC_GATE__SDB_H264_MASK * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating
  | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
  | UVD_SUVD_CGC_GATE__SCLR_MASK *
  | UVD_SUVD_CGC_GATE__UVD_SC_MASK
  | UVD_SUVD_CGC_GATE__ENT_MASK
  | static void vcn_v4_0_5_enable_clock_gatistruct *)
  |UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
  | UVD_SUVD_CGC_GATE__SITE_MASK
  | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
  int =>;
 |UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
  | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 |UVD_SUVD_CGC_GATE__IME_HEVC_MASKjava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 |  ;

  (VCN, regUVD_SUVD_CGC_CTRL
data (
  
  data(VCN , );
  | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 |UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
  UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 |UVD_SUVD_CGC_CTRL__IME_MODE_MASK
   );
 WREG32_SOC15(VCN  
}

/**
 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 *
 * @vinst: VCN instance
 * @sram_sel: sram select
 * @indirect: indirectly write sram
 *
 * Disable clock gating for VCN block with dpg mode
 */
|java.lang.StringIndexOutOfBoundsException: Range [31, 32) out of bounds for length 31
   uint8_t,
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 struct amdgpu_device | UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 int inst_idx = vinst->inst;
 uint32_treg_data0

  adev- & )
  return;

/
 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT  UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 reg_data|UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 reg_data   
   UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
   UVD_CGC_CTRL__UDEC_IT_MODE_MASK|
   UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
   UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
   UVD_CGC_CTRL__SYS_MODE_MASK |
   UVD_CGC_CTRL__UDEC_MODE_MASK |
   UVD_CGC_CTRL__MPEG2_MODE_MASK |
   UVD_CGC_CTRL__REGS_MODE_MASK WREG32_SOC15(, inst, regUVD_SUVD_CGC_CTRL data;
   UVD_CGC_CTRL__RBC_MODE_MASK |
   UVD_CGC_CTRL__LMI_MC_MODE_MASK |
   UVD_CGC_CTRL__LMI_UMC_MODE_MASK
   java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 0
   UVD_CGC_CTRL__MPRD_MODE_MASK |
   UVD_CGC_CTRL__MPC_MODE_MASK |
   * @vinst: VCN instance
   UVD_CGC_CTRL__LRBBM_MODE_MASK |
   UVD_CGC_CTRL__WCB_MODE_MASK *
   UVD_CGC_CTRL__VCPU_MODE_MASK * Start VCN block with dpg mode
 static vcn_v4_0_5_start_dpg_mode amdgpu_vcn_inst*inst
  VCN, inst_idx     indirect

 /* turn off clock gating */
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSETint =>;
, indirect

 /* turn on SUVD clock gating */ ring
 WREG32_SOC15_DPG_MODE;
  VCN, inst_idx

 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
  /* enable dynamic power gating mode */
  , inst_idxregUVD_SUVD_CGC_CTRL,0 sram_sel,indirect
}

/**
 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating
 *
 * @vinst: VCN instance
 *
 * Enable clock gating for VCN block
 */
staticadev-vcn[inst_idxdpg_sram_curr_addr
{
 structamdgpu_device * = vinst-adev
 int inst = vinst-
 uint32_tdata

 if ( cn_v4_0_5_disable_clock_gating_dpg_mode, ,indirect
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* enable VCN CGC */
 data = RREG32_SOC15tmp= UVD_VCPU_CNTL__CLK_EN_MASK  UVD_VCPU_CNTL__BLK_RST_MASK
data=0< UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFTjava.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
  |  <<UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
 data |= 4
 WREG32_SOC15VCNinstregUVD_CGC_CTRL data)

 data(inst_idxSOC15_DPG_MODE_OFFSET
 data | (java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
  |UVD_CGC_CTRL__UDEC_IT_MODE_MASK
  | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
  | UVD_CGC_CTRL__UDEC_MP_MODE_MASK   |
  | UVD_CGC_CTRL__SYS_MODE_MASK
  | UVD_CGC_CTRL__UDEC_MODE_MASK
  | UVD_CGC_CTRL__MPEG2_MODE_MASK
  | UVD_CGC_CTRL__REGS_MODE_MASK
  | UVD_CGC_CTRL__RBC_MODE_MASK
  | UVD_CGC_CTRL__LMI_MC_MODE_MASK
  | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
  | UVD_CGC_CTRL__IDCT_MODE_MASK
  | UVD_CGC_CTRL__MPRD_MODE_MASK
  | UVD_CGC_CTRL__MPC_MODE_MASK
 8< ) |
  | UVD_CGC_CTRL__LRBBM_MODE_MASK 0);
  WREG32_SOC15_DPG_MODE(, (
  | UVD_CGC_CTRL__VCPU_MODE_MASK
 |UVD_CGC_CTRL__MMSCH_MODE_MASK
 WREG32_SOC15(

 data = RREG32_SOC15(VCN, instVCNinst_idxregUVD_MPC_CNTL
 ata(
  | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 |UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
  | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 |UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 |UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 | );
 WREG32_SOC15(VCN 0 < UVD_MPC_SET_MUXA0__VARA_4__SHIFT), ,indirect
}

/**
 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode
 *
 * @vinst: VCN instance
 * @indirect: indirectly write sram
 *
 * Start VCN block with dpg mode
 */
static( <UVD_MPC_SET_MUXB0__VARB_3__SHIFT
     (x4 )),0 );
{
 struct amdgpu_device WREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
 nt = vinst->;
 volatile struct( < ) |
 struct amdgpu_ring *ring;
uint32_t;
 int ret;

 /* disable register anti-hang mechanism */
WREG32_P(VCN , ),,
  ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 /* enable dynamic power gating mode */
 tmp = RREG32_SOC15(VCN,  , , regUVD_VCPU_CNTL,tmp 0,indirect
 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK
 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
WREG32_SOC15, , regUVD_POWER_STATUS, tmp

 if (indirect)
 >vcninst[].dpg_sram_curr_addr
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* enable clock gating */
 vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect);

 /* enable VCPU clock */
 tmp= (0xFF<<UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT;
 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  VCN, inst_idxjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* disable master interrupt */
 WREG32_SOC15_DPG_MODE_(inst_idx(
 dev_errdevvcn   d", ret)


tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__REQ_MODE_MASK |
UVD_LMI_CTRL__CRC_RESET_MASK |
UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
0x00100000L);
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);

WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_MPC_CNTL),
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);

WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_MPC_SET_MUXA0),
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);

WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_MPC_SET_MUXB0),
 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);

WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_MPC_SET_MUX),
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);

vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect);

tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);

/* enable LMI MC and UMC channels */
 tmp   > <  java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);

 /* enable master interrupt */
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET
  VCN
  UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);

 if * vcn_v4_0_5_start - VCN start
  ret = java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 23
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   dev_erradev-dev" sramloadfailed%\");
   return ret;
  }
 }

 ring = &adev->vcn.inst[inst_idx].ring_enc[0];

 WREG32_SOC15(VCN, inst_idx,  inti= vinst-inst;
WREG32_SOC15(, inst_idx, regUVD_RB_BASE_HIupper_32_bitsring-gpu_addr));
 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);

 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
 tmp& ~VCN_RB_ENABLE__RB1_EN_MASK;
 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
fw_shared-sqqueue_mode | ;
 WREG32_SOC15(VCNjava.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
 WREG32_SOC15(VCNreturn;

 tmp = RREG32_SOC15(VCN, inst_idx,  if adev-pm.dpm_enabled)
 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
 ring-> = RREG32_SOC15VCN , regUVD_RB_WPTR

 tmp = RREG32_SOC15(VCN, inst_idxfw_shared adev-vcn[i]fw_shared;
 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
 WREG32_SOC15, inst_idxregVCN_RB_ENABLEtmp;
 fw_shared->sq  vcn_v4_0_5_start_dpg_mode, adev-vcn[i]indirect_sram

 WREG32_SOC15(VCN inst_idx regVCN_RB1_DB_CTRL
   ring->doorbell_index  (vinst);
   VCN_RB1_DB_CTRL__EN_MASK);

 /* Keeping one read-back to ensure all register writes are done, otherwise
 * it may introduce race conditions */
RREG32_SOC15VCN, inst_idx regVCN_RB1_DB_CTRL);

 return 0;
}


/**
 * vcn_v4_0_5_start - VCN start
 *
 * @vinst: VCN instance
 *
 * Start VCN block
 */
static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)
{
 struct amdgpu_device *adev = 
int i = vinst->inst;
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
int j, k, r;

if (adev->vcn.harvest_config & (1 << i))
return 0;

if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_vcn(adev, true, i);

fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;

if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return vcn_v4_0_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);

/* disable VCN power gating */
 (VCNi , );

 /* setup regUVD_LMI_CTRL */
tmp=RREG32_SOC15, ,regUVD_STATUS  ;
 WREG32_SOC15 WREG32_SOC15(, , , tmp

 /* SW clock gating */
 vcn_v4_0_5_disable_clock_gating(vinstUVD_LMI_CTRL__MASK_MC_URGENT_MASK

 /* enable VCPU clock */
WREG32_PSOC15_REG_OFFSET(, , ),
   UVD_VCPU_CNTL__CLK_EN_MASK

/
 WREG32_P =x2 ;
   ~ WREG32_SOC15,i , tmp

 /* enable LMI MC and UMC channels */
 WREG32_P(SOC15_REG_OFFSET(      (x1 <UVD_MPC_SET_MUXA0__VARA_1__SHIFT
   ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);

 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
WREG32_SOC15, i regUVD_SOFT_RESET tmp

 /* setup regUVD_LMI_CTRL */
 tmp
 (VCN regUVD_LMI_CTRLtmp |
       UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
       UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
       UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
       UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);

 /* setup regUVD_MPC_CNTL */
 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
tmp= java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 WREG32_SOC15       <) java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
vcn_v4_0_5_mc_resume);
 /* setup UVD_MPC_SET_MUXA0 */
 WREG32_SOC15(VCN, WREG32_SOC15(VCN, ,regUVD_GFX10_ADDR_CONFIG,
 (0 <) |
        (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
        (
        ( /* unblock VCPU register access */

 /* setup UVD_MPC_SET_MUXB0 */
 WREG32_SOC15VCN i ,
       ((0x1 <
        ( 
      (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
      (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));

/* setup UVD_MPC_SET_MUX */
 WREG32_SOC15(VCN, i
     0 < ) java.lang.StringIndexOutOfBoundsException: Range [48, 49) out of bounds for length 48
  (01 < ) |
        (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT   = (, ,);

 vcn_v4_0_5_mc_resume ;

 /* VCN global tiling registers */
 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
       adev->gfxconfiggb_addr_config

 /* unblock VCPU register access */
 WREG32_P(SOC15_REG_OFFSET(
  ~);

 /* release VCPU reset to boot */
 WREG32_P(SOC15_REG_OFFSET(VCN, i  r 0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
   ~UVD_VCPU_CNTL__BLK_RST_MASK)   0

 for (j = 0; j < 10; + ;
  uint32_t status;

  for (  "VCN%]isnotresponding, ryingtoresetVCPU!!n" )
 statusRREG32_SOC15VCN i );
   if (status & 2)
    break;
   mdelay(10);
   if (amdgpu_emu_mode == 1)
    sleep
  }

  if (amdgpu_emu_mode == 1) {
   r = -1;
   if 
    r = 0;
    break;
   }
  } else if (r {
java.lang.StringIndexOutOfBoundsException: Range [19, 9) out of bounds for length 9
  if (tatus 2)
    break;

   dev_err(adev->dev,
  "[%d]isnotresponding,tryingtoresetVCPU!\, i)
   WREG32_P(SOC15_REG_OFFSET(VCN UVD_MASTINT_EN__VCPU_EN_MASK
     UVD_VCPU_CNTL__BLK_RST_MASK,
  /* clear the busy bit of VCN_STATUS */
   (1)java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
 ((i ), ,
   ~);

   mdelay(10);
   r = -1;
  }
 }

 f(r java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return( , )java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
 }

 /* enable master interrupt */
((VCNi regUVD_MASTINT_EN
  ,
   ~UVD_MASTINT_EN__VCPU_EN_MASK);

 /* clear the busy bit of VCN_STATUS */
 WREG32_P(SOC15_REG_OFFSET(VCN >wptr(,i);
   ~(2 < =(VCNi );

  &vcn.[0
 WREG32_SOC15(VCN>. =~FW_QUEUE_RING_RESET |FW_QUEUE_DPG_HOLD_OFF)java.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
      VCN_RB1_DB_CTRL__EN_MASK;

 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 (VCN ,regUVD_RB_SIZE >ring_size )java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59

 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 WREG32_SOC15(VCN * Stop VCN block with dpg mode
 fw_shared->sq.ueue_mode|=FW_QUEUE_RING_RESET
 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);

 tmp =  int32_t;
 WREG32_SOC15
 ring->wptr = RREG32_SOC15(obe *

tmp RREG32_SOC15VCN ,r);
  );
 WREG32_SOC15(VCN
 fw_shared->sqqueue_mode& FW_QUEUE_RING_RESETFW_QUEUE_DPG_HOLD_OFF

 /* Keeping one read-back to ensure all register writes are done, otherwiseRREG32_SOC15(VCN,inst_idx regUVD_RB_WPTR
 * it may introduce race conditions */
 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

 return )
}

/**WREG32_PSOC15_REG_OFFSET(, ,regUVD_POWER_STATUS,0
 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode
 *
 * @vinst: VCN instance
 *
 * Stop VCN block with dpg mode
 */
static void
{
 struct amdgpu_device *adev = vinst->adev *
 int *
 uint32_t tmp;

 /* Wait for power status to be 1 */
 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

 /* wait for read ptr to be equal to write ptr */
 tmp = RREG32_SOC15   >inst
 SOC15_WAIT_ON_RREG struct *fw_shared

 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

/
 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS  0;
  ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);

 /* Keeping one read-back to ensure all register writes are done,f>sqqueue_mode=FW_QUEUE_DPG_HOLD_OFF;
 * otherwise it may introduce race conditions.
 */
 RREG32_SOC15(VCN,   vcn_v4_0_5_stop_dpg_mode(inst)
}

/**
 * vcn_v4_0_5_stop - VCN stop
 *
 * @vinst: VCN instance
 *
 * Stop VCN block
 */
static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst)
{
structamdgpu_deviceadev=vinst-adev
 int i =vinst-;
 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
  UVD_LMI_STATUS__READ_CLEAN_MASK|
 int r = 0;

 if (adev->vcn  VD_LMI_STATUS__WRITE_CLEAN_MASK
  return 0

 fw_shared  >vcn[i]fw_sharedcpu_addr;
 fw_shared-sq | ;

 if (adev->pg_flags & java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 vcn_v4_0_5_stop_dpg_mode);
   0
 ;
 }

 /* wait for vcn idle */
 r =   ;
 if (r)
  goto done;

 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
  UVD_LMI_STATUS__READ_CLEAN_MASK |
  UVD_LMI_STATUS__WRITE_CLEAN_MASK |
  UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
 r = SOC15_WAIT_ON_RREG(VCN, i,  (SOC15_REG_OFFSET,i ),
 if rjava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
  goto done;

/
 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
WREG32_SOC15VCN,regUVD_LMI_CTRL2);
 tmp   |
 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
 r  (VCNi , tmp);
 if ()
 gotodone;

 /* block VCPU register access */
 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRLjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 UVD_RB_ARB_CTRL__VCPU_DIS_MASK
 

 /* reset VCPU */
WREG32_P(VCNi ),
   UVD_VCPU_CNTL__BLK_RST_MASK,
   UVD_VCPU_CNTL__BLK_RST_MASK

 /* disable VCPU clock */
 WREG32_P(SOC15_REG_OFFSET /* Keeping one read-back to ensure all register writes are done,
 ~(UVD_VCPU_CNTL__CLK_EN_MASK));

/* apply soft reset */
  =RREG32_SOC15,i );
 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
done:
 (VCN ,regUVD_SOFT_RESET
 tmp=UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
 WREG32_SOC15(VCN, i

}
 WREG32_SOC15(VCN, i, regUVD_STATUS, 0)/

 /* apply HW clock gating */
 vcn_v4_0_5_enable_clock_gating(vinst * @vinst: VCN instance

 /* enable VCN power gating */
 vcn_v4_0_5_enable_static_power_gating(vinst);

 /* Keeping one read-back to ensure all register writes are done,
 * otherwise it may introduce race conditions.
 */
RREG32_SOC15, i regUVD_STATUS);

done:
 if (adev->pm.dpm_enabled)
  amdgpu_dpm_enable_vcnadevfalse,);

 return r;
}

/**
 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode
 *
 * @vinst: VCN instance
 * @new_state: pause state
 *
 * Pause dpg mode for VCN block
 */
static   >vcn[inst_idxpause_state, new_state-fw_based)
   struct *new_statejava.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
{
 amdgpu_device  >adev
 int inst_idx UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 uint32_t reg_data = 0;
 int ret_code;

 /* pause/unpause if state is changed */
 if (adev->vcn. WREG32_SOC15VCN ,regUVD_DPG_PAUSE );
  DRM_DEV_DEBUG(adev- /* wait for ACK */
   adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->  (VCN,inst_idx ,
  =RREG32_SOC15,inst_idxregUVD_DPG_PAUSE
     UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK

  if O SOC15_WAIT_ON_RREG, inst_idx regUVD_POWER_STATUS,
 ret_code SOC15_WAIT_ON_RREGVCNinst_idx, regUVD_POWER_STATUS0,
    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK

   if (!ret_code) {
    /* pause DPG */
;
    WREG32_SOC15(VCN,  (VCN, , reg_data;

    /* wait for ACK */].ause_state = new_state-fw_based
    SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
   return ;
}

   SOC15_WAIT_ON_RREG,inst_idxregUVD_POWER_STATUSjava.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
     UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
     UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
   }
  } else {
   /* unpause dpg, no need to wait */
   reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
   WREG32_SOC15(VCN inst_idx , reg_data;
 
  adev->cn[inst_idxpause_state =new_state-;
 }

 return 0;
}

/**
 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware unified read pointer
 */
static uint64_t vcn_v4_0_5_unified_ring_get_rptr(struct
{
 struct amdgpu_device *adev =  * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer

 if (ring !=  *
  DRM_ERROR("wrong ring id is identified in %s", __func__);

 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
}

/**
 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware unified write pointer
 */
static uint64_t vcn_v4_0_5_unified_ring_get_wptr(struct
{
  struct

 if
DRM_ERROR("wrong ring id is identified in %s", __func__);

if (ring->use_doorbell)
return *ring->wptr_cpu_addr;
else
return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
}

/**
 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the enc write pointer to the hardware
 */
  vcn_v4_0_5_unified_ring_set_wptr *
{
  amdgpu_device = ring-;

 if(ing adev-.inst[>mering_enc0)
  DRM_ERROR("wrong ring id is identified in WDOORBELL32(>doorbell_index,lower_32_bits(>wptr);

if(>use_doorbell{
  *ring-}
  WDOORBELL32(ring->doorbell_index, java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 0
 }else{
  WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits  struct )
 }
}

static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *  ;
   (ring);
     struct amdgpu_fence()
{
 struct amdgpu_device *adev(java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me}
 int r;

 amdgpu_ring_reset_helper_beginring timedout_fence;
r=vcn_v4_0_5_stop(vinst
 ifr
 return ;
 r = vcn_v4_0_5_start(vinst);
 if  .get_rptr= vcn_v4_0_5_unified_ring_get_rptr,
  return r;
 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}

static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
 .type = AMDGPU_RING_TYPE_VCN_ENC,
 .align_mask = 0x3f,
 .nop = VCN_ENC_CMD_NO_OP,
 .get_rptr = vcn_v4_0_5_unified_ring_get_rptr,
 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr,
 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr,
 .emit_frame_size =
  SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
  SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
 .mit_ib_size=5 /* vcn_v2_0_enc_ring_emit_ib */
  x2 vmfence
  1, /* vcn_v2_0_enc_ring_insert_end */
 .emit_ib_size = 5insert_end=vcn_v2_0_enc_ring_insert_end,
 .emit_ib = amdgpu_ring_generic_pad_ib
 .emit_fencebegin_useamdgpu_vcn_ring_begin_use
 .emit_vm_flush,
 .test_ring  emit_wreg vcn_v2_0_enc_ring_emit_wreg
. = ,
 .insert_nop  emit_reg_write_reg_wait amdgpu_ring_emit_reg_write_reg_wait_helper,
 .nsert_end= vcn_v2_0_enc_ring_insert_end
 };
 .begin_use = amdgpu_vcn_ring_begin_use,
 .end_use = amdgpu_vcn_ring_end_use,
 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 .reset = vcn_v4_0_5_ring_reset,
};

/**
 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions
 *
 * @adev: amdgpu_device pointer
 *
 * Set unified ring functions
 */
static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device
{
 int i;

 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if ( continuejava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
   continue;


  vcn_v4_0_5_unified_ring_vm_funcs = true

  adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;
  adev->vcn
 }
}

/**
 * vcn_v4_0_5_is_idle - check VCN block is idle
 *
 * @ip_block: Pointer to the amdgpu_ip_block structure
 *
 * Check whether VCN block is idle
 */
staticstatic  vcn_v4_0_5_is_idlestruct *ip_block
{
   *dev=ip_block-adev
 int i, ret = 1;

 for (i = 0; i < adev- ori= ;i< >vcnnum_vcn_inst +){
  if (adev->vcn.harvest_config & (1 << i))
   continue;

  ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
 }

 return ret;
}

/**
 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Wait for VCN block idle
 */
static int vcn_v4_0_5_wait_for_idle(struct java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 45
{
 structamdgpu_deviceadev ip_block-adev
 int i, ret = 0;

 for (i = 0 c;
  if (adev->vcn   =(, ,,UVD_STATUS__IDLE
   continue;

  ret = SOC15_WAIT_ON_RREG(}
   UVD_STATUS__IDLE);
  if (ret)
   returnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }

 return ret;
}

/**
 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state
 *
 * @ip_block: amdgpu_ip_block pointer
 * @state: clock gating state
 *
 * Set VCN block clockgating state
 */
static
      amd_clockgating_state)
{
 structamdgpu_deviceadev ip_block->dev
 ( ;i<>vcn; + {
  struct * =&adev-vcn.[i]java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53

 for (i = 0; i < adev- enable
 struct * =&dev-inst]

 ifadev-.harvest_config1<i)java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
   continue

  if (enable) {
   if (RREG32_SOC15(VCN, java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
    return -EBUSY;
   vcn_v4_0_5_enable_clock_gating(vinst);
  } elsejava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
   vcn_v4_0_5_disable_clock_gating(inst
  }
 }

 return 0;
}

static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst,
       enumamd_powergating_state )
{
 int ret e== AMD_PG_STATE_GATE)

 if (state == vinst->cur_state)
  return 0;

 if t =vcn_v4_0_5_startvinst;
  ret = vcn_v4_0_5_stop(vinst);
 else
  ret = vcn_v4_0_5_start(vinst);

 if
 vinst-c = state

 return ret;
}

/**
 * vcn_v4_0_5_process_interrupt - process VCN block interrupt
 *
 * @adev: amdgpu_device pointer
 * @source: interrupt sources
 * @entry: interrupt entry from clients and sources
 *
 * Process VCN block interrupt
 */
static structamdgpu_iv_entry*ntry
  struct amdgpu_iv_entry *entry) uint32_t;
{
 uint32_t ip_instance;

 switch (entry->client_id) {
 case SOC15_IH_CLIENTID_VCN: case :
  ip_instance = 0;
  break;
 case SOC15_IH_CLIENTID_VCN1:
  ip_instance=1;
  break;
 default:
  DRM_ERROR("Unhandled client id: %d\n", entry->client_id
 0
 }

 DRM_DEBUG("IH: VCN TRAP\n");

switch>src_id
 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
  amdgpu_fence_process(&adev-amdgpu_vcn_process_poison_irq, , entry)
  break;
 case VCN_4_0__SRCID_UVD_POISON (" interrupt % %\"
 amdgpu_vcn_process_poison_irqadev, entry
  break;
 default:
  DRM_ERROR("Unhandled interrupt: %d %d\n",
     java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 10
  break;
 java.lang.StringIndexOutOfBoundsException: Range [2, 3) out of bounds for length 2

 return 0;
}

static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = {
 . * @adev: amdgpu_device pointer
};

/**
 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions
 *
 * @adev: amdgpu_device pointer
 *
 * Set VCN block interrupt irq functions
 */
 void(struct *)
{
 int i;

 for (  ;  < adev-vcn.; ++i {
  if (adev->vcn continue
   continue;

  adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1;
  adev->vcnadev-.inst..funcs &cn_v4_0_5_irq_funcs;
 }
}

static voidjava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 0
{
 struct amdgpu_device *adev i,;
 int i, j;
uint32_t  (vcn_reg_list_4_0_5
 uint32_t inst_off,  inst_off;

 if(adev->.ip_dump
;

d(p num_instancesdn"adev-vcn.num_vcn_inst)
 for(  ;i<adev-v.num_vcn_inst+){
  if (adev->vcn.harvest_config & (1 << i)) {
   drm_printf(p, "\nHarvested Instance:VCN%d (, "nHarvested:VCN  dump" )java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
   continue;
  }

  inst_off = i * reg_count;
  is_powered  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK ;
    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;

  if (is_powered) {
  drm_printfp,"nActiveInstance:VCN%\" )java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
   for (j = 0; j < reg_count drm_printfp %-5s\t 00xn, cn_reg_list_4_0_5]reg_name
  drm_printfp "%-0 \ 0%8\" vcn_reg_list_4_0_5].eg_name
        >vcn[inst_off ];
  } else {
   drm_printf(p, "\nInactive Instance:VCN%d\n", i);
  }
 }
}

static void vcn_v4_0_5_dump_ip_state(struct}
{
 struct amdgpu_device static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
 int i, j;
 bool is_powered
 uint32_t inst_off;
 uint32_t reg_count = ARRAY_SIZEjava.lang.StringIndexOutOfBoundsException: Range [32, 33) out of bounds for length 17

 if (!adev->vcn.ip_dump)
  return;

fori  ; i<adev-vcn.; i+) {
  if (  return;
   continue;

  inst_off = i * reg_count;
  /* mmUVD_POWER_STATUS is always readable and is first element of the array */
  adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN   continue
  is_powered = (adev->vcn.ip_dump[inst_off inst_off i * reg_count
   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK!= 1;

 ifis_powered
 (j = ; j<reg_countj+)
    adev->vcn.ip_dump[inst_off + j] =
     RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
            i));
 }
}

static const struct amd_ip_funcs >vcnip_dump + j java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 name"cn_v4_0_5,
 .early_init = vcn_v4_0_5_early_init,
 .sw_init = vcn_v4_0_5_sw_init,
 .
 hw_init vcn_v4_0_5_hw_init
 .hw_fini = vcn_v4_0_5_hw_fini
 .suspendvcn_v4_0_5_suspend
 .resume = vcn_v4_0_5_resume,
 .is_idle = vcn_v4_0_5_is_idle,
 .wait_for_idle = vcn_v4_0_5_wait_for_idle,
 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
 .set_powergating_state = vcn_set_powergating_state,
 .dump_ip_state = vcn_v4_0_5_dump_ip_state,
 .print_ip_state = vcn_v4_0_5_print_ip_state,
};

const struct amdgpu_ip_block_version.set_clockgating_state vcn_v4_0_5_set_clockgating_state,
 .type = AMD_IP_BLOCK_TYPE_VCN,
 .major = 4,
 .minor = 0,
 .rev = 5,
 .funcs = &vcn_v4_0_5_ip_funcs,
};