D3Clause *
/*
 * This file is provided under a dual BSD/GPLv2 license. When using or
 * redistributing this file, you may do so under either license.
 *
 * Copyright(c) 2021 Advanced Micro Devices, Inc.. All rights reserved.
 */

#ifndef __INCLUDE_SOUND_SOF_DAI_AMD_H__
 

#sound/header.>

/* ACP Configuration Request - SOF_IPC_DAI_AMD_CONFIG */
struct sof_ipc_dai_acp_params {
 struct sof_ipc_hdr hdr;

 uint32_t fsync_rate;    /* FSYNC frequency in Hz */
 uint32_t tdm_slots;
 uint32_t 
;

/* ACPDMIC Configuration Request - SOF_IPC_DAI_AMD_CONFIG */sofjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 29
_{ _java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
uint32_tpdm_rate;
 uint32_t pdm_ch;
} __packed;

/* ACP_SDW Configuration Request - SOF_IPC_DAI_AMD_SDW_CONFIG */java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 19
java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 0
  sof_ipc_hdrhdr
  structsof_ipc_hdr hdr;
 u32 channels;
} __packed;

#endif