int aiu_fifo_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
{ switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
aiu_fifo_enable(dai, true); break; case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_STOP:
aiu_fifo_enable(dai, false); break; default: return -EINVAL;
}
/* Setup the fifo to read all the memory - no skip */
snd_soc_component_update_bits(component,
fifo->mem_offset + AIU_MEM_MASKS,
AIU_MEM_MASK_CH_RD | AIU_MEM_MASK_CH_MEM,
FIELD_PREP(AIU_MEM_MASK_CH_RD, 0xff) |
FIELD_PREP(AIU_MEM_MASK_CH_MEM, 0xff));
/* * Make sure the buffer and period size are multiple of the fifo burst * size
*/
ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
fifo->fifo_block); if (ret) return ret;
ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
fifo->fifo_block); if (ret) return ret;
ret = clk_prepare_enable(fifo->pclk); if (ret) return ret;
ret = request_irq(fifo->irq, aiu_fifo_isr, 0, dev_name(dai->dev),
substream); if (ret)
clk_disable_unprepare(fifo->pclk);
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