/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse #ifndef __RADEON_H__#define __RADEON_H__/* TODO: Here are things that needs to be done : * - surface allocator & initializer : (bit like scratch reg) should * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings * related to surface * - WB : write back stuff (do it bit like scratch reg things) * - Vblank : look at Jesse's rework and what we should do * - r600/r700: gart & cp * - cs : clean cs ioctl use bitmap & things like that. * - power management stuff * - Barrier in gart code * - Unmappabled vram ? * - TESTING, TESTING, TESTING /* Initialization path: * We expect that acceleration initialization might fail for various * reasons even thought we work hard to make it works on most * configurations. In order to still have a working userspace in such * situation the init path must succeed up to the memory controller * initialization point. Failure before this point are considered as * fatal error. Here is the init callchain : * radeon_device_init perform common structure, mutex initialization * asic_init setup the GPU memory layout and perform all * one time initialization (failure in this * function are considered fatal) * asic_startup setup the GPU acceleration, in order to * follow guideline the first thing this * function should do is setting the GPU * memory controller (only MC setup failure * are considered as fatal) #include <linux/agp_backend.h>#include <linux/atomic.h>#include <linux/wait.h>#include <linux/list.h>#include <linux/kref.h>#include <linux/interval_tree.h>#include <linux/hashtable.h>#include <linux/dma-fence.h>#ifdef CONFIG_MMU_NOTIFIER#include <linux/mmu_notifier.h>#endif #include <drm/ttm/ttm_bo.h>#include <drm/ttm/ttm_placement.h>#include <drm/drm_exec.h>#include <drm/drm_gem.h>#include <drm/drm_audio_component.h>#include <drm/drm_suballoc.h>#include "radeon_family.h" #include "radeon_mode.h" #include "radeon_reg.h" /* * Modules parameters. extern int radeon_no_wb;extern int radeon_modeset;extern int radeon_dynclks;extern int radeon_r4xx_atom;extern int radeon_agpmode;extern int radeon_vram_limit;extern int radeon_gart_size;extern int radeon_benchmarking;extern int radeon_testing;extern int radeon_connector_table;extern int radeon_tv;extern int radeon_audio;extern int radeon_disp_priority;extern int radeon_hw_i2c;extern int radeon_pcie_gen2;extern int radeon_msi;extern int radeon_lockup_timeout;extern int radeon_fastfb;extern int radeon_dpm;extern int radeon_aspm;extern int radeon_runtime_pm;extern int radeon_hard_reset;extern int radeon_vm_size;extern int radeon_vm_block_size;extern int radeon_deep_color;extern int radeon_use_pflipirq;extern int radeon_bapm;extern int radeon_backlight;extern int radeon_auxch;extern int radeon_uvd;extern int radeon_vce;extern int radeon_si_support;extern int radeon_cik_support;/* * Copy from radeon_drv.h so we don't have to include both and have conflicting * symbol; #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ /* RADEON_IB_POOL_SIZE must be a power of 2 */ #define RADEON_IB_POOL_SIZE 16#define RADEON_DEBUGFS_MAX_COMPONENTS 32#define RADEON_BIOS_NUM_SCRATCH 8/* internal ring indices */ /* r1xx+ has gfx CP ring */ #define RADEON_RING_TYPE_GFX_INDEX 0/* cayman has 2 compute CP rings */ #define CAYMAN_RING_TYPE_CP1_INDEX 1#define CAYMAN_RING_TYPE_CP2_INDEX 2/* R600+ has an async dma ring */ #define R600_RING_TYPE_DMA_INDEX 3/* cayman add a second async dma ring */ #define CAYMAN_RING_TYPE_DMA1_INDEX 4/* R600+ */ #define R600_RING_TYPE_UVD_INDEX 5/* TN+ */ #define TN_RING_TYPE_VCE1_INDEX 6#define TN_RING_TYPE_VCE2_INDEX 7/* max number of rings */ #define RADEON_NUM_RINGS 8/* number of hw syncs before falling back on blocking */ #define RADEON_NUM_SYNCS 4/* hardcode those limit for now */ #define RADEON_VA_IB_OFFSET (1 << 20)#define RADEON_VA_RESERVED_SIZE (8 << 20)#define RADEON_IB_VM_MAX_SIZE (64 << 10)/* hard reset data */ #define RADEON_ASIC_RESET_DATA 0x39d5e86b/* reset flags */ #define RADEON_RESET_GFX (1 << 0)#define RADEON_RESET_COMPUTE (1 << 1)#define RADEON_RESET_DMA (1 << 2)#define RADEON_RESET_CP (1 << 3)#define RADEON_RESET_GRBM (1 << 4)#define RADEON_RESET_DMA1 (1 << 5)#define RADEON_RESET_RLC (1 << 6)#define RADEON_RESET_SEM (1 << 7)#define RADEON_RESET_IH (1 << 8)#define RADEON_RESET_VMC (1 << 9)#define RADEON_RESET_MC (1 << 10)#define RADEON_RESET_DISPLAY (1 << 11)/* CG block flags */ #define RADEON_CG_BLOCK_GFX (1 << 0)#define RADEON_CG_BLOCK_MC (1 << 1)#define RADEON_CG_BLOCK_SDMA (1 << 2)#define RADEON_CG_BLOCK_UVD (1 << 3)#define RADEON_CG_BLOCK_VCE (1 << 4)#define RADEON_CG_BLOCK_HDP (1 << 5)#define RADEON_CG_BLOCK_BIF (1 << 6)/* CG flags */ #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)#define RADEON_CG_SUPPORT_MC_LS (1 << 8)#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)/* PG flags */ #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)#define RADEON_PG_SUPPORT_UVD (1 << 3)#define RADEON_PG_SUPPORT_VCE (1 << 4)#define RADEON_PG_SUPPORT_CP (1 << 5)#define RADEON_PG_SUPPORT_GDS (1 << 6)#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)#define RADEON_PG_SUPPORT_SDMA (1 << 8)#define RADEON_PG_SUPPORT_ACP (1 << 9)#define RADEON_PG_SUPPORT_SAMU (1 << 10)/* max cursor sizes (in pixels) */ #define CURSOR_WIDTH 64#define CURSOR_HEIGHT 64#define CIK_CURSOR_WIDTH 128#define CIK_CURSOR_HEIGHT 128/* * Errata workarounds. enum radeon_pll_errata {struct radeon_device;/* * BIOS. bool radeon_get_bios(struct radeon_device *rdev);/* * Dummy page struct radeon_dummy_page {struct page *page;int radeon_dummy_page_init(struct radeon_device *rdev);void radeon_dummy_page_fini(struct radeon_device *rdev);/* * Clocks struct radeon_clock {struct radeon_pll p1pll;struct radeon_pll p2pll;struct radeon_pll dcpll;struct radeon_pll spll;struct radeon_pll mpll;/* 10 Khz units */ /* * Power management int radeon_pm_init(struct radeon_device *rdev);int radeon_pm_late_init(struct radeon_device *rdev);void radeon_pm_fini(struct radeon_device *rdev);void radeon_pm_compute_clocks(struct radeon_device *rdev);void radeon_pm_suspend(struct radeon_device *rdev);void radeon_pm_resume(struct radeon_device *rdev);void radeon_combios_get_power_modes(struct radeon_device *rdev);void radeon_atombios_get_power_modes(struct radeon_device *rdev);int radeon_atom_get_clock_dividers(struct radeon_device *rdev,bool strobe_mode,struct atom_clock_dividers *dividers);int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,bool strobe_mode,struct atom_mpll_param *mpll_param);void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,int radeon_atom_get_voltage_step(struct radeon_device *rdev,int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,int radeon_atom_get_voltage_evv(struct radeon_device *rdev,int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,int radeon_atom_get_min_voltage(struct radeon_device *rdev,int radeon_atom_get_max_voltage(struct radeon_device *rdev,int radeon_atom_get_voltage_table(struct radeon_device *rdev,struct atom_voltage_table *voltage_table);bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,int radeon_atom_get_svi2_info(struct radeon_device *rdev,void radeon_atom_update_memory_dll(struct radeon_device *rdev,void radeon_atom_set_ac_timing(struct radeon_device *rdev,int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,struct atom_mc_reg_table *reg_table);int radeon_atom_get_memory_info(struct radeon_device *rdev,struct atom_memory_info *mem_info);int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,bool gddr5, u8 module_index,struct atom_memory_clock_range_table *mclk_range_table);int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,void rs690_pm_info(struct radeon_device *rdev);extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,unsigned *bankh, unsigned *mtaspect,unsigned *tile_split);/* * Fences. struct radeon_fence_driver {struct radeon_device *rdev;volatile uint32_t *cpu_addr;/* sync_seq is protected by ring emission lock */ bool initialized, delayed_irq;struct delayed_work lockup_work;struct radeon_fence {struct dma_fence base;struct radeon_device *rdev;/* RB, DMA, etc. */ unsigned ring;bool is_vm_update;int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);void radeon_fence_driver_init(struct radeon_device *rdev);void radeon_fence_driver_fini(struct radeon_device *rdev);void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);void radeon_fence_process(struct radeon_device *rdev, int ring);bool radeon_fence_signaled(struct radeon_fence *fence);long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);int radeon_fence_wait_next(struct radeon_device *rdev, int ring);int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);void radeon_fence_unref(struct radeon_fence **fence);unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);void radeon_fence_note_sync(struct radeon_fence *fence, int ring);static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,struct radeon_fence *b)if (!a) {return b;if (!b) {return a;if (a->seq > b->seq) {return a;else {return b;static inline bool radeon_fence_is_earlier(struct radeon_fence *a,struct radeon_fence *b)if (!a) {return false ;if (!b) {return true ;return a->seq < b->seq;/* * Tiling registers struct radeon_surface_reg {struct radeon_bo *bo;#define RADEON_GEM_MAX_SURFACES 8/* * TTM. struct radeon_mman {struct ttm_device bdev;bool initialized;struct radeon_bo_list {struct radeon_bo *robj;struct list_head list;bool shared;unsigned preferred_domains;unsigned allowed_domains;/* bo virtual address in a specific vm */ struct radeon_bo_va {/* protected by bo being reserved */ struct list_head bo_list;struct radeon_fence *last_pt_update;unsigned ref_count;/* protected by vm mutex */ struct interval_tree_node it;struct list_head vm_status;/* constant after initialization */ struct radeon_vm *vm;struct radeon_bo *bo;struct radeon_bo {/* Protected by gem.mutex */ struct list_head list;/* Protected by tbo.reserved */ struct ttm_place placements[4];struct ttm_placement placement;struct ttm_buffer_object tbo;struct ttm_bo_kmap_obj kmap;void *kptr;int surface_reg;unsigned prime_shared_count;/* list of all virtual address to which this bo * is associated to struct list_head va;/* Constant after initialization */ struct radeon_device *rdev;#ifdef CONFIG_MMU_NOTIFIERstruct mmu_interval_notifier notifier;#endif #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)struct radeon_sa_manager {struct drm_suballoc_manager base;struct radeon_bo *bo;void *cpu_ptr;/* * GEM objects. struct radeon_gem {struct mutex mutex;struct list_head objects;extern const struct drm_gem_object_funcs radeon_gem_object_funcs;int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);int radeon_gem_init(struct radeon_device *rdev);void radeon_gem_fini(struct radeon_device *rdev);int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,int alignment, int initial_domain,bool kernel,struct drm_gem_object **obj);int radeon_mode_dumb_create(struct drm_file *file_priv,struct drm_device *dev,struct drm_mode_create_dumb *args);int radeon_mode_dumb_mmap(struct drm_file *filp,struct drm_device *dev,/* * Semaphores. struct radeon_semaphore {struct drm_suballoc *sa_bo;signed waiters;int radeon_semaphore_create(struct radeon_device *rdev,struct radeon_semaphore **semaphore);bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,struct radeon_semaphore *semaphore);bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,struct radeon_semaphore *semaphore);void radeon_semaphore_free(struct radeon_device *rdev,struct radeon_semaphore **semaphore,struct radeon_fence *fence);/* * Synchronization struct radeon_sync {struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];struct radeon_fence *sync_to[RADEON_NUM_RINGS];struct radeon_fence *last_vm_update;void radeon_sync_create(struct radeon_sync *sync);void radeon_sync_fence(struct radeon_sync *sync,struct radeon_fence *fence);int radeon_sync_resv(struct radeon_device *rdev,struct radeon_sync *sync,struct dma_resv *resv,bool shared);int radeon_sync_rings(struct radeon_device *rdev,struct radeon_sync *sync,int waiting_ring);void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,struct radeon_fence *fence);/* * GART structures, functions & helpers struct radeon_mc;#define RADEON_GPU_PAGE_SIZE 4096#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)#define RADEON_GPU_PAGE_SHIFT 12#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)#define RADEON_GART_PAGE_DUMMY 0#define RADEON_GART_PAGE_VALID (1 << 0)#define RADEON_GART_PAGE_READ (1 << 1)#define RADEON_GART_PAGE_WRITE (1 << 2)#define RADEON_GART_PAGE_SNOOP (1 << 3)struct radeon_gart {struct radeon_bo *robj;void *ptr;unsigned num_gpu_pages;unsigned num_cpu_pages;unsigned table_size;struct page **pages;bool ready;int radeon_gart_table_ram_alloc(struct radeon_device *rdev);void radeon_gart_table_ram_free(struct radeon_device *rdev);int radeon_gart_table_vram_alloc(struct radeon_device *rdev);void radeon_gart_table_vram_free(struct radeon_device *rdev);int radeon_gart_table_vram_pin(struct radeon_device *rdev);void radeon_gart_table_vram_unpin(struct radeon_device *rdev);int radeon_gart_init(struct radeon_device *rdev);void radeon_gart_fini(struct radeon_device *rdev);void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,int pages);int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,int pages, struct page **pagelist,/* * GPU MC structures, functions & helpers struct radeon_mc {/* for some chips with <= 32MB we need to lie unsigned vram_width;int vram_mtrr;bool vram_is_ddr;bool igp_sideport_enabled;bool radeon_combios_sideport_present(struct radeon_device *rdev);bool radeon_atombios_sideport_present(struct radeon_device *rdev);/* * GPU scratch registers structures, functions & helpers struct radeon_scratch {unsigned num_reg;bool free[32];int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);/* * GPU doorbell structures, functions & helpers #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ struct radeon_doorbell {/* doorbell mmio */ /* Number of doorbells actually reserved for radeon. */ int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);/* * IRQS. struct radeon_flip_work {struct work_struct flip_work;struct work_struct unpin_work;struct radeon_device *rdev;int crtc_id;struct drm_pending_vblank_event *event;struct radeon_bo *old_rbo;struct dma_fence *fence;bool async;struct r500_irq_stat_regs {struct r600_irq_stat_regs {struct evergreen_irq_stat_regs {struct cik_irq_stat_regs {union radeon_irq_stat_regs {struct r500_irq_stat_regs r500;struct r600_irq_stat_regs r600;struct evergreen_irq_stat_regs evergreen;struct cik_irq_stat_regs cik;struct radeon_irq {bool installed;bool crtc_vblank_int[RADEON_MAX_CRTCS];bool hpd[RADEON_MAX_HPD_PINS];bool afmt[RADEON_MAX_AFMT_BLOCKS];union radeon_irq_stat_regs stat_regs;bool dpm_thermal;int radeon_irq_kms_init(struct radeon_device *rdev);void radeon_irq_kms_fini(struct radeon_device *rdev);void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);/* * CP & rings. struct radeon_ib {struct drm_suballoc *sa_bo;int ring;struct radeon_fence *fence;struct radeon_vm *vm;bool is_const_ib;struct radeon_sync sync;struct radeon_ring {struct radeon_device *rdev;struct radeon_bo *ring_obj;volatile uint32_t *ring;unsigned rptr_offs;unsigned rptr_save_reg;volatile u32 *next_rptr_cpu_addr;unsigned wptr;unsigned wptr_old;unsigned ring_size;unsigned ring_free_dw;int count_dw;bool ready;/* for CIK queues */ struct radeon_bo *mqd_obj;unsigned wptr_offs;struct radeon_mec {struct radeon_bo *hpd_eop_obj;/* * VM /* maximum number of VMIDs */ #define RADEON_NUM_VM 16/* number of entries in page table */ #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)/* PTBs (Page Table Blocks) need to be aligned to 32K */ #define RADEON_VM_PTB_ALIGN_SIZE 32768#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)#define R600_PTE_VALID (1 << 0)#define R600_PTE_SYSTEM (1 << 1)#define R600_PTE_SNOOPED (1 << 2)#define R600_PTE_READABLE (1 << 5)#define R600_PTE_WRITEABLE (1 << 6)/* PTE (Page Table Entry) fragment field for different page sizes */ #define R600_PTE_FRAG_4KB (0 << 7)#define R600_PTE_FRAG_64KB (4 << 7)#define R600_PTE_FRAG_256KB (6 << 7)/* flags needed to be set so we can copy directly from the GART table */ #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \struct radeon_vm_pt {struct radeon_bo *bo;struct radeon_vm_id {unsigned id;/* last flushed PD/PT update */ struct radeon_fence *flushed_updates;/* last use of vmid */ struct radeon_fence *last_id_use;struct radeon_vm {struct mutex mutex;struct rb_root_cached va;/* protecting invalidated and freed */ /* BOs moved, but not yet updated in the PT */ struct list_head invalidated;/* BOs freed, but not yet updated in the PT */ struct list_head freed;/* BOs cleared in the PT */ struct list_head cleared;/* contains the page directory */ struct radeon_bo *page_directory;unsigned max_pde_used;/* array of page tables, one for each page directory entry */ struct radeon_vm_pt *page_tables;struct radeon_bo_va *ib_bo_va;/* for id and flush management per ring */ struct radeon_vm_id ids[RADEON_NUM_RINGS];struct radeon_vm_manager {struct radeon_fence *active[RADEON_NUM_VM];/* number of VMIDs */ unsigned nvm;/* vram base address for page table entry */ /* is vm enabled? */ bool enabled;/* for hw to save the PD addr on suspend/resume */ /* * file private structure struct radeon_fpriv {struct radeon_vm vm;/* * R6xx+ IH ring struct r600_ih {struct radeon_bo *ring_obj;volatile uint32_t *ring;unsigned rptr;unsigned ring_size;bool enabled;/* * RLC stuff #include "clearstate_defs.h" struct radeon_rlc {/* for power gating */ struct radeon_bo *save_restore_obj;volatile uint32_t *sr_ptr;const u32 *reg_list;/* for clear state */ struct radeon_bo *clear_state_obj;volatile uint32_t *cs_ptr;const struct cs_section_def *cs_data;/* for cp tables */ struct radeon_bo *cp_table_obj;volatile uint32_t *cp_table_ptr;int radeon_ib_get(struct radeon_device *rdev, int ring,struct radeon_ib *ib, struct radeon_vm *vm,unsigned size);void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,struct radeon_ib *const_ib, bool hdp_flush);int radeon_ib_pool_init(struct radeon_device *rdev);void radeon_ib_pool_fini(struct radeon_device *rdev);int radeon_ib_ring_tests(struct radeon_device *rdev);/* Ring access between begin & end cannot sleep */ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,struct radeon_ring *ring);void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,bool hdp_flush);void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,bool hdp_flush);void radeon_ring_undo(struct radeon_ring *ring);void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);void radeon_ring_lockup_update(struct radeon_device *rdev,struct radeon_ring *ring);bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,unsigned size, uint32_t *data);int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,unsigned rptr_offs, u32 nop);void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);/* r600 async dma */ void r600_dma_stop(struct radeon_device *rdev);int r600_dma_resume(struct radeon_device *rdev);void r600_dma_fini(struct radeon_device *rdev);void cayman_dma_stop(struct radeon_device *rdev);int cayman_dma_resume(struct radeon_device *rdev);void cayman_dma_fini(struct radeon_device *rdev);/* * CS. struct radeon_cs_chunk {void __user *user_ptr;struct radeon_cs_parser {struct device *dev;struct radeon_device *rdev;struct drm_file *filp;/* chunks */ unsigned nchunks;struct radeon_cs_chunk *chunks;/* IB */ unsigned idx;/* relocations */ unsigned nrelocs;struct radeon_bo_list *relocs;struct radeon_bo_list *vm_bos;struct list_head validated;unsigned dma_reloc_idx;struct drm_exec exec;/* indices of various chunks */ struct radeon_cs_chunk *chunk_ib;struct radeon_cs_chunk *chunk_relocs;struct radeon_cs_chunk *chunk_flags;struct radeon_cs_chunk *chunk_const_ib;struct radeon_ib ib;struct radeon_ib const_ib;void *track;unsigned family;int parser_error;static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)struct radeon_cs_chunk *ibc = p->chunk_ib;if (ibc->kdata)return ibc->kdata[idx];return p->ib.ptr[idx];struct radeon_cs_packet {unsigned idx;unsigned type;unsigned reg;unsigned opcode;int count;unsigned one_reg_wr;typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,struct radeon_cs_packet *pkt,unsigned idx, unsigned reg);/* * AGP struct radeon_agp_mode {unsigned long mode; /**< AGP mode */ struct radeon_agp_info {int agp_version_major;int agp_version_minor;unsigned long mode;unsigned long aperture_base; /* physical address */ unsigned long aperture_size; /* bytes */ unsigned long memory_allowed; /* bytes */ unsigned long memory_used;/* PCI information */ unsigned short id_vendor;unsigned short id_device;struct radeon_agp_head {struct agp_kern_info agp_info;struct list_head memory;unsigned long mode;struct agp_bridge_data *bridge;int enabled;int acquired;unsigned long base;int agp_mtrr;int cant_use_aperture;unsigned long page_mask;#if IS_ENABLED(CONFIG_AGP)struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);#else static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)return NULL;#endif int radeon_agp_init(struct radeon_device *rdev);void radeon_agp_resume(struct radeon_device *rdev);void radeon_agp_suspend(struct radeon_device *rdev);void radeon_agp_fini(struct radeon_device *rdev);/* * Writeback struct radeon_wb {struct radeon_bo *wb_obj;volatile uint32_t *wb;bool enabled;bool use_event;#define RADEON_WB_SCRATCH_OFFSET 0#define RADEON_WB_RING0_NEXT_RPTR 256#define RADEON_WB_CP_RPTR_OFFSET 1024#define RADEON_WB_CP1_RPTR_OFFSET 1280#define RADEON_WB_CP2_RPTR_OFFSET 1536#define R600_WB_DMA_RPTR_OFFSET 1792#define R600_WB_IH_WPTR_OFFSET 2048#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304#define R600_WB_EVENT_OFFSET 3072#define CIK_WB_CP1_WPTR_OFFSET 3328#define CIK_WB_CP2_WPTR_OFFSET 3584#define R600_WB_DMA_RING_TEST_OFFSET 3588#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592/** * struct radeon_pm - power management datas * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) * @sclk: GPU clock Mhz (core bandwidth depends of this clock) * @needed_bandwidth: current bandwidth needs * * It keeps track of various data needed to take powermanagement decision. * Bandwidth need is used to determine minimun clock of the GPU and memory. * Equation between gpu/memory clock and available bandwidth is hw dependent * (type of memory, bus size, efficiency, ...) enum radeon_pm_method {enum radeon_dynpm_state {enum radeon_dynpm_action {enum radeon_voltage_type {enum radeon_pm_state_type {/* not used for dpm */ /* user selectable states */ /* internal states */ enum radeon_pm_profile_type {#define PM_PROFILE_DEFAULT_IDX 0#define PM_PROFILE_LOW_SH_IDX 1#define PM_PROFILE_MID_SH_IDX 2#define PM_PROFILE_HIGH_SH_IDX 3#define PM_PROFILE_LOW_MH_IDX 4#define PM_PROFILE_MID_MH_IDX 5#define PM_PROFILE_HIGH_MH_IDX 6#define PM_PROFILE_MAX 7struct radeon_pm_profile {int dpms_off_ps_idx;int dpms_on_ps_idx;int dpms_off_cm_idx;int dpms_on_cm_idx;enum radeon_int_thermal_type {struct radeon_voltage {enum radeon_voltage_type type;/* gpio voltage */ struct radeon_gpio_rec gpio;/* delay in usec from voltage drop to sclk change */ bool active_high; /* voltage drop is active when bit is high */ /* VDDC voltage */ /* index into vddc voltage table */ /* index into vddci voltage table */ bool vddci_enabled;/* r6xx+ sw */ /* evergreen+ vddci */ /* clock mode flags */ #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)struct radeon_pm_clock_info {/* memory clock */ /* engine clock */ /* voltage info */ struct radeon_voltage voltage;/* standardized clock flags */ /* state flags */ #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)struct radeon_power_state {enum radeon_pm_state_type type;struct radeon_pm_clock_info *clock_info;/* number of valid clock modes in this power state */ int num_clock_modes;struct radeon_pm_clock_info *default_clock_mode;/* standardized state flags */ /* vbios specific flags */ /* vbios specific flags */ int pcie_lanes; /* pcie lanes */ /* * Some modes are overclocked by very low value, accept them #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ enum radeon_dpm_auto_throttle_src {enum radeon_dpm_event_src {#define RADEON_MAX_VCE_LEVELS 6enum radeon_vce_level {/* AC, All cases */ /* DC, entropy encoding */ /* DC, low latency queue, res <= 720 */ /* DC, low latency queue, 1080 >= res > 720 */ /* DC, general purpose queue, res <= 720 */ /* DC, general purpose queue, 1080 >= res > 720 */ struct radeon_ps {/* vbios flags */ class ; /* vbios flags */ /* vbios flags */ /* UVD clocks */ /* VCE clocks */ bool vce_active;enum radeon_vce_level vce_level;/* asic priv */ void *ps_priv;struct radeon_dpm_thermal {/* thermal interrupt work */ struct work_struct work;/* low temperature threshold */ int min_temp;/* high temperature threshold */ int max_temp;/* was interrupt low to high or high to low */ bool high_to_low;enum radeon_clk_action {struct radeon_blacklist_clocks {enum radeon_clk_action action;struct radeon_clock_and_voltage_limits {struct radeon_clock_array {struct radeon_clock_voltage_dependency_entry {struct radeon_clock_voltage_dependency_table {struct radeon_clock_voltage_dependency_entry *entries;union radeon_cac_leakage_entry {struct {struct {struct radeon_cac_leakage_table {union radeon_cac_leakage_entry *entries;struct radeon_phase_shedding_limits_entry {struct radeon_phase_shedding_limits_table {struct radeon_phase_shedding_limits_entry *entries;struct radeon_uvd_clock_voltage_dependency_entry {struct radeon_uvd_clock_voltage_dependency_table {struct radeon_uvd_clock_voltage_dependency_entry *entries;struct radeon_vce_clock_voltage_dependency_entry {struct radeon_vce_clock_voltage_dependency_table {struct radeon_vce_clock_voltage_dependency_entry *entries;struct radeon_ppm_table {struct radeon_cac_tdp_table {struct radeon_dpm_dynamic_state {struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;struct radeon_clock_array valid_sclk_values;struct radeon_clock_array valid_mclk_values;struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;struct radeon_cac_leakage_table cac_leakage_table;struct radeon_phase_shedding_limits_table phase_shedding_limits_table;struct radeon_ppm_table *ppm_table;struct radeon_cac_tdp_table *cac_tdp_table;struct radeon_dpm_fan {bool ucode_fan_control;enum radeon_pcie_gen {enum radeon_dpm_forced_level {struct radeon_vce_state {/* vce clocks */ /* gpu clocks */ struct radeon_dpm {struct radeon_ps *ps;/* number of valid power states */ int num_ps;/* current power state that is active */ struct radeon_ps *current_ps;/* requested power state */ struct radeon_ps *requested_ps;/* boot up power state */ struct radeon_ps *boot_ps;/* default uvd power state */ struct radeon_ps *uvd_ps;/* vce requirements */ struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];enum radeon_vce_level vce_level;enum radeon_pm_state_type state;enum radeon_pm_state_type user_state;void *priv;int new_active_crtc_count;int high_pixelclock_count;int current_active_crtc_count;bool single_display;struct radeon_dpm_dynamic_state dyn_state;struct radeon_dpm_fan fan;bool power_control;bool ac_power;/* special states active */ bool thermal_active;bool uvd_active;bool vce_active;/* thermal handling */ struct radeon_dpm_thermal thermal;/* forced levels */ enum radeon_dpm_forced_level forced_level;/* track UVD streams */ unsigned sd;unsigned hd;void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);struct radeon_pm {struct mutex mutex;/* write locked while reprogramming mclk */ struct rw_semaphore mclk_lock;int active_crtc_count;int req_vblank;bool vblank_sync;struct radeon_power_state *power_state;/* number of valid power states */ int num_power_states;int current_power_state_index;int current_clock_mode_index;int requested_power_state_index;int requested_clock_mode_index;int default_power_state_index;struct radeon_i2c_chan *i2c_bus;/* selected pm method */ enum radeon_pm_method pm_method;/* dynpm power management */ struct delayed_work dynpm_idle_work;enum radeon_dynpm_state dynpm_state;enum radeon_dynpm_action dynpm_planned_action;unsigned long dynpm_action_timeout;bool dynpm_can_upclock;bool dynpm_can_downclock;/* profile-based power management */ enum radeon_pm_profile_type profile;int profile_index;struct radeon_pm_profile profiles[PM_PROFILE_MAX];/* internal thermal controller on rv6xx+ */ enum radeon_int_thermal_type int_thermal_type;struct device *int_hwmon_dev;/* fan control parameters */ bool no_fan;/* dpm */ bool dpm_enabled;bool sysfs_initialized;struct radeon_dpm dpm;#define RADEON_PCIE_SPEED_25 1#define RADEON_PCIE_SPEED_50 2#define RADEON_PCIE_SPEED_80 4int radeon_pm_get_type_index(struct radeon_device *rdev,enum radeon_pm_state_type ps_type,int instance);/* * UVD #define RADEON_DEFAULT_UVD_HANDLES 10#define RADEON_MAX_UVD_HANDLES 30#define RADEON_UVD_STACK_SIZE (200*1024)#define RADEON_UVD_HEAP_SIZE (256*1024)#define RADEON_UVD_SESSION_SIZE (50*1024)struct radeon_uvd {bool fw_header_present;struct radeon_bo *vcpu_bo;void *cpu_addr;unsigned max_handles;struct drm_file *filp[RADEON_MAX_UVD_HANDLES];unsigned img_size[RADEON_MAX_UVD_HANDLES];struct delayed_work idle_work;int radeon_uvd_init(struct radeon_device *rdev);void radeon_uvd_fini(struct radeon_device *rdev);int radeon_uvd_suspend(struct radeon_device *rdev);int radeon_uvd_resume(struct radeon_device *rdev);int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,struct radeon_fence **fence);int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,struct radeon_fence **fence);void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,void radeon_uvd_free_handles(struct radeon_device *rdev,struct drm_file *filp);int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);void radeon_uvd_note_usage(struct radeon_device *rdev);int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,unsigned vclk, unsigned dclk,unsigned vco_min, unsigned vco_max,unsigned fb_factor, unsigned fb_mask,unsigned pd_min, unsigned pd_max,unsigned pd_even,unsigned *optimal_fb_div,unsigned *optimal_vclk_div,unsigned *optimal_dclk_div);int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,unsigned cg_upll_func_cntl);/* * VCE #define RADEON_MAX_VCE_HANDLES 16struct radeon_vce {struct radeon_bo *vcpu_bo;unsigned fw_version;unsigned fb_version;struct drm_file *filp[RADEON_MAX_VCE_HANDLES];unsigned img_size[RADEON_MAX_VCE_HANDLES];struct delayed_work idle_work;int radeon_vce_init(struct radeon_device *rdev);void radeon_vce_fini(struct radeon_device *rdev);int radeon_vce_suspend(struct radeon_device *rdev);int radeon_vce_resume(struct radeon_device *rdev);int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,struct radeon_fence **fence);int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,struct radeon_fence **fence);void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);void radeon_vce_note_usage(struct radeon_device *rdev);int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);int radeon_vce_cs_parse(struct radeon_cs_parser *p);bool radeon_vce_semaphore_emit(struct radeon_device *rdev,struct radeon_ring *ring,struct radeon_semaphore *semaphore,bool emit_wait);void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);void radeon_vce_fence_emit(struct radeon_device *rdev,struct radeon_fence *fence);int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);struct r600_audio_pin {int channels;int rate;int bits_per_sample;bool connected;struct r600_audio {bool enabled;struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];int num_pins;struct radeon_audio_funcs *hdmi_funcs;struct radeon_audio_funcs *dp_funcs;struct radeon_audio_basic_funcs *funcs;struct drm_audio_component *component;bool component_registered;struct mutex component_mutex;/* * Benchmarking void radeon_benchmark(struct radeon_device *rdev, int test_number);/* * Testing void radeon_test_moves(struct radeon_device *rdev);void radeon_test_ring_sync(struct radeon_device *rdev,struct radeon_ring *cpA,struct radeon_ring *cpB);void radeon_test_syncing(struct radeon_device *rdev);/* * MMU Notifier #if defined (CONFIG_MMU_NOTIFIER)int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);void radeon_mn_unregister(struct radeon_bo *bo);#else static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)return -ENODEV;static inline void radeon_mn_unregister(struct radeon_bo *bo) {}#endif /* * Debugfs void radeon_debugfs_fence_init(struct radeon_device *rdev);void radeon_gem_debugfs_init(struct radeon_device *rdev);/* * ASIC ring specific functions. struct radeon_asic_ring {/* ring read/write ptr handling */ struct radeon_device *rdev, struct radeon_ring *ring);struct radeon_device *rdev, struct radeon_ring *ring);void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);/* validating and patching of IBs */ int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);int (*cs_parse)(struct radeon_cs_parser *p);/* command emmit functions */ void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,struct radeon_semaphore *semaphore, bool emit_wait);void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,unsigned vm_id, uint64_t pd_addr);/* testing functions */ int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);/* deprecated */ void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);/* * ASIC specific functions. struct radeon_asic {int (*init)(struct radeon_device *rdev);void (*fini)(struct radeon_device *rdev);int (*resume)(struct radeon_device *rdev);int (*suspend)(struct radeon_device *rdev);void (*vga_set_state)(struct radeon_device *rdev, bool state);int (*asic_reset)(struct radeon_device *rdev, bool hard);/* Flush the HDP cache via MMIO */ void (*mmio_hdp_flush)(struct radeon_device *rdev);/* check if 3D engine is idle */ bool (*gui_idle)(struct radeon_device *rdev);/* wait for mc_idle */ int (*mc_wait_for_idle)(struct radeon_device *rdev);/* get the reference clock */ struct radeon_device *rdev);/* get the gpu clock counter */ struct radeon_device *rdev);/* get register for info ioctl */ int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);/* gart */ struct {void (*tlb_flush)(struct radeon_device *rdev);void (*set_page)(struct radeon_device *rdev, unsigned i,struct {int (*init)(struct radeon_device *rdev);void (*fini)(struct radeon_device *rdev);void (*copy_pages)(struct radeon_device *rdev,struct radeon_ib *ib,unsigned count);void (*write_pages)(struct radeon_device *rdev,struct radeon_ib *ib,unsigned count,void (*set_pages)(struct radeon_device *rdev,struct radeon_ib *ib,unsigned count,void (*pad_ib)(struct radeon_ib *ib);/* ring specific callbacks */ const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];/* irqs */ struct {int (*set)(struct radeon_device *rdev);int (*process)(struct radeon_device *rdev);/* displays */ struct {/* display watermarks */ void (*bandwidth_update)(struct radeon_device *rdev);/* get frame count */ struct radeon_device *rdev, int crtc);/* wait for vblank */ void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);/* set backlight level */ void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);/* get backlight level */ struct radeon_encoder *radeon_encoder);/* audio callbacks */ void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);/* copy functions for bo handling */ struct {struct radeon_fence *(*blit)(struct radeon_device *rdev,unsigned num_gpu_pages,struct dma_resv *resv);struct radeon_fence *(*dma)(struct radeon_device *rdev,unsigned num_gpu_pages,struct dma_resv *resv);/* method used for bo copy */ struct radeon_fence *(*copy)(struct radeon_device *rdev,unsigned num_gpu_pages,struct dma_resv *resv);/* ring used for bo copies */ /* surfaces */ struct {int (*set_reg)(struct radeon_device *rdev, int reg,void (*clear_reg)(struct radeon_device *rdev, int reg);/* hotplug detect */ struct {void (*init)(struct radeon_device *rdev);void (*fini)(struct radeon_device *rdev);bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);/* static power management */ struct {void (*misc)(struct radeon_device *rdev);void (*prepare)(struct radeon_device *rdev);void (*finish)(struct radeon_device *rdev);void (*init_profile)(struct radeon_device *rdev);void (*get_dynpm_state)(struct radeon_device *rdev);struct radeon_device *rdev);void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);struct radeon_device *rdev);void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);int (*get_pcie_lanes)(struct radeon_device *rdev);void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);void (*set_clock_gating)(struct radeon_device *rdev, int enable);int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);int (*get_temperature)(struct radeon_device *rdev);/* dynamic power management */ struct {int (*init)(struct radeon_device *rdev);void (*setup_asic)(struct radeon_device *rdev);int (*enable)(struct radeon_device *rdev);int (*late_enable)(struct radeon_device *rdev);void (*disable)(struct radeon_device *rdev);int (*pre_set_power_state)(struct radeon_device *rdev);int (*set_power_state)(struct radeon_device *rdev);void (*post_set_power_state)(struct radeon_device *rdev);void (*display_configuration_changed)(struct radeon_device *rdev);void (*fini)(struct radeon_device *rdev);struct radeon_device *rdev, bool low);struct radeon_device *rdev, bool low);void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);bool (*vblank_too_short)(struct radeon_device *rdev);void (*powergate_uvd)(struct radeon_device *rdev, bool gate);void (*enable_bapm)(struct radeon_device *rdev, bool enable);void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);struct radeon_device *rdev);int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);struct radeon_device *rdev);struct radeon_device *rdev);struct radeon_device *rdev);/* pageflipping */ struct {void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);/* * Asic structures struct r100_asic {const unsigned *reg_safe_bm;unsigned reg_safe_bm_size;struct r300_asic {const unsigned *reg_safe_bm;unsigned reg_safe_bm_size;struct r600_asic {unsigned max_pipes;unsigned max_tile_pipes;unsigned max_simds;unsigned max_backends;unsigned max_gprs;unsigned max_threads;unsigned max_stack_entries;unsigned max_hw_contexts;unsigned max_gs_threads;unsigned sx_max_export_size;unsigned sx_max_export_pos_size;unsigned sx_max_export_smx_size;unsigned sq_num_cf_insts;unsigned tiling_nbanks;unsigned tiling_npipes;unsigned tiling_group_size;unsigned tile_config;unsigned backend_map;unsigned active_simds;struct rv770_asic {unsigned max_pipes;unsigned max_tile_pipes;unsigned max_simds;unsigned max_backends;unsigned max_gprs;unsigned max_threads;unsigned max_stack_entries;unsigned max_hw_contexts;unsigned max_gs_threads;unsigned sx_max_export_size;unsigned sx_max_export_pos_size;unsigned sx_max_export_smx_size;unsigned sq_num_cf_insts;unsigned sx_num_of_sets;unsigned sc_prim_fifo_size;unsigned sc_hiz_tile_fifo_size;unsigned sc_earlyz_tile_fifo_fize;unsigned tiling_nbanks;unsigned tiling_npipes;unsigned tiling_group_size;unsigned tile_config;unsigned backend_map;unsigned active_simds;struct evergreen_asic {unsigned num_ses;unsigned max_pipes;unsigned max_tile_pipes;unsigned max_simds;unsigned max_backends;unsigned max_gprs;unsigned max_threads;unsigned max_stack_entries;unsigned max_hw_contexts;unsigned max_gs_threads;unsigned sx_max_export_size;unsigned sx_max_export_pos_size;unsigned sx_max_export_smx_size;unsigned sq_num_cf_insts;unsigned sx_num_of_sets;unsigned sc_prim_fifo_size;unsigned sc_hiz_tile_fifo_size;unsigned sc_earlyz_tile_fifo_size;unsigned tiling_nbanks;unsigned tiling_npipes;unsigned tiling_group_size;unsigned tile_config;unsigned backend_map;unsigned active_simds;struct cayman_asic {unsigned max_shader_engines;unsigned max_pipes_per_simd;unsigned max_tile_pipes;unsigned max_simds_per_se;unsigned max_backends_per_se;unsigned max_texture_channel_caches;unsigned max_gprs;unsigned max_threads;unsigned max_gs_threads;unsigned max_stack_entries;unsigned sx_num_of_sets;unsigned sx_max_export_size;unsigned sx_max_export_pos_size;unsigned sx_max_export_smx_size;unsigned max_hw_contexts;unsigned sq_num_cf_insts;unsigned sc_prim_fifo_size;unsigned sc_hiz_tile_fifo_size;unsigned sc_earlyz_tile_fifo_size;unsigned num_shader_engines;unsigned num_shader_pipes_per_simd;unsigned num_tile_pipes;unsigned num_simds_per_se;unsigned num_backends_per_se;unsigned backend_disable_mask_per_asic;unsigned backend_map;unsigned num_texture_channel_caches;unsigned mem_max_burst_length_bytes;unsigned mem_row_size_in_kb;unsigned shader_engine_tile_size;unsigned num_gpus;unsigned multi_gpu_tile_size;unsigned tile_config;unsigned active_simds;struct si_asic {unsigned max_shader_engines;unsigned max_tile_pipes;unsigned max_cu_per_sh;unsigned max_sh_per_se;unsigned max_backends_per_se;unsigned max_texture_channel_caches;unsigned max_gprs;unsigned max_gs_threads;unsigned max_hw_contexts;unsigned sc_prim_fifo_size_frontend;unsigned sc_prim_fifo_size_backend;unsigned sc_hiz_tile_fifo_size;unsigned sc_earlyz_tile_fifo_size;unsigned num_tile_pipes;unsigned backend_enable_mask;unsigned backend_disable_mask_per_asic;unsigned backend_map;unsigned num_texture_channel_caches;unsigned mem_max_burst_length_bytes;unsigned mem_row_size_in_kb;unsigned shader_engine_tile_size;unsigned num_gpus;unsigned multi_gpu_tile_size;unsigned tile_config;struct cik_asic {unsigned max_shader_engines;unsigned max_tile_pipes;unsigned max_cu_per_sh;unsigned max_sh_per_se;unsigned max_backends_per_se;unsigned max_texture_channel_caches;unsigned max_gprs;unsigned max_gs_threads;unsigned max_hw_contexts;unsigned sc_prim_fifo_size_frontend;unsigned sc_prim_fifo_size_backend;unsigned sc_hiz_tile_fifo_size;unsigned sc_earlyz_tile_fifo_size;unsigned num_tile_pipes;unsigned backend_enable_mask;unsigned backend_disable_mask_per_asic;unsigned backend_map;unsigned num_texture_channel_caches;unsigned mem_max_burst_length_bytes;unsigned mem_row_size_in_kb;unsigned shader_engine_tile_size;unsigned num_gpus;unsigned multi_gpu_tile_size;unsigned tile_config;union radeon_asic_config {struct r300_asic r300;struct r100_asic r100;struct r600_asic r600;struct rv770_asic rv770;struct evergreen_asic evergreen;struct cayman_asic cayman;struct si_asic si;struct cik_asic cik;/* * asic initizalization from radeon_asic.c void radeon_agp_disable(struct radeon_device *rdev);int radeon_asic_init(struct radeon_device *rdev);/* * IOCTL. int radeon_gem_info_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_create_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,struct drm_file *file_priv);int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,struct drm_file *file_priv);int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_va_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_op_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,struct drm_file *filp);int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Messung V0.5 C=92 H=97 G=94
¤ Dauer der Verarbeitung: 0.29 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
