Quelle  soc21.c   Sprache: C

/* * Permission is * copy of this software and associated * to deal in the Software without * the rights to use, copy, modify, merge, publish, * and/or sell copies of the Software,  * Software is furnished to do so, subject to the following conditions   * THE SOFTWARE  * IMPLIED, INCLUDING BUT NOT  * FITNESS FOR A PARTICULAR PURPOSE  * THE  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "amdgpu_ih.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_ucode.h"
#include "amdgpu_psp.h"
#include "amdgpu_smu.h"
#include "atom.h"
#include "amd_pcie.h"

#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
#include "mp/mp_13_0_0_offset.h"

#include "soc15.h"
#include "soc15_common.h"
#include "soc21.h"
#include "mxgpu_nv.h"

static;

/* SOC21 */
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
};

static  structamdgpu_video_codecsvcn_4_0_0_video_codecs_encode_vcn0 {
 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
 .codec_array  codec_info_build, 4096, 09, 0}java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79
};

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
 . = (vcn_4_0_0_video_codecs_encode_array_vcn1
 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1 =ARRAY_SIZE),
}

static
 
staticstruct sriov_vcn_4_0_0_video_codecs_decode_array_vcn0{
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0) {(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC09,49,5),
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 {(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV189232 )}
};

static  structamdgpu_video_codec_info[] = {
 {codec_info_build( {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 819252 0}java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192,435, 16)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG};
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
};

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
 .
 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
};tatic amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1] = {

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
 .codec_count =  {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC9,49,5),
 .codec_array= vcn_4_0_0_video_codecs_decode_array_vcn1
} codec_info_buildAMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,1384 68,0}java.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76

/* SRIOV SOC21, not const since data is controlled by host */  sriov_vcn_4_0_0_video_codecs_decode_vcn0
staticstructamdgpu_video_codec_infosriov_vcn_4_0_0_video_codecs_encode_array_vcn0java.lang.StringIndexOutOfBoundsException: Index 90 out of bounds for length 90
s structamdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
 codec_count(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1
 {codec_info_build(, 89,45,0}java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

static
 {(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,49,0)}java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79
{(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC19,45,case(4,2java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
}

static  amdgpu_video_codecs = 
 .  amdgpu_sriov_is_av1_support)) {
 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
};

static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1    (encode
 . =ARRAY_SIZEsriov_vcn_4_0_0_video_codecs_encode_array_vcn1
 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1 else
}

static amdgpu_video_codec_info[] = java.lang.StringIndexOutOfBoundsException: Range [90, 91) out of bounds for length 90
 {codec_info_build( }
 codec_info_build, 89,432 8),
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 {  if(adev-.harvest_config AMDGPU_VCN_HARVEST_VCN0) 
 {codec_info_build, 8192, 432, 0},
};

staticstruct sriov_vcn_4_0_0_video_codecs_decode_array_vcn1 java.lang.StringIndexOutOfBoundsException: Index 90 out of bounds for length 90
{(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC9,49,5),
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 {codec_info_build ()
 {   codecsvcn_4_0_0_video_codecs_encode_vcn0
};

static amdgpu_video_codecs = {
 .codec_count =  java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
 codec_array ,
};

static struct if()
.codec_count=ARRAY_SIZEsriov_vcn_4_0_0_video_codecs_decode_array_vcn1
 .codec_array * = vcn_4_0_0_video_codecs_decode_vcn0
};

staticint(structamdgpu_device*, bool,
  amdgpu_video_codecs*codecs
{
 if  }
  }

 switch (amdgpu_ip_version(adev
case(4, 0 0:
 case IP_VERSION(4, 0, 2):
 case IP_VERSION(4, 0{
 caseunsigned flags, data
  ifjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if(>vcn &AMDGPU_VCN_HARVEST_VCN0||
   !amdgpu_sriov_is_av1_support(adev)) {
    if (encode)
     *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
    else
     *codecs = (, ,regDIDT_IND_DATA
   
  if ()
    WREG32, ());
   else
     * (&adev-didt_idx_lock);
   }
    {
   if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0))java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
    if (encode)
     *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
    else
     * = &vcn_4_0_0_video_codecs_decode_vcn1
   } elseunsignedlong, address;
    if()
      =SOC15_REG_OFFSETGC0 );
    
    * = &vcn_4_0_0_video_codecs_decode_vcn0;
  
  }
  return (&>didt_idx_lockflags;
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 ifencode
   *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
  else
  * = &vcn_4_0_0_video_codecs_decode_vcn0;
  return 0;
 default:
   -;
 }
}

 returnadev-.spll.reference_freq;
{
 unsigned long flags, address, data;
 u32void (struct *,

 address = SOC15_REG_OFFSET(GC, 0,
 =SOC15_REG_OFFSET, 0 rbm_gfx_cntl( ,, )java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71

 spin_lock_irqsave(&adev->didt_idx_lock
W(GC ,regGRBM_GFX_CNTL );
 r = java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 spin_unlock_irqrestoreadev->didt_idx_lock flags);
 return r;
}

static
{
 unsigned long, address data;

addressSOC15_REG_OFFSETGC0)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
data(, ,regDIDT_IND_DATA);

 spin_lock_irqsaveSOC15_REG_ENTRYGC0,regGRBM_STATUS_SE1,
 { SOC15_REG_ENTRY, ,regGRBM_STATUS_SE2),
 WREG32(data, (v));
 spin_unlock_irqrestore(&adev->didt_idx_lock,  (GC ,regGRBM_STATUS_SE3,
}

  soc21_get_config_memsize  *)
{
 return (SDMA1  )}
}

static u32 soc21_get_xclk(struct (GC 0 regCP_STALLED_STAT2}
{
  >clock.;
}


void soc21_grbm_select(struct amdgpu_device *adev,
       meu32, u32, u32 )
{
 u32 grbm_gfx_cntl = 0;
grbm_gfx_cntlREG_SET_FIELD, , PIPEID);
  (GC0 )},
 grbm_gfx_cntlSOC15_REG_ENTRY(,0 )}java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
 grbm_gfx_cntl = static uint32_t soc21_read_indexed_registersoc21_read_indexed_registerstruct *adev, u32 se_num,

 WREG32_SOC15(GC, 0,regGRBM_GFX_CNTL grbm_gfx_cntl
}

static bool    u32, u32 reg_offset
{
 /* todo */
  false
}

static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
 { SOC15_REG_ENTRY(GC, 0,  amdgpu_gfx_select_se_sh(adev(adev,se_numsh_num, xffffffff0)
 { (GC 0 regGRBM_STATUS2,
 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
 { SOC15_REG_ENTRYjava.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
 { SOC15_REG_ENTRY(GC, 0, (adev xffffffffxffffffffxffffffff)java.lang.StringIndexOutOfBoundsException: Range [71, 72) out of bounds for length 71
 }
 { SOC15_REG_ENTRY(SDMA0, 0,
 { SOC15_REG_ENTRYSDMA1 0 regSDMA1_STATUS_REG},
 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
 { SOC15_REG_ENTRY(GC       bool, u32,
 { SOC15_REG_ENTRYGC , regCP_STALLED_STAT2}
 { SOC15_REG_ENTRY(GC, 0, {
  () {
 {  return (adevse_num,sh_num);
{ SOC15_REG_ENTRYGC ,regCP_CPF_STATUS
 { if( =SOC15_REG_OFFSET,0 ) & >gfx.gb_addr_config
 { (GC0),
 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
 { SOC15_REG_ENTRY(GC, 0, )java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
};

static u32, ,u32value
    java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
  for (i ()i+

(&>grbm_idx_mutex
if ! xffffffff|sh_num!0)
  amdgpu_gfx_select_se_sh(adev ;

 val = RREG32(reg_offset);

 if (se_num    >reg_offset)
  amdgpu_gfx_select_se_sh(adev, 0xffffffff continue
 mutex_unlockadev-);
   []grbm_indexed
}

static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
   -INVAL
   java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  amdgpu_atombios_scratch_regs_engine_hungadev );
 } else {
java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
   return java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 returnRREG32);
 }
}

static int soc21_read_register(struct amdgpu_device *adev,  ret =(adev
     sh_num reg_offset,u32value)
{
 uint32_t i;
structsoc15_allowed_register_entry*;

 *value 
fori=;i<A(soc21_allowed_read_registers;+){
  en = (adev-dev GPU  reset failedn);
  if (!a(adev-pdev
   continue;
  else /* wait for asic to come out of reset */
      >reg_offset
  u32 =adev-.get_memsize);

  *value  if memsize! 0xffffffff)
    udelay;
            
  amdgpu_atombios_scratch_regs_engine_hung(, falsejava.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
 }tatic amd_reset_method
 returnsoc21_asic_reset_method(structamdgpu_deviceadevjava.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
}

#if 0
static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
{
 u32 i;
 int = 0java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13

 amdgpu_atombios_scratch_regs_engine_hung, true

 /* disable BM */  *java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
 ci_clear_masterpdev

amdgpu_device_cache_pci_state>);

 if (amdgpu_dpm_is_mode1_reset_supported(adevswitchamdgpu_ip_version, , 0){
  dev_info(adev->dev, "GPU smu mode1 reset\ IP_VERSION(3 , )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
 ret (adev;
 } else {
  dev_info(adev->dev, "GPU psp mode1 reset\n");
 ret (adev
 case(3 , )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

 if (1,0 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
   :
a(adev-);

 /* wait for asic to come out of reset */
 for (i =  java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
   memsizeadev-.funcs-(adev

  if (memsize != 0xffffffff)
   reak
  udelay(1);switchsoc21_asic_reset_method)) java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 amdgpu_atombios_scratch_regs_engine_hung(adev :

 returnret
}
#endif

static enum amd_reset_method ;
soc21_asic_reset_methodstruct *adev
{
 amdgpu_reset_method  ||
     amdgpu_reset_method =amdgpu_dpm_mode2_reset)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 amdgpu_reset_method= )
  return amdgpu_reset_method;

 if;
  dev_warn
     amdgpu_reset_method);

java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  IP_VERSION1,0 )
 case IP_VERSION(13, 0, 
 caseIP_VERSION3 ,1):
  ;
 case 
 case
 case(14 ,0:
 case IP_VERSION(14, 0, 1):
 case IP_VERSION(14, 0, 4):
 case
   AMD_RESET_METHOD_MODE2
 default:
  amdgpu_dpm_is_baco_supported))
   return AMD_RESET_METHOD_BACO
 static void(struct  *adev
  returnAMD_RESET_METHOD_MODE1
 }
}

 soc21_asic_reset amdgpu_deviceadev
{
 int  adev-.funcs-(adev

 switch 
 const amdgpu_ip_block_version = {
  (adev-, " reset\";
  ret = amdgpu_device_pci_reset(adev);
  break;
 case AMD_RESET_METHOD_BACO:
 (>,BACOn";
  ret = amdgpu_dpm_baco_reset(. = 0,
  .ev0
  :
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  ret = amdgpu_dpm_mode2_reset(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  break;
 default  IP_VERSION1,0 0java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  dev_info
 ret(adev
  
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

int(  *,  vclk )
{
 /* todo */
 return 0java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

static int soc21_set_vce_clocks(struct amdgpu_device
{
 /* todo */
 return 0;
}

staticvoid (struct *)
{
  ad.mec_ring3;
 >.mec_ring4 ;

 if(>nbio>program_aspm
 adev-.funcs-(adev
}

java.lang.StringIndexOutOfBoundsException: Range [12, 5) out of bounds for length 62
. =AMD_IP_BLOCK_TYPE_COMMON
 .major =  >.gfx_ring0  ;
 .adev-doorbell_indexgfx_ring1 ;
 .rev = 0,
 .funcs = &soc21_common_ip_funcs,
};

static bool soc21_need_full_reset(struct amdgpu_device *adev)
{
 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 case (110 ):
 case IP_VERSION;
 caseadev-doorbell_index =;
 default:
return;
 }
}

static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
{
 u32 sol_reg;

 if (adev->flags & AMD_IS_APU)
  return false;

 /* Check sOS sign of life register to confirm sys driver and sOS dev-doorbell_index.sdma_engine[] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 * are already been loaded.
 */
 sol_reg = RREG32_SOC15( adev->doorbell_index.vcn.vcn_ring0_1;
 if ( dev-doorbell_indexvcn. =;
  return;

 return >doorbell_indexvpe_ring=AMDGPU_NAVI10_DOORBELL64_VPE;
}

static void soc21_init_doorbell_index(struct;
{
 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 adev-adev-.max_assignment  << 1
 adev->doorbell_index = 2;
 adev-
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 adev-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 adev-     bool)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
adev-.userqueue_end  ;
 adev-e
 adev-> amdgpu_gfx_rlc_exit_safe_mode(, 0);
 adev- ;
  AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
 adev->doorbell_index
 ;
 adev-  ,
a>.mes_ring1  AMDGPU_NAVI10_DOORBELL_MES_RING1
 adev- . = soc21_read_register
 adev->.sdma_engine]=AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1
.ih=AMDGPU_NAVI10_DOORBELL_IH
 adev-..vcn_ring0_1AMDGPU_NAVI10_DOORBELL64_VCN0_1
index.vcn_ring2_3 ;
  set_vce_clocks&,
  . =&,
 .nit_doorbell_index=&,
 adev-need_full_reset=&soc21_need_full_reset
adev-. = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;

 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT get_pcie_replay_count amdgpu_nbio_get_pcie_replay_count
 adev->doorbell_index =&,
}

static void soc21_pre_asic_init(struct amdgpu_device *adev)
{static  (struct *ip_block
}

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  b enter
{
  enter
  amdgpu_gfx_rlc_enter_safe_mode(adev-> = &;
 else
  amdgpu_gfx_rlc_exit_safe_mode, 0java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41

 if (adev->gfx.funcs->update_perfmon_mgcg)
  adev-java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55

 return;
}

static const struct amdgpu_asic_funcs soc21_asic_funcs = {
.read_disabled_bios  &,
 dev- = soc21_didt_wreg
 .
 .eset =&,
 .java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
 .get_xclk>external_rev_id=0;
 . ((adev, )){
 set_vce_clocks&soc21_set_vce_clocks,
 .get_config_memsize = &soc21_get_config_memsize,
 .init_doorbell_index = &soc21_init_doorbell_indexadev- = AMD_CG_SUPPORT_GFX_CGCG |
 .need_full_reset = &soc21_need_full_reset,
 .need_reset_on_init = &soc21_need_reset_on_init
 .et_pcie_replay_count &,
 .supports_baco = &amdgpu_dpm_is_baco_supportedjava.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 6
 .pre_asic_init = &soc21_pre_asic_init,
 .query_video_codecs = &soc21_query_video_codecs,
 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
};

static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *  AMD_CG_SUPPORT_GFX_PERF_CLK|

 adev->nbio.funcs->set_reg_remap(adev);
 adev->smc_rreg =  AMD_CG_SUPPORT_JPEG_MGCG|
 adev->smc_wreg = NULL;
 adev->pcie_rreg = & AMD_CG_SUPPORT_ATHUB_MGCG
adev-pcie_wreg=&amdgpu_device_indirect_wreg;
   AMD_CG_SUPPORT_MC_MGCG
  AMD_CG_SUPPORT_MC_LS
 dev- = amdgpu_device_pcie_port_rreg
adev->pciep_wreg=amdgpu_device_pcie_port_wreg

 /* TODO: will add them during VCN v2 implementation */
    |
    |

 >didt_rreg soc21_didt_rreg
 adev- = soc21_didt_wreg

 >asic_funcs=&soc21_asic_funcs

 adev- ase(1 0,2:
 adev->external_rev_id = 0xff;
 switch (amdgpu_ip_version adev->cg_flags =
 case(11 0 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  adev->cg_flags |
   |
#f 0
CGCG
  |
#endif
 AMD_CG_SUPPORT_GFX_MGCG
  |
     |
     |
      |
 AMD_PG_SUPPORT_MMHUB;
  AMD_CG_SUPPORT_ATHUB_MGCG
   AMD_CG_SUPPORT_ATHUB_LS |
  AMD_CG_SUPPORT_MC_MGCG
   AMD_CG_SUPPORT_MC_LS |
   AMD_CG_SUPPORT_IH_CG |
    AMD_CG_SUPPORT_GFX_CGCG
  AMD_CG_SUPPORT_GFX_CGLS
 AMD_CG_SUPPORT_GFX_MGCG |
    AMD_CG_SUPPORT_GFX_ |
   |
   AMD_PG_SUPPORT_MMHUBAMD_CG_SUPPORT_GFX_PERF_CLK
 >external_rev_id=adev-rev_idx1
  break;
 caseIP_VERSION1,0 )
  adev- AMD_CG_SUPPORT_HDP_MGCG
  AMD_CG_SUPPORT_GFX_CGCG
 AMD_CG_SUPPORT_GFX_CGLS
    |
    |
  |
  |
   AMD_CG_SUPPORT_VCN_MGCG|
     ;
    adev- =
    AMD_PG_SUPPORT_GFX_PG
 AMD_PG_SUPPORT_VCN
   |
   AMD_PG_SUPPORT_JPEG |
   AMD_PG_SUPPORT_ATHUB |
   AMD_PG_SUPPORT_MMHUB
  adev->external_rev_id =  IP_VERSION(1 ,3:
  break;
 case IP_VERSION(11, 0, 1):
 adev- =
     |
   AMD_CG_SUPPORT_GFX_CGLS  AMD_CG_SUPPORT_GFX_CGCG|
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_GFX_FGCG |
   AMD_CG_SUPPORT_REPEATER_FGCG|
    AMD_CG_SUPPORT_REPEATER_FGCG|
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS |
   AMD_CG_SUPPORT_HDP_MGCG |
  AMD_CG_SUPPORT_HDP_LS
  AMD_CG_SUPPORT_HDP_SD
 AMD_CG_SUPPORT_ATHUB_MGCG
 AMD_CG_SUPPORT_IH_CG
  AMD_CG_SUPPORT_BIF_MGCG java.lang.StringIndexOutOfBoundsException: Range [28, 29) out of bounds for length 28
   |
   AMD_CG_SUPPORT_VCN_MGCG |
   AMD_CG_SUPPORT_JPEG_MGCG;
  adev->pg_flags =
   AMD_PG_SUPPORT_GFX_PG |
   AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_VCN_DPG |
   AMD_PG_SUPPORT_JPEG;
  
  break; |
  (1,0 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  adev-  |
 ;
   AMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS |
   AMD_CG_SUPPORT_REPEATER_FGCG |
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_HDP_SD |
   AMD_CG_SUPPORT_ATHUB_MGCG |
   AMD_CG_SUPPORT_ATHUB_LS;
  adev->pg_flags = AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_VCN_DPG |
   AMD_PG_SUPPORT_JPEG;
  adev->external_rev_id = adev->rev_idev_id+ 0;
  break;
(11,0 4):
 adev-cg_flags =
    ;
   adev- = adev-rev_id +0;
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_GFX_FGCG|
   AMD_CG_SUPPORT_REPEATER_FGCG IP_VERSION1,5 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
   AMD_CG_SUPPORT_GFX_PERF_CLK |
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS |
   AMD_CG_SUPPORT_HDP_MGCG |
   AMD_CG_SUPPORT_HDP_LS |
   |
   AMD_CG_SUPPORT_ATHUB_LS |
 AMD_CG_SUPPORT_GFX_3D_CGCG
  AMD_CG_SUPPORT_BIF_MGCG |
   AMD_CG_SUPPORT_BIF_LS AMD_CG_SUPPORT_MC_MGCG
   |
    AMD_CG_SUPPORT_HDP_LS|
  adev->pg_flags = AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_VCN_DPG |
   AMD_PG_SUPPORT_GFX_PG |
   AMD_PG_SUPPORT_JPEG;
  adev->external_rev_id = adev->rev_id + 0x80;
  break;
  IP_VERSION11 5 0:
 adev-cg_flags = AMD_CG_SUPPORT_VCN_MGCG|
   AMD_CG_SUPPORT_JPEG_MGCG |
   AMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS |
   AMD_CG_SUPPORT_GFX_MGCG |
  AMD_CG_SUPPORT_GFX_FGCG|
    AMD_CG_SUPPORT_IH_CG
    AMD_CG_SUPPORT_BIF_MGCG
   AMD_CG_SUPPORT_BIF_LS
   AMD_CG_SUPPORT_GFX_3D_CGLS |
  AMD_CG_SUPPORT_MC_MGCG
    AMD_PG_SUPPORT_VCN
   AMD_CG_SUPPORT_HDP_LS |
   AMD_CG_SUPPORT_HDP_DS |
   AMD_CG_SUPPORT_HDP_SD |
  AMD_CG_SUPPORT_ATHUB_MGCG
   AMD_CG_SUPPORT_ATHUB_LS |
   AMD_CG_SUPPORT_IH_CG
   
     >external_rev_idadev- + 0;
  adev-b;
  AMD_PG_SUPPORT_JPEG_DPG|
   AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_JPEG |
   AMD_PG_SUPPORT_GFX_PG;
  if (adev-   |
  adev-> =0;
  else AMD_CG_SUPPORT_GFX_MGCG
  adev- = >rev_id + x10
  break AMD_CG_SUPPORT_REPEATER_FGCG
 case IP_VERSION(  AMD_CG_SUPPORT_GFX_3D_CGCG |
  adev->cg_flags =
   AMD_CG_SUPPORT_GFX_CGCG |
    AMD_CG_SUPPORT_HDP_LS
  AMD_CG_SUPPORT_GFX_MGCG
   AMD_CG_SUPPORT_GFX_FGCG |
   AMD_CG_SUPPORT_REPEATER_FGCGjava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
AMD_CG_SUPPORT_GFX_PERF_CLK
     java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 AMD_CG_SUPPORT_GFX_3D_CGLS
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS |
   AMD_CG_SUPPORT_HDP_LS |
   AMD_CG_SUPPORT_HDP_DS |
   AMD_CG_SUPPORT_HDP_SD |
   AMD_CG_SUPPORT_ATHUB_MGCG |
   AMD_CG_SUPPORT_ATHUB_LS |
   AMD_CG_SUPPORT_IH_CG |
   AMD_CG_SUPPORT_BIF_MGCG |
   AMD_CG_SUPPORT_BIF_LS adev-external_rev_id adev->rev_id0xc1;
   AMD_CG_SUPPORT_VCN_MGCG |
   AMD_CG_SUPPORT_JPEG_MGCG;
  adev->pg_flags adev-cg_flags  |
     AMD_CG_SUPPORT_JPEG_MGCG java.lang.StringIndexOutOfBoundsException: Range [29, 30) out of bounds for length 29
   AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_VCN_DPG |
   AMD_PG_SUPPORT_JPEG;
  adev->external_rev_id = adev->rev_id + 0xc1;
  break
   |
   AMD_CG_SUPPORT_GFX_MGCG
   AMD_CG_SUPPORT_JPEG_MGCG |
   AMD_CG_SUPPORT_GFX_CGCG |  |
   AMD_CG_SUPPORT_GFX_CGLSAMD_CG_SUPPORT_HDP_SD java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_GFX_FGCG |
ER_FGCG
  adev-pg_flagsA |
  |
  |
      |
  ;
   >external_rev_id >rev_idx40
   AMD_CG_SUPPORT_HDP_DS |
   |
   AMD_CG_SUPPORT_ATHUB_MGCG |
   |
   |
   AMD_CG_SUPPORT_BIF_MGCG |
   AMD_CG_SUPPORT_BIF_LS;
  adev->pg_flags adev->pg_flags  |
   |
     |
   AMD_PG_SUPPORT_JPEG |
   AMD_PG_SUPPORT_GFX_PG;
 adev-> = >rev_id x40
  break;
case IP_VERSION1,5 3:
  adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
   AMD_CG_SUPPORT_JPEG_MGCG |
   AMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS |
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_GFX_FGCG |
   |
   AMD_CG_SUPPORT_GFX_PERF_CLKAMD_CG_SUPPORT_HDP_DS |
AMD_CG_SUPPORT_HDP_SD
   AMD_CG_SUPPORT_ATHUB_MGCG |
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS |
 AMD_CG_SUPPORT_HDP_LS
 AMD_CG_SUPPORT_IH_CG |
    AMD_CG_SUPPORT_BIF_MGCG |
     AMD_CG_SUPPORT_BIF_LS
  AMD_CG_SUPPORT_ATHUB_LS
   AMD_CG_SUPPORT_IH_CG |
   AMD_CG_SUPPORT_BIF_MGCG |
   AMD_CG_SUPPORT_BIF_LS;
  adev-pg_flags = |
   AMD_PG_SUPPORT_VCNadev- = >rev_id00
   AMD_PG_SUPPORT_JPEG_DPG |
   AMD_PG_SUPPORT_JPEG |
   AMD_PG_SUPPORT_GFX_PG;
  adev- = adev->rev_id 0x50;
  break;
 return EINVAL
  /* FIXME: not supported yet */
  return -EINVAL;
 }

}
  amdgpu_virt_init_setting(adev) eturn
  xgpu_nv_mailbox_set_irq_funcs(
 }

 return amdgpu_deviceadev ip_block-a;
}

static int (adev;
{
 struct amdgpu_device *adevamdgpu_sriov_is_av1_support)){

 if (amdgpu_sriov_vf(adev)) {
  xgpu_nv_mailbox_get_irqadev
  if ((         ,
  !      ARRAY_SIZE(sriov_vcn_4_0_0_
   (adev
     ARRAY_SIZE));
            ARRAY_SIZE(java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 10
            sriov_vcn_4_0_0_video_codecs_decode_array_vcn1      (sriov_vcn_4_0_0_video_codecs_encode_array_vcn0
            ARRAY_SIZE(         ARRAY_SIZE));
  }}else
   amdgpu_virt_update_sriov_video_codec (adev-.ras&
            sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
            ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0 /* don't need to fail gpu late init
     sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
     ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
}
} else {
if (adev->nbio.ras &&
    adev->nbio.ras_err_event_athub_irq.funcs)
/* don't need to fail gpu late init
 * if enabling athub_err_event interrupt failed
 * nbio v4_3 only support fatal error hanlding
 * just enable the interrupt directly */
 amdgpu_irq_get(dev,&>nbio., 0;
 }

 /* Enable selfring doorbell aperture late because doorbell BAR
 * aperture will change if resize BAR successfully in gmc sw_init.
 */
 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, 

 return 0;
}();

  soc21_common_sw_init amdgpu_ip_block *ip_block
{
 structstaticintsoc21_common_hw_initstructamdgpu_ip_block*ip_block

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  xgpu_nv_mailbox_add_irq_id(adev);

 return 0;
}

static int   * to process space
{
 struct amdgpu_device *adev = ip_block->adev;

 /* enable aspm */
soc21_program_aspm();
 /* setup nbio registers */
 adev->nbio.funcs->init_registers(adev>nbio>enable_doorbell_aperture, true)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
/
  * for the purpose of expose those{
  * to process space
  */
 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev /* Disable the doorbell aperture and selfring doorbell aperture
adev->nbio.funcs->remap_hdp_registers(adev);
/* enable the doorbell aperture */
 adev->nbio.funcs->java.lang.StringIndexOutOfBoundsException: Range [0, 43) out of bounds for length 22

 return 0;
}

static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block)
{
 struct if (mdgpu_sriov_vf()) {

 /* Disable the doorbell aperture and selfring doorbell aperture
 * separately in hw_fini because soc21_enable_doorbell_aperture
 * has been removed and there is no need to delay disabling
 * selfring doorbell.
 */
 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
adev-.>enable_doorbell_selfring_aperture, false)

 ifjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 } else {
  if (adev- (ip_block
      adev->nbio
 (adev&>nbioras_err_event_athub_irq, )
 }

  ;
}

static int soc21_common_suspend(struct 
{
 return soc21_common_hw_fini  * 1) Only reset dGPU side  * 2) S3 suspend got aborted and   *    As for dGPU suspend abort cases the SOL value
}

 boolsoc21_need_reset_on_resume(struct amdgpu_device*dev)
{
u32, ;

 /* Will reset for the following suspend abort cases.
 * 1) Only reset dGPU side.
 * 2) S3 suspend got aborted and TOS is active.
 *    As for dGPU suspend abort cases the SOL value
 *    will be kept as zero at this resume point.
 */
 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) {
  sol_reg1
 (10;
  sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

  ( !=sol_reg2;
 }

 return false;
}

static soc21_common_resumestruct *ip_block
{
 struct amdgpu_deviceadev =ip_block-adev;

 if (soc21_need_reset_on_resume(adev)) {
  dev_info(adev->dev, "S3 suspend aborted soc21_asic_reset(adev)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
 
}

r ()java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
}

static (struct *)
{
r true
}

static   (, 3,0:
        enum amd_clockgating_state state)
{
 struct amdgpu_devicecaseIP_VERSION(,3 )java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26

 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
 case(4,3 0:
 case IP_VERSION(4, 3, 1):
case(7 ,0:
 case IP_VERSION(7, 7, 1):
 case IP_VERSION(7, 11, 0):
caseIP_VERSION7 1,1:
 case IP_VERSION(7, 11, 2):
caseIP_VERSION7 1 )
>nbio>update_medium_grain_clock_gating,
   == );
adev-.funcs-(adev
    >hdp>update_clock_gating,
 adev->.funcs-(adev
    state == AMD_CG_STATE_GATE);
  break ;
default
 breakjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
 java.lang.StringIndexOutOfBoundsException: Range [2, 3) out of bounds for length 2
 return 0;
}

 intsoc21_common_set_powergating_statestruct *ip_block
        enum java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0
{
 struct * = ip_block-;

 switch (amdgpu_ip_version(adev,  >lsdma>update_memory_power_gating,
 case (6 ,0
 case IP_VERSION(6, 0, 2):
  adev->lsdma:
    state   reak
  breakjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 default:
  break;
 }

 return 0;
}

static void java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 0
{
 struct namesoc21_common

 adev->nbio.funcs->get_clockgating_state(adev, flags);

 adev-sw_init  ,
}

static  amd_ip_funcs = {
 .name = "soc21_common",
 .early_init = soc21_common_early_init,. = ,
 .late_init = soc21_common_late_init,
 .sw_init = soc21_common_sw_init,
 .hw_init ,
 .hw_fini = soc21_common_hw_fini,
 .suspend = soc21_common_suspend;
 .resume = soc21_common_resume,
 .is_idle = soc21_common_is_idle,
 .set_clockgating_state = soc21_common_set_clockgating_state,
 .set_powergating_state = soc21_common_set_powergating_state,
 .get_clockgating_state = soc21_common_get_clockgating_state,
};