/* Throw the die ID into the entropy pool at boot */
omap_get_die_id(&odi);
add_device_randomness(&odi, sizeof(odi)); return 0;
}
omap_device_initcall(omap_feed_randpool);
void __init omap2xxx_check_revision(void)
{ int i, j;
u32 idcode, prod_id;
u16 hawkeye;
u8 dev_type, rev; struct omap_die_id odi;
/* * am35x fixups: * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as * reserved and therefore return 0 when read. Unfortunately, * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to * mean that a feature is present even though it isn't so clear * the incorrectly set feature bits.
*/ if (soc_is_am35xx())
omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
/* * TODO: Get additional info (where applicable) * e.g. Size of L2 cache.
*/
/* * We cannot access revision registers on ES1.0. * If the processor type is Cortex-A8 and the revision is 0x0 * it means its Cortex r0p0 which is 3430 ES1.0.
*/
cpuid = read_cpuid_id(); if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
cpu_rev = "1.0"; return;
}
/* * Detection for 34xx ES2.0 and above can be done with just * hawkeye and rev. See TRM 1.5.2 Device Identification. * Note that rev does not map directly to our defined processor * revision numbers as ES1.0 uses value 0.
*/
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
switch (hawkeye) { case 0xb7ae: /* Handle 34xx/35xx devices */ switch (rev) { case 0: /* Take care of early samples */ case 1:
omap_revision = OMAP3430_REV_ES2_0;
cpu_rev = "2.0"; break; case 2:
omap_revision = OMAP3430_REV_ES2_1;
cpu_rev = "2.1"; break; case 3:
omap_revision = OMAP3430_REV_ES3_0;
cpu_rev = "3.0"; break; case 4:
omap_revision = OMAP3430_REV_ES3_1;
cpu_rev = "3.1"; break; case 7: default: /* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1_2;
cpu_rev = "3.1.2";
} break; case 0xb868: /* * Handle OMAP/AM 3505/3517 devices * * Set the device to be OMAP3517 here. Actual device * is identified later based on the features.
*/ switch (rev) { case 0:
omap_revision = AM35XX_REV_ES1_0;
cpu_rev = "1.0"; break; case 1: default:
omap_revision = AM35XX_REV_ES1_1;
cpu_rev = "1.1";
} break; case 0xb891: /* Handle 36xx devices */
switch(rev) { case 0: /* Take care of early samples */
omap_revision = OMAP3630_REV_ES1_0;
cpu_rev = "1.0"; break; case 1:
omap_revision = OMAP3630_REV_ES1_1;
cpu_rev = "1.1"; break; case 2: default:
omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2";
} break; case 0xb81e: switch (rev) { case 0:
omap_revision = TI8168_REV_ES1_0;
cpu_rev = "1.0"; break; case 1:
omap_revision = TI8168_REV_ES1_1;
cpu_rev = "1.1"; break; case 2:
omap_revision = TI8168_REV_ES2_0;
cpu_rev = "2.0"; break; case 3: default:
omap_revision = TI8168_REV_ES2_1;
cpu_rev = "2.1";
} break; case 0xb944: switch (rev) { case 0:
omap_revision = AM335X_REV_ES1_0;
cpu_rev = "1.0"; break; case 1:
omap_revision = AM335X_REV_ES2_0;
cpu_rev = "2.0"; break; case 2: default:
omap_revision = AM335X_REV_ES2_1;
cpu_rev = "2.1"; break;
} break; case 0xb98c: switch (rev) { case 0:
omap_revision = AM437X_REV_ES1_0;
cpu_rev = "1.0"; break; case 1:
omap_revision = AM437X_REV_ES1_1;
cpu_rev = "1.1"; break; case 2: default:
omap_revision = AM437X_REV_ES1_2;
cpu_rev = "1.2"; break;
} break; case 0xb8f2: case 0xb968: switch (rev) { case 0: case 1:
omap_revision = TI8148_REV_ES1_0;
cpu_rev = "1.0"; break; case 2:
omap_revision = TI8148_REV_ES2_0;
cpu_rev = "2.0"; break; case 3: default:
omap_revision = TI8148_REV_ES2_1;
cpu_rev = "2.1"; break;
} break; default: /* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2";
pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
hawkeye);
}
sprintf(soc_rev, "ES%s", cpu_rev);
}
/* * The IC rev detection is done with hawkeye and rev. * Note that rev does not map directly to defined processor * revision numbers as ES1.0 uses value 0.
*/
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xf;
/* * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 * Use ARM register to detect the correct ES version
*/ if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
idcode = read_cpuid_id();
rev = (idcode & 0xf) - 1;
}
switch (hawkeye) { case 0xb852: switch (rev) { case 0:
omap_revision = OMAP4430_REV_ES1_0; break; case 1: default:
omap_revision = OMAP4430_REV_ES2_0;
} break; case 0xb95c: switch (rev) { case 3:
omap_revision = OMAP4430_REV_ES2_1; break; case 4:
omap_revision = OMAP4430_REV_ES2_2; break; case 6: default:
omap_revision = OMAP4430_REV_ES2_3;
} break; case 0xb94e: switch (rev) { case 0:
omap_revision = OMAP4460_REV_ES1_0; break; case 2: default:
omap_revision = OMAP4460_REV_ES1_1; break;
} break; case 0xb975: switch (rev) { case 0: default:
omap_revision = OMAP4470_REV_ES1_0; break;
} break; default: /* Unknown default to latest silicon rev as default */
omap_revision = OMAP4430_REV_ES2_3;
}
/* * Set up things for map_io and processor detection later on. Gets called * pretty much first thing from board init. For multi-omap, this gets * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to * detect the exact revision later on in omap2_detect_revision() once map_io * is done.
*/ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
{
omap_revision = class;
tap_base = tap;
/* XXX What is this intended to do? */ if (soc_is_omap34xx())
tap_prod_id = 0x0210; else
tap_prod_id = 0x0208;
}
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