Quelle  sdm660.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2018, Craig Tatlor.
 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
 * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
 */

#include "sdm630.dtsi"

&adreno_gpu {
 compatible = "qcom,adreno-512.0", "qcom,adreno";
 operating-points-v2 = <&gpu_sdm660_opp_table>;

 gpu_sdm660_opp_table: opp-table {
  compatible = "operating-points-v2";

  /*
   * 775MHz is only available on the highest speed bin
   * Though it cannot be used for now due to interconnect
   * framework not supporting multiple frequencies
   * at the same opp-level

  opp-750000000 {
   opp-hz = /bits/ 64 <750000000>;
   opp-level = <RPM_SMD_LEVEL_TURBO>;
   opp-peak-kBps = <5412000>;
   opp-supported-hw = <0xCHECKME>;
  };

  * These OPPs are correct, but we are lacking support for the
  * GPU regulator. Hence, disable them for now to prevent the
  * platform from hanging on high graphics loads.

  opp-700000000 {
   opp-hz = /bits/ 64 <700000000>;
   opp-level = <RPM_SMD_LEVEL_TURBO>;
   opp-peak-kBps = <5184000>;
   opp-supported-hw = <0xff>;
  };

  opp-647000000 {
   opp-hz = /bits/ 64 <647000000>;
   opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
   opp-peak-kBps = <4068000>;
   opp-supported-hw = <0xff>;
  };

  opp-588000000 {
   opp-hz = /bits/ 64 <588000000>;
   opp-level = <RPM_SMD_LEVEL_NOM>;
   opp-peak-kBps = <3072000>;
   opp-supported-hw = <0xff>;
  };

  opp-465000000 {
   opp-hz = /bits/ 64 <465000000>;
   opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
   opp-peak-kBps = <2724000>;
   opp-supported-hw = <0xff>;
  };

  opp-370000000 {
   opp-hz = /bits/ 64 <370000000>;
   opp-level = <RPM_SMD_LEVEL_SVS>;
   opp-peak-kBps = <2188000>;
   opp-supported-hw = <0xff>;
  };
  */

  opp-266000000 {
   opp-hz = /bits/ 64 <266000000>;
   opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
   opp-peak-kBps = <1648000>;
   opp-supported-hw = <0xff>;
  };

  opp-160000000 {
   opp-hz = /bits/ 64 <160000000>;
   opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
   opp-peak-kBps = <1200000>;
   opp-supported-hw = <0xff>;
  };
 };
};

&cpu0 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <1024>;
 /delete-property/ operating-points-v2;
};

&cpu1 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <1024>;
 /delete-property/ operating-points-v2;
};

&cpu2 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <1024>;
 /delete-property/ operating-points-v2;
};

&cpu3 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <1024>;
 /delete-property/ operating-points-v2;
};

&cpu4 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <640>;
 /delete-property/ operating-points-v2;
};

&cpu5 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <640>;
 /delete-property/ operating-points-v2;
};

&cpu6 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <640>;
 /delete-property/ operating-points-v2;
};

&cpu7 {
 compatible = "qcom,kryo260";
 capacity-dmips-mhz = <640>;
 /delete-property/ operating-points-v2;
};

&gcc {
 compatible = "qcom,gcc-sdm660";
};

&gpucc {
 compatible = "qcom,gpucc-sdm660";
};

&mdp {
 compatible = "qcom,sdm660-mdp5", "qcom,mdp5";

 ports {
  port@1 {
   reg = <1>;
   mdp5_intf2_out: endpoint {
    remote-endpoint = <&mdss_dsi1_in>;
   };
  };
 };
};

&mdss {
 mdss_dsi1: dsi@c996000 {
  compatible = "qcom,sdm660-dsi-ctrl",
        "qcom,mdss-dsi-ctrl";
  reg = <0x0c996000 0x400>;
  reg-names = "dsi_ctrl";

  /* DSI1 shares the OPP table with DSI0 */
  operating-points-v2 = <&dsi_opp_table>;
  power-domains = <&rpmpd SDM660_VDDCX>;

  interrupt-parent = <&mdss>;
  interrupts = <5>;

  assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
     <&mmcc PCLK1_CLK_SRC>;
  assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
      <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;

  clocks = <&mmcc MDSS_MDP_CLK>,
    <&mmcc MDSS_BYTE1_CLK>,
    <&mmcc MDSS_BYTE1_INTF_CLK>,
    <&mmcc MNOC_AHB_CLK>,
    <&mmcc MDSS_AHB_CLK>,
    <&mmcc MDSS_AXI_CLK>,
    <&mmcc MISC_AHB_CLK>,
    <&mmcc MDSS_PCLK1_CLK>,
    <&mmcc MDSS_ESC1_CLK>;
  clock-names = "mdp_core",
     "byte",
     "byte_intf",
     "mnoc",
     "iface",
     "bus",
     "core_mmss",
     "pixel",
     "core";

  phys = <&mdss_dsi1_phy>;

  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    mdss_dsi1_in: endpoint {
     remote-endpoint = <&mdp5_intf2_out>;
    };
   };

   port@1 {
    reg = <1>;
    mdss_dsi1_out: endpoint {
    };
   };
  };
 };

 mdss_dsi1_phy: phy@c996400 {
  compatible = "qcom,dsi-phy-14nm-660";
  reg = <0x0c996400 0x100>,
    <0x0c996500 0x300>,
    <0x0c996800 0x188>;
  reg-names = "dsi_phy",
    "dsi_phy_lane",
    "dsi_pll";

  #clock-cells = <1>;
  #phy-cells = <0>;

  clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
  clock-names = "iface", "ref";
  status = "disabled";
 };
};

&mmcc {
 compatible = "qcom,mmcc-sdm660";
 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
   <&sleep_clk>,
   <&gcc GCC_MMSS_GPLL0_CLK>,
   <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
   <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
   <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
   <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
   <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
   <0>,
   <0>;
};

&tlmm {
 compatible = "qcom,sdm660-pinctrl";
};

&tsens {
 #qcom,sensors = <14>;
};