Quelle  sm8550.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2022, Linaro Limited
 */

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,sm8550-camcc.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 chosen { };

 clocks {
  xo_board: xo-board {
   compatible = "fixed-clock";
   #clock-cells = <0>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
  };

  bi_tcxo_div2: bi-tcxo-div2-clk {
   #clock-cells = <0>;
   compatible = "fixed-factor-clock";
   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-mult = <1>;
   clock-div = <2>;
  };

  bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
   #clock-cells = <0>;
   compatible = "fixed-factor-clock";
   clocks = <&rpmhcc RPMH_CXO_CLK_A>;
   clock-mult = <1>;
   clock-div = <2>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a510";
   reg = <0 0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_0>;
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   #cooling-cells = <2>;
   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a510";
   reg = <0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_100>;
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   #cooling-cells = <2>;
   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a510";
   reg = <0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_200>;
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   #cooling-cells = <2>;
   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a715";
   reg = <0 0x300>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   next-level-cache = <&l2_300>;
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1792>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@400 {
   device_type = "cpu";
   compatible = "arm,cortex-a715";
   reg = <0 0x400>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   next-level-cache = <&l2_400>;
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1792>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   l2_400: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu5: cpu@500 {
   device_type = "cpu";
   compatible = "arm,cortex-a710";
   reg = <0 0x500>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   next-level-cache = <&l2_500>;
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1792>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   l2_500: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu6: cpu@600 {
   device_type = "cpu";
   compatible = "arm,cortex-a710";
   reg = <0 0x600>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   next-level-cache = <&l2_600>;
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1792>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   l2_600: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu7: cpu@700 {
   device_type = "cpu";
   compatible = "arm,cortex-x3";
   reg = <0 0x700>;
   clocks = <&cpufreq_hw 2>;
   enable-method = "psci";
   next-level-cache = <&l2_700>;
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 2>;
   capacity-dmips-mhz = <1894>;
   dynamic-power-coefficient = <588>;
   #cooling-cells = <2>;
   l2_700: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };

    core4 {
     cpu = <&cpu4>;
    };

    core5 {
     cpu = <&cpu5>;
    };

    core6 {
     cpu = <&cpu6>;
    };

    core7 {
     cpu = <&cpu7>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   little_cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    idle-state-name = "silver-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <550>;
    exit-latency-us = <750>;
    min-residency-us = <6700>;
    local-timer-stop;
   };

   big_cpu_sleep_0: cpu-sleep-1-0 {
    compatible = "arm,idle-state";
    idle-state-name = "gold-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <600>;
    exit-latency-us = <1300>;
    min-residency-us = <8136>;
    local-timer-stop;
   };

   prime_cpu_sleep_0: cpu-sleep-2-0 {
    compatible = "arm,idle-state";
    idle-state-name = "goldplus-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <500>;
    exit-latency-us = <1350>;
    min-residency-us = <7480>;
    local-timer-stop;
   };
  };

  domain-idle-states {
   cluster_sleep_0: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <750>;
    exit-latency-us = <2350>;
    min-residency-us = <9144>;
   };

   cluster_sleep_1: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100c344>;
    entry-latency-us = <2800>;
    exit-latency-us = <4400>;
    min-residency-us = <10150>;
   };
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sm8550", "qcom,scm";
   qcom,dload-mode = <&tcsr 0x19000>;
   interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
  };
 };

 clk_virt: interconnect-0 {
  compatible = "qcom,sm8550-clk-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mc_virt: interconnect-1 {
  compatible = "qcom,sm8550-mc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 qup_opp_table_100mhz: opp-table-qup100mhz {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };
 };

 qup_opp_table_120mhz: opp-table-qup120mhz {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-120000000 {
   opp-hz = /bits/ 64 <120000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };
 };

 qup_opp_table_125mhz: opp-table-qup125mhz {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-125000000 {
   opp-hz = /bits/ 64 <125000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };
 };

 memory@a0000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0 0xa0000000 0 0>;
 };

 pmu-a510 {
  compatible = "arm,cortex-a510-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 };

 pmu-a710 {
  compatible = "arm,cortex-a710-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 };

 pmu-a715 {
  compatible = "arm,cortex-a715-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 };

 pmu-x3 {
  compatible = "arm,cortex-x3-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&prime_cpu_sleep_0>;
  };

  cluster_pd: power-domain-cluster {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
  };
 };

 reserved_memory: reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  hyp_mem: hyp-region@80000000 {
   reg = <0 0x80000000 0 0xa00000>;
   no-map;
  };

  cpusys_vm_mem: cpusys-vm-region@80a00000 {
   reg = <0 0x80a00000 0 0x400000>;
   no-map;
  };

  hyp_tags_mem: hyp-tags-region@80e00000 {
   reg = <0 0x80e00000 0 0x3d0000>;
   no-map;
  };

  xbl_sc_mem: xbl-sc-region@d8100000 {
   reg = <0 0xd8100000 0 0x40000>;
   no-map;
  };

  hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
   reg = <0 0x811d0000 0 0x30000>;
   no-map;
  };

  /* merged xbl_dt_log, xbl_ramdump, aop_image */
  xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
   reg = <0 0x81a00000 0 0x260000>;
   no-map;
  };

  aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
   compatible = "qcom,cmd-db";
   reg = <0 0x81c60000 0 0x20000>;
   no-map;
  };

  /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
  aop_config_merged_mem: aop-config-merged-region@81c80000 {
   reg = <0 0x81c80000 0 0x74000>;
   no-map;
  };

  /* secdata region can be reused by apps */
  smem: smem@81d00000 {
   compatible = "qcom,smem";
   reg = <0 0x81d00000 0 0x200000>;
   hwlocks = <&tcsr_mutex 3>;
   no-map;
  };

  adsp_mhi_mem: adsp-mhi-region@81f00000 {
   reg = <0 0x81f00000 0 0x20000>;
   no-map;
  };

  global_sync_mem: global-sync-region@82600000 {
   reg = <0 0x82600000 0 0x100000>;
   no-map;
  };

  tz_stat_mem: tz-stat-region@82700000 {
   reg = <0 0x82700000 0 0x100000>;
   no-map;
  };

  cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
   reg = <0 0x82800000 0 0x4600000>;
   no-map;
  };

  mpss_mem: mpss-region@8a800000 {
   reg = <0 0x8a800000 0 0x10800000>;
   no-map;
  };

  q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
   reg = <0 0x9b000000 0 0x80000>;
   no-map;
  };

  ipa_fw_mem: ipa-fw-region@9b080000 {
   reg = <0 0x9b080000 0 0x10000>;
   no-map;
  };

  ipa_gsi_mem: ipa-gsi-region@9b090000 {
   reg = <0 0x9b090000 0 0xa000>;
   no-map;
  };

  gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
   reg = <0 0x9b09a000 0 0x2000>;
   no-map;
  };

  spss_region_mem: spss-region@9b100000 {
   reg = <0 0x9b100000 0 0x180000>;
   no-map;
  };

  /* First part of the "SPU secure shared memory" region */
  spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
   reg = <0 0x9b280000 0 0x60000>;
   no-map;
  };

  /* Second part of the "SPU secure shared memory" region */
  spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
   reg = <0 0x9b2e0000 0 0x20000>;
   no-map;
  };

  camera_mem: camera-region@9b300000 {
   reg = <0 0x9b300000 0 0x800000>;
   no-map;
  };

  video_mem: video-region@9bb00000 {
   reg = <0 0x9bb00000 0 0x700000>;
   no-map;
  };

  cvp_mem: cvp-region@9c200000 {
   reg = <0 0x9c200000 0 0x700000>;
   no-map;
  };

  cdsp_mem: cdsp-region@9c900000 {
   reg = <0 0x9c900000 0 0x2000000>;
   no-map;
  };

  q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
   reg = <0 0x9e900000 0 0x80000>;
   no-map;
  };

  q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
   reg = <0 0x9e980000 0 0x80000>;
   no-map;
  };

  adspslpi_mem: adspslpi-region@9ea00000 {
   reg = <0 0x9ea00000 0 0x4080000>;
   no-map;
  };

  /* uefi region can be reused by apps */

  /* Linux kernel image is loaded at 0xa8000000 */

  rmtfs_mem: rmtfs-region@d4a80000 {
   compatible = "qcom,rmtfs-mem";
   reg = <0x0 0xd4a80000 0x0 0x280000>;
   no-map;

   qcom,client-id = <1>;
   qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
  };

  mpss_dsm_mem: mpss-dsm-region@d4d00000 {
   reg = <0 0xd4d00000 0 0x3300000>;
   no-map;
  };

  tz_reserved_mem: tz-reserved-region@d8000000 {
   reg = <0 0xd8000000 0 0x100000>;
   no-map;
  };

  cpucp_fw_mem: cpucp-fw-region@d8140000 {
   reg = <0 0xd8140000 0 0x1c0000>;
   no-map;
  };

  qtee_mem: qtee-region@d8300000 {
   reg = <0 0xd8300000 0 0x500000>;
   no-map;
  };

  ta_mem: ta-region@d8800000 {
   reg = <0 0xd8800000 0 0x8a00000>;
   no-map;
  };

  tz_tags_mem: tz-tags-region@e1200000 {
   reg = <0 0xe1200000 0 0x2740000>;
   no-map;
  };

  hwfence_shbuf: hwfence-shbuf-region@e6440000 {
   reg = <0 0xe6440000 0 0x279000>;
   no-map;
  };

  trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
   reg = <0 0xf3600000 0 0x4aee000>;
   no-map;
  };

  trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
   reg = <0 0xf80ee000 0 0x1000>;
   no-map;
  };

  trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
   reg = <0 0xf80ef000 0 0x9000>;
   no-map;
  };

  trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
   reg = <0 0xf80f8000 0 0x4000>;
   no-map;
  };

  trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
   reg = <0 0xf80fc000 0 0x4000>;
   no-map;
  };

  trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
   reg = <0 0xf8100000 0 0x100000>;
   no-map;
  };

  oem_vm_mem: oem-vm-region@f8400000 {
   reg = <0 0xf8400000 0 0x4800000>;
   no-map;
  };

  oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
   reg = <0 0xfcc00000 0 0x4000>;
   no-map;
  };

  oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
   reg = <0 0xfcc04000 0 0x100000>;
   no-map;
  };

  hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
   reg = <0 0xfce00000 0 0x2900000>;
   no-map;
  };

  hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
   reg = <0 0xff700000 0 0x100000>;
   no-map;
  };
 };

 smp2p-adsp {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;
  interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_LPASS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  smp2p_adsp_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_adsp_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;
  interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_CDSP
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  smp2p_cdsp_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_cdsp_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-modem {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;
  interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_MPSS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  smp2p_modem_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_modem_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  ipa_smp2p_out: ipa-ap-to-modem {
   qcom,entry-name = "ipa";
   #qcom,smem-state-cells = <1>;
  };

  ipa_smp2p_in: ipa-modem-to-ap {
   qcom,entry-name = "ipa";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  compatible = "simple-bus";
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;

  #address-cells = <2>;
  #size-cells = <2>;

  gcc: clock-controller@100000 {
   compatible = "qcom,sm8550-gcc";
   reg = <0 0x00100000 0 0x1f4200>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   clocks = <&bi_tcxo_div2>, <&sleep_clk>,
     <&pcie0_phy>,
     <&pcie1_phy QMP_PCIE_PIPE_CLK>,
     <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
     <&ufs_mem_phy 0>,
     <&ufs_mem_phy 1>,
     <&ufs_mem_phy 2>,
     <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
  };

  ipcc: mailbox@408000 {
   compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
   reg = <0 0x00408000 0 0x1000>;
   interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <3>;
   #mbox-cells = <2>;
  };

  gpi_dma2: dma-controller@800000 {
   compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
   #dma-cells = <3>;
   reg = <0 0x00800000 0 0x60000>;
   interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0x3e>;
   iommus = <&apps_smmu 0x436 0>;
   dma-coherent;
   status = "disabled";
  };

  qupv3_id_1: geniqup@8c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x008c0000 0 0x2000>;
   ranges;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
   iommus = <&apps_smmu 0x423 0>;
   dma-coherent;
   #address-cells = <2>;
   #size-cells = <2>;
   status = "disabled";

   i2c8: i2c@880000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00880000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c8_data_clk>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
           <&gpi_dma2 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi8: spi@880000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00880000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
           <&gpi_dma2 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c9: i2c@884000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00884000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c9_data_clk>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
           <&gpi_dma2 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi9: spi@884000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00884000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
           <&gpi_dma2 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c10: i2c@888000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00888000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c10_data_clk>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
           <&gpi_dma2 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi10: spi@888000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00888000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
           <&gpi_dma2 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c11: i2c@88c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0088c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c11_data_clk>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
           <&gpi_dma2 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi11: spi@88c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0088c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
           <&gpi_dma2 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c12: i2c@890000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00890000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c12_data_clk>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
           <&gpi_dma2 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi12: spi@890000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00890000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
           <&gpi_dma2 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c13: i2c@894000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c13_data_clk>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
           <&gpi_dma2 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi13: spi@894000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
           <&gpi_dma2 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart14: serial@898000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x898000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
    interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_125mhz>;
    status = "disabled";
   };

   i2c15: i2c@89c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0089c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c15_data_clk>;
    interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
           <&gpi_dma2 1 7 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    status = "disabled";
   };

   spi15: spi@89c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0089c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
    interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
           <&gpi_dma2 1 7 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };
  };

  i2c_master_hub_0: geniqup@9c0000 {
   compatible = "qcom,geni-se-i2c-master-hub";
   reg = <0x0 0x009c0000 0x0 0x2000>;
   clock-names = "s-ahb";
   clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   status = "disabled";

   i2c_hub_0: i2c@980000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0x0 0x00980000 0x0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c0_data_clk>;
    interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_1: i2c@984000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0x0 0x00984000 0x0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c1_data_clk>;
    interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_2: i2c@988000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0x0 0x00988000 0x0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c2_data_clk>;
    interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_3: i2c@98c000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0x0 0x0098c000 0x0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c3_data_clk>;
    interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_4: i2c@990000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0x0 0x00990000 0x0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c4_data_clk>;
    interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_5: i2c@994000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0 0x00994000 0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c5_data_clk>;
    interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_6: i2c@998000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0 0x00998000 0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c6_data_clk>;
    interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_7: i2c@99c000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0 0x0099c000 0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c7_data_clk>;
    interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_8: i2c@9a0000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0 0x009a0000 0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c8_data_clk>;
    interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   i2c_hub_9: i2c@9a4000 {
    compatible = "qcom,geni-i2c-master-hub";
    reg = <0 0x009a4000 0 0x4000>;
    clock-names = "se", "core";
    clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
      <&gcc GCC_QUPV3_I2C_CORE_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&hub_i2c9_data_clk>;
    interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd RPMHPD_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };
  };

  gpi_dma1: dma-controller@a00000 {
   compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
   #dma-cells = <3>;
   reg = <0 0x00a00000 0 0x60000>;
   interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0x1e>;
   iommus = <&apps_smmu 0xb6 0>;
   dma-coherent;
   status = "disabled";
  };

  qupv3_id_0: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x00ac0000 0 0x2000>;
   ranges;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   iommus = <&apps_smmu 0xa3 0>;
   interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
      &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "qup-core";
   dma-coherent;
   #address-cells = <2>;
   #size-cells = <2>;
   status = "disabled";

   i2c0: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c0_data_clk>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
           <&gpi_dma1 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi0: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
           <&gpi_dma1 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c1: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a84000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c1_data_clk>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
           <&gpi_dma1 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    status = "disabled";
   };

   spi1: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a84000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
           <&gpi_dma1 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_120mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c2: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c2_data_clk>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
           <&gpi_dma1 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    status = "disabled";
   };

   spi2: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
           <&gpi_dma1 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c3: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a8c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c3_data_clk>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
           <&gpi_dma1 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    status = "disabled";
   };

   spi3: spi@a8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a8c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
           <&gpi_dma1 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c4: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c4_data_clk>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
           <&gpi_dma1 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    status = "disabled";
   };

   spi4: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
           <&gpi_dma1 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c5: i2c@a94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a94000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c5_data_clk>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
           <&gpi_dma1 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi5: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a94000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
           <&gpi_dma1 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c6: i2c@a98000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a98000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c6_data_clk>;
    interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
           <&gpi_dma1 1 6 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi6: spi@a98000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a98000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
      <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
           <&gpi_dma1 1 6 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart7: serial@a9c000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0 0x00a9c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart7_default>;
    interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
    interconnect-names = "qup-core", "qup-config";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
    power-domains = <&rpmhpd RPMHPD_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    status = "disabled";
   };
  };

  cnoc_main: interconnect@1500000 {
   compatible = "qcom,sm8550-cnoc-main";
   reg = <0 0x01500000 0 0x13080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  config_noc: interconnect@1600000 {
   compatible = "qcom,sm8550-config-noc";
   reg = <0 0x01600000 0 0x6200>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system_noc: interconnect@1680000 {
   compatible = "qcom,sm8550-system-noc";
   reg = <0 0x01680000 0 0x1d080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  pcie_noc: interconnect@16c0000 {
   compatible = "qcom,sm8550-pcie-anoc";
   reg = <0 0x016c0000 0 0x12200>;
   #interconnect-cells = <2>;
   clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
     <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre1_noc: interconnect@16e0000 {
   compatible = "qcom,sm8550-aggre1-noc";
   reg = <0 0x016e0000 0 0x14400>;
   #interconnect-cells = <2>;
   clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre2_noc: interconnect@1700000 {
   compatible = "qcom,sm8550-aggre2-noc";
   reg = <0 0x01700000 0 0x1e400>;
   #interconnect-cells = <2>;
   clocks = <&rpmhcc RPMH_IPA_CLK>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mmss_noc: interconnect@1780000 {
   compatible = "qcom,sm8550-mmss-noc";
   reg = <0 0x01780000 0 0x5b800>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  rng: rng@10c3000 {
   compatible = "qcom,sm8550-trng", "qcom,trng";
   reg = <0 0x010c3000 0 0x1000>;
  };

  pcie0: pcie@1c00000 {
   device_type = "pci";
   compatible = "qcom,pcie-sm8550";
   reg = <0 0x01c00000 0 0x3000>,
         <0 0x60000000 0 0xf1d>,
         <0 0x60000f20 0 0xa8>,
         <0 0x60001000 0 0x1000>,
         <0 0x60100000 0 0x100000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <0>;
   num-lanes = <2>;

   interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr";

   interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   msi-map = <0x0 &gic_its 0x1400 0x1>,
      <0x100 &gic_its 0x1401 0x1>;
   iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
        <0x100 &apps_smmu 0x1401 0x1>;

   resets = <&gcc GCC_PCIE_0_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_0_GDSC>;

   phys = <&pcie0_phy>;
   phy-names = "pciephy";

   operating-points-v2 = <&pcie0_opp_table>;

   status = "disabled";

   pcie0_opp_table: opp-table {
    compatible = "operating-points-v2";

    /* GEN 1 x1 */
    opp-2500000 {
     opp-hz = /bits/ 64 <2500000>;
     required-opps = <&rpmhpd_opp_low_svs>;
     opp-peak-kBps = <250000 1>;
    };

    /* GEN 1 x2 and GEN 2 x1 */
    opp-5000000 {
     opp-hz = /bits/ 64 <5000000>;
     required-opps = <&rpmhpd_opp_low_svs>;
     opp-peak-kBps = <500000 1>;
    };

    /* GEN 2 x2 */
    opp-10000000 {
     opp-hz = /bits/ 64 <10000000>;
     required-opps = <&rpmhpd_opp_low_svs>;
     opp-peak-kBps = <1000000 1>;
    };

    /* GEN 3 x1 */
    opp-8000000 {
     opp-hz = /bits/ 64 <8000000>;
     required-opps = <&rpmhpd_opp_nom>;
     opp-peak-kBps = <984500 1>;
    };

    /* GEN 3 x2 */
    opp-16000000 {
     opp-hz = /bits/ 64 <16000000>;
     required-opps = <&rpmhpd_opp_nom>;
     opp-peak-kBps = <1969000 1>;
    };
   };

   pcieport0: pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie0_phy: phy@1c06000 {
   compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
   reg = <0 0x01c06000 0 0x2000>;

   clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&tcsr TCSR_PCIE_0_CLKREF_EN>,
     <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
     <&gcc GCC_PCIE_0_PIPE_CLK>;
   clock-names = "aux", "cfg_ahb", "ref", "rchng",
          "pipe";

   resets = <&gcc GCC_PCIE_0_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
   assigned-clock-rates = <100000000>;

   power-domains = <&gcc PCIE_0_PHY_GDSC>;

   #clock-cells = <0>;
   clock-output-names = "pcie0_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  pcie1: pcie@1c08000 {
   device_type = "pci";
   compatible = "qcom,pcie-sm8550";
   reg = <0x0 0x01c08000 0x0 0x3000>,
         <0x0 0x40000000 0x0 0xf1d>,
         <0x0 0x40000f20 0x0 0xa8>,
         <0x0 0x40001000 0x0 0x1000>,
         <0x0 0x40100000 0x0 0x100000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <1>;
   num-lanes = <2>;

   interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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