Spracherkennung für: .dtsi vermutete Sprache: Unknown {[0] [0] [0]} [Methode: Schwerpunktbildung, einfache Gewichte, sechs Dimensionen]
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8650-camcc.h>
#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
bi_tcxo_div2: bi-tcxo-div2-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-mult = <1>;
clock-div = <2>;
};
bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK_A>;
clock-mult = <1>;
clock-div = <2>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a520";
reg = <0 0>;
clocks = <&cpufreq_hw 0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a520";
reg = <0 0x100>;
clocks = <&cpufreq_hw 0>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x200>;
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_200>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 3>;
operating-points-v2 = <&cpu2_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x300>;
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_300>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 3>;
operating-points-v2 = <&cpu2_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x400>;
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_400>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 3>;
operating-points-v2 = <&cpu2_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x500>;
clocks = <&cpufreq_hw 1>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_500>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu5_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x600>;
clocks = <&cpufreq_hw 1>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_600>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu5_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x4";
reg = <0 0x700>;
clocks = <&cpufreq_hw 2>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_700>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
core6 {
cpu = <&cpu6>;
};
core7 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "psci";
silver_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <550>;
exit-latency-us = <750>;
min-residency-us = <6700>;
local-timer-stop;
};
gold_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <600>;
exit-latency-us = <1300>;
min-residency-us = <8136>;
local-timer-stop;
};
gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-plus-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <500>;
exit-latency-us = <1350>;
min-residency-us = <7480>;
local-timer-stop;
};
};
domain-idle-states {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <750>;
exit-latency-us = <2350>;
min-residency-us = <9144>;
};
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2800>;
exit-latency-us = <4400>;
min-residency-us = <10150>;
};
};
};
ete-0 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu0>;
out-ports {
port {
ete0_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete0>;
};
};
};
};
ete-1 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu1>;
out-ports {
port {
ete1_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete1>;
};
};
};
};
ete-2 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu2>;
out-ports {
port {
ete2_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete2>;
};
};
};
};
ete-3 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu3>;
out-ports {
port {
ete3_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete3>;
};
};
};
};
ete-4 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu4>;
out-ports {
port {
ete4_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete4>;
};
};
};
};
ete-5 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu5>;
out-ports {
port {
ete5_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete5>;
};
};
};
};
ete-6 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu6>;
out-ports {
port {
ete6_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete6>;
};
};
};
};
ete-7 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu7>;
out-ports {
port {
ete7_out_funnel_ete: endpoint {
remote-endpoint = <&funnel_ete_in_ete7>;
};
};
};
};
funnel-ete {
compatible = "arm,coresight-static-funnel";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_ete_in_ete0: endpoint {
remote-endpoint = <&ete0_out_funnel_ete>;
};
};
port@1 {
reg = <1>;
funnel_ete_in_ete1: endpoint {
remote-endpoint = <&ete1_out_funnel_ete>;
};
};
port@2 {
reg = <2>;
funnel_ete_in_ete2: endpoint {
remote-endpoint = <&ete2_out_funnel_ete>;
};
};
port@3 {
reg = <3>;
funnel_ete_in_ete3: endpoint {
remote-endpoint = <&ete3_out_funnel_ete>;
};
};
port@4 {
reg = <4>;
funnel_ete_in_ete4: endpoint {
remote-endpoint = <&ete4_out_funnel_ete>;
};
};
port@5 {
reg = <5>;
funnel_ete_in_ete5: endpoint {
remote-endpoint = <&ete5_out_funnel_ete>;
};
};
port@6 {
reg = <6>;
funnel_ete_in_ete6: endpoint {
remote-endpoint = <&ete6_out_funnel_ete>;
};
};
port@7 {
reg = <7>;
funnel_ete_in_ete7: endpoint {
remote-endpoint = <&ete7_out_funnel_ete>;
};
};
};
out-ports {
port {
funnel_ete_out_funnel_apss: endpoint {
remote-endpoint = <&funnel_apss_in_funnel_ete>;
};
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8650", "qcom,scm";
qcom,dload-mode = <&tcsr 0x19000>;
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
};
clk_virt: interconnect-0 {
compatible = "qcom,sm8650-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-1 {
compatible = "qcom,sm8650-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
qup_opp_table_100mhz: opp-table-qup100mhz {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
};
qup_opp_table_120mhz: opp-table-qup120mhz {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-120000000 {
opp-hz = /bits/ 64 <120000000>;
required-opps = <&rpmhpd_opp_svs>;
};
};
qup_opp_table_128mhz: opp-table-qup128mhz {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-128000000 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_svs>;
};
};
qup_opp_table_240mhz: opp-table-qup240mhz {
compatible = "operating-points-v2";
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmhpd_opp_svs>;
};
};
memory@a0000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0xa0000000 0 0>;
};
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-364800000 {
opp-hz = /bits/ 64 <364800000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-460800000 {
opp-hz = /bits/ 64 <460800000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
};
opp-672000000 {
opp-hz = /bits/ 64 <672000000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
};
opp-787200000 {
opp-hz = /bits/ 64 <787200000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
};
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
};
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>;
};
opp-1132800000 {
opp-hz = /bits/ 64 <1132800000>;
opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>;
};
opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
};
opp-1459200000 {
opp-hz = /bits/ 64 <1459200000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
};
opp-1536000000 {
opp-hz = /bits/ 64 <1536000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
};
opp-1574400000 {
opp-hz = /bits/ 64 <1574400000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
};
opp-1689600000 {
opp-hz = /bits/ 64 <1689600000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
};
opp-1747200000 {
opp-hz = /bits/ 64 <1747200000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
};
opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
};
opp-1939200000 {
opp-hz = /bits/ 64 <1939200000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>;
};
opp-2265600000 {
opp-hz = /bits/ 64 <2265600000>;
opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>;
};
};
cpu2_opp_table: opp-table-cpu2 {
compatible = "operating-points-v2";
opp-shared;
opp-460800000 {
opp-hz = /bits/ 64 <460800000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-614400000 {
opp-hz = /bits/ 64 <614400000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
};
opp-691200000 {
opp-hz = /bits/ 64 <691200000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1152000000 {
opp-hz = /bits/ 64 <1152000000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1286400000 {
opp-hz = /bits/ 64 <1286400000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2131200000 {
opp-hz = /bits/ 64 <2131200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2246400000 {
opp-hz = /bits/ 64 <2246400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2304000000 {
opp-hz = /bits/ 64 <2304000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2323200000 {
opp-hz = /bits/ 64 <2323200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2380800000 {
opp-hz = /bits/ 64 <2380800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2438400000 {
opp-hz = /bits/ 64 <2438400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2515200000 {
opp-hz = /bits/ 64 <2515200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2572800000 {
opp-hz = /bits/ 64 <2572800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2630400000 {
opp-hz = /bits/ 64 <2630400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2707200000 {
opp-hz = /bits/ 64 <2707200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2764800000 {
opp-hz = /bits/ 64 <2764800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
};
opp-2841600000 {
opp-hz = /bits/ 64 <2841600000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2899200000 {
opp-hz = /bits/ 64 <2899200000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2956800000 {
opp-hz = /bits/ 64 <2956800000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3014400000 {
opp-hz = /bits/ 64 <3014400000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3072000000 {
opp-hz = /bits/ 64 <3072000000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3148800000 {
opp-hz = /bits/ 64 <3148800000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
};
};
cpu5_opp_table: opp-table-cpu5 {
compatible = "operating-points-v2";
opp-shared;
opp-460800000 {
opp-hz = /bits/ 64 <460800000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-614400000 {
opp-hz = /bits/ 64 <614400000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
};
opp-691200000 {
opp-hz = /bits/ 64 <691200000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1152000000 {
opp-hz = /bits/ 64 <1152000000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
};
opp-1267200000 {
opp-hz = /bits/ 64 <1267200000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1286400000 {
opp-hz = /bits/ 64 <1286400000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
};
opp-1497600000 {
opp-hz = /bits/ 64 <1497600000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>;
};
opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2131200000 {
opp-hz = /bits/ 64 <2131200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2188800000 {
opp-hz = /bits/ 64 <2188800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2246400000 {
opp-hz = /bits/ 64 <2246400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2304000000 {
opp-hz = /bits/ 64 <2304000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2323200000 {
opp-hz = /bits/ 64 <2323200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2380800000 {
opp-hz = /bits/ 64 <2380800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2438400000 {
opp-hz = /bits/ 64 <2438400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2515200000 {
opp-hz = /bits/ 64 <2515200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2572800000 {
opp-hz = /bits/ 64 <2572800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2630400000 {
opp-hz = /bits/ 64 <2630400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2707200000 {
opp-hz = /bits/ 64 <2707200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2764800000 {
opp-hz = /bits/ 64 <2764800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
};
opp-2841600000 {
opp-hz = /bits/ 64 <2841600000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2899200000 {
opp-hz = /bits/ 64 <2899200000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2956800000 {
opp-hz = /bits/ 64 <2956800000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3014400000 {
opp-hz = /bits/ 64 <3014400000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3072000000 {
opp-hz = /bits/ 64 <3072000000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3148800000 {
opp-hz = /bits/ 64 <3148800000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
};
};
cpu7_opp_table: opp-table-cpu7 {
compatible = "operating-points-v2";
opp-shared;
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
};
opp-614400000 {
opp-hz = /bits/ 64 <614400000>;
opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
};
opp-672000000 {
opp-hz = /bits/ 64 <672000000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-787200000 {
opp-hz = /bits/ 64 <787200000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>;
};
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1075200000 {
opp-hz = /bits/ 64 <1075200000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1132800000 {
opp-hz = /bits/ 64 <1132800000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1305600000 {
opp-hz = /bits/ 64 <1305600000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1363200000 {
opp-hz = /bits/ 64 <1363200000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>;
};
opp-1420800000 {
opp-hz = /bits/ 64 <1420800000>;
opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1670400000 {
opp-hz = /bits/ 64 <1670400000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>;
};
opp-1939200000 {
opp-hz = /bits/ 64 <1939200000>;
opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2169600000 {
opp-hz = /bits/ 64 <2169600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2246400000 {
opp-hz = /bits/ 64 <2246400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2304000000 {
opp-hz = /bits/ 64 <2304000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2342400000 {
opp-hz = /bits/ 64 <2342400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2380800000 {
opp-hz = /bits/ 64 <2380800000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2438400000 {
opp-hz = /bits/ 64 <2438400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2457600000 {
opp-hz = /bits/ 64 <2457600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2496000000 {
opp-hz = /bits/ 64 <2496000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2553600000 {
opp-hz = /bits/ 64 <2553600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>;
};
opp-2630400000 {
opp-hz = /bits/ 64 <2630400000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2688000000 {
opp-hz = /bits/ 64 <2688000000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>;
};
opp-2745600000 {
opp-hz = /bits/ 64 <2745600000>;
opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>;
};
opp-2803200000 {
opp-hz = /bits/ 64 <2803200000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2880000000 {
opp-hz = /bits/ 64 <2880000000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2937600000 {
opp-hz = /bits/ 64 <2937600000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-2995200000 {
opp-hz = /bits/ 64 <2995200000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3052800000 {
opp-hz = /bits/ 64 <3052800000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>;
};
opp-3187200000 {
opp-hz = /bits/ 64 <3187200000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
};
opp-3302400000 {
opp-hz = /bits/ 64 <3302400000>;
opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>;
};
};
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
};
pmu-a720 {
compatible = "arm,cortex-a720-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
};
pmu-x4 {
compatible = "arm,cortex-x4-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&silver_cpu_sleep_0>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&silver_cpu_sleep_0>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_cpu_sleep_0>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&gold_plus_cpu_sleep_0>;
};
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_sleep_0>,
<&cluster_sleep_1>;
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp@80000000 {
reg = <0 0x80000000 0 0xe00000>;
no-map;
};
cpusys_vm_mem: cpusys-vm@80e00000 {
reg = <0 0x80e00000 0 0x400000>;
no-map;
};
/* Merged xbl_dtlog, xbl_ramdump and aop_image regions */
xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
reg = <0 0x81a00000 0 0x260000>;
no-map;
};
aop_cmd_db_mem: aop-cmd-db@81c60000 {
compatible = "qcom,cmd-db";
reg = <0 0x81c60000 0 0x20000>;
no-map;
};
/* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */
aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
reg = <0 0x81c80000 0 0x75000>;
no-map;
};
/* Secdata region can be reused by apps */
smem: smem@81d00000 {
compatible = "qcom,smem";
reg = <0 0x81d00000 0 0x200000>;
hwlocks = <&tcsr_mutex 3>;
no-map;
};
adsp_mhi_mem: adsp-mhi@81f00000 {
reg = <0 0x81f00000 0 0x20000>;
no-map;
};
pvmfw_mem: pvmfw@824a0000 {
reg = <0 0x824a0000 0 0x100000>;
no-map;
};
global_sync_mem: global-sync@82600000 {
reg = <0 0x82600000 0 0x100000>;
no-map;
};
tz_stat_mem: tz-stat@82700000 {
reg = <0 0x82700000 0 0x100000>;
no-map;
};
qdss_mem: qdss@82800000 {
reg = <0 0x82800000 0 0x2000000>;
no-map;
};
qlink_logging_mem: qlink-logging@84800000 {
reg = <0 0x84800000 0 0x200000>;
no-map;
};
mpss_dsm_mem: mpss-dsm@86b00000 {
reg = <0 0x86b00000 0 0x4900000>;
no-map;
};
mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
reg = <0 0x8b400000 0 0x800000>;
no-map;
};
mpss_mem: mpss@8bc00000 {
reg = <0 0x8bc00000 0 0xf400000>;
no-map;
};
q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
reg = <0 0x9b000000 0 0x80000>;
no-map;
};
ipa_fw_mem: ipa-fw@9b080000 {
reg = <0 0x9b080000 0 0x10000>;
no-map;
};
ipa_gsi_mem: ipa-gsi@9b090000 {
reg = <0 0x9b090000 0 0xa000>;
no-map;
};
gpu_micro_code_mem: gpu-micro-code@9b09a000 {
reg = <0 0x9b09a000 0 0x2000>;
no-map;
};
spss_region_mem: spss@9b0a0000 {
reg = <0 0x9b0a0000 0 0x1e0000>;
no-map;
};
/* First part of the "SPU secure shared memory" region */
spu_tz_shared_mem: spu-tz-shared@9b280000 {
reg = <0 0x9b280000 0 0x60000>;
no-map;
};
/* Second part of the "SPU secure shared memory" region */
spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
reg = <0 0x9b2e0000 0 0x20000>;
no-map;
};
camera_mem: camera@9b300000 {
reg = <0 0x9b300000 0 0x800000>;
no-map;
};
video_mem: video@9bb00000 {
reg = <0 0x9bb00000 0 0x800000>;
no-map;
};
cvp_mem: cvp@9c300000 {
reg = <0 0x9c300000 0 0x700000>;
no-map;
};
cdsp_mem: cdsp@9ca00000 {
reg = <0 0x9ca00000 0 0x1400000>;
no-map;
};
q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
reg = <0 0x9de00000 0 0x80000>;
no-map;
};
q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
reg = <0 0x9de80000 0 0x80000>;
no-map;
};
adspslpi_mem: adspslpi@9df00000 {
reg = <0 0x9df00000 0 0x4080000>;
no-map;
};
rmtfs_mem: rmtfs@d7c00000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xd7c00000 0 0x400000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
};
/* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */
tz_merged_mem: tz-merged@d8000000 {
reg = <0 0xd8000000 0 0x800000>;
no-map;
};
hwfence_shbuf: hwfence-shbuf@e6440000 {
reg = <0 0xe6440000 0 0x2dd000>;
no-map;
};
trust_ui_vm_mem: trust-ui-vm@f3800000 {
reg = <0 0xf3800000 0 0x4400000>;
no-map;
};
oem_vm_mem: oem-vm@f7c00000 {
reg = <0 0xf7c00000 0 0x4c00000>;
no-map;
};
llcc_lpi_mem: llcc-lpi@ff800000 {
reg = <0 0xff800000 0 0x600000>;
no-map;
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <443>, <429>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <94>, <432>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <435>, <428>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
smp2p_modem_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_modem_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
ipa_smp2p_in: ipa-modem-to-ap {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0 0 0 0 0x10 0>;
ranges = <0 0 0 0 0x10 0>;
gcc: clock-controller@100000 {
compatible = "qcom,sm8650-gcc";
reg = <0 0x00100000 0 0x1f4200>;
clocks = <&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy QMP_PCIE_PIPE_CLK>,
<&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
ipcc: mailbox@406000 {
compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
reg = <0 0x00406000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>;
dma-channels = <12>;
dma-channel-mask = <0x3f>;
#dma-cells = <3>;
iommus = <&apps_smmu 0x436 0>;
dma-coherent;
status = "disabled";
};
qupv3_id_1: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0x423 0>;
dma-coherent;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c8: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00880000 0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c8_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0 0x00880000 0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00884000 0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c9_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi9: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0 0x00884000 0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00888000 0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c10_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0 0x00888000 0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c11_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0088c000 0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c12: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c12_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi12: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0 0x00890000 0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c13: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c13_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi13: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0 0x00894000 0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart14: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0 0x00898000 0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_128mhz>;
pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
pinctrl-names = "default";
status = "disabled";
};
uart15: serial@89c000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x0089c000 0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
pinctrl-0 = <&qup_uart15_default>;
pinctrl-names = "default";
status = "disabled";
};
};
i2c_master_hub_0: geniqup@9c0000 {
compatible = "qcom,geni-se-i2c-master-hub";
reg = <0 0x009c0000 0 0x2000>;
clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
clock-names = "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c_hub_0: i2c@980000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x00980000 0 0x4000>;
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
pinctrl-0 = <&hub_i2c0_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_1: i2c@984000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x00984000 0 0x4000>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
pinctrl-0 = <&hub_i2c1_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_2: i2c@988000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x00988000 0 0x4000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
pinctrl-0 = <&hub_i2c2_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_3: i2c@98c000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x0098c000 0 0x4000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
pinctrl-0 = <&hub_i2c3_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_4: i2c@990000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x00990000 0 0x4000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
pinctrl-0 = <&hub_i2c4_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_5: i2c@994000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x00994000 0 0x4000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
pinctrl-0 = <&hub_i2c5_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_6: i2c@998000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0 0x00998000 0 0x4000>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
--> --------------------
--> maximum size reached
--> --------------------
