Quelle sm8750.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
};
cpu6: cpu@10000 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu7: cpu@10100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
};
cluster1 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "psci";
cluster0_c4: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <93>;
exit-latency-us = <129>;
min-residency-us = <560>;
};
cluster1_c4: cpu-sleep-1 {
compatible = "arm,idle-state";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <172>;
exit-latency-us = <130>;
min-residency-us = <686>;
};
};
domain-idle-states {
cluster_cl5: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2150>;
exit-latency-us = <1983>;
min-residency-us = <9144>;
};
domain_ss3: domain-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x0200c354>;
entry-latency-us = <2800>;
exit-latency-us = <4400>;
min-residency-us = <10150>;
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8750", "qcom,scm";
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
};
clk_virt: interconnect-0 {
compatible = "qcom,sm8750-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-1 {
compatible = "qcom,sm8750-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
memory@a0000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0xa0000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cluster1_c4>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cluster1_c4>;
};
cluster0_pd: power-domain-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_cl5>;
power-domains = <&system_pd>;
};
cluster1_pd: power-domain-cluster1 {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_cl5>;
power-domains = <&system_pd>;
};
system_pd: power-domain-system {
#power-domain-cells = <0>;
domain-idle-states = <&domain_ss3>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
gunyah_hyp_mem: gunyah-hyp@80000000 {
reg = <0x0 0x80000000 0x0 0xe00000>;
no-map;
};
cpusys_vm_mem: cpusys-vm-mem@80e00000 {
reg = <0x0 0x80e00000 0x0 0x40000>;
no-map;
};
cpucp_mem: cpucp@81200000 {
reg = <0x0 0x81200000 0x0 0x200000>;
no-map;
};
xbl_dtlog_mem: xbl-dtlog@81a00000 {
reg = <0x0 0x81a00000 0x0 0x40000>;
no-map;
};
aop_image_mem: aop-image@81c00000 {
reg = <0x0 0x81c00000 0x0 0x60000>;
no-map;
};
aop_cmd_db_mem: aop-cmd-db@81c60000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x81c60000 0x0 0x20000>;
no-map;
};
/* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
reg = <0x0 0x81c80000 0x0 0x74000>;
no-map;
};
/* Secdata region can be reused by apps */
smem_mem: smem@81d00000 {
compatible = "qcom,smem";
reg = <0x0 0x81d00000 0x0 0x200000>;
hwlocks = <&tcsr_mutex 3>;
no-map;
};
pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
reg = <0x0 0x81f00000 0x0 0x100000>;
no-map;
};
cpucp_scandump_mem: cpucp-scandump@82000000 {
reg = <0x0 0x82000000 0x0 0x380000>;
no-map;
};
adsp_mhi_mem: adsp-mhi@82380000 {
reg = <0x0 0x82380000 0x0 0x20000>;
no-map;
};
soccp_sdi_mem: soccp-sdi@823a0000 {
reg = <0x0 0x823a0000 0x0 0x40000>;
no-map;
};
pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
reg = <0x0 0x823e0000 0x0 0x80000>;
no-map;
};
pvmfw_mem: pvmfw@824a0000 {
reg = <0x0 0x824a0000 0x0 0x100000>;
no-map;
};
global_sync_mem: global-sync@82600000 {
reg = <0x0 0x82600000 0x0 0x100000>;
no-map;
};
tz_stat_mem: tz-stat@82700000 {
reg = <0x0 0x82700000 0x0 0x100000>;
no-map;
};
qdss_mem: qdss@82800000 {
reg = <0x0 0x82800000 0x0 0x2000000>;
no-map;
};
dsm_partition_1_mem: dsm-partition-1@84a00000 {
reg = <0x0 0x84a00000 0x0 0x4900000>;
no-map;
};
dsm_partition_2_mem: dsm-partition-2@89300000 {
reg = <0x0 0x89300000 0x0 0xa80000>;
no-map;
};
mpss_mem: mpss@8ba00000 {
reg = <0x0 0x8ba00000 0x0 0xf600000>;
no-map;
};
q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
reg = <0x0 0x9b000000 0x0 0x80000>;
no-map;
};
ipa_fw_mem: ipa-fw@9b080000 {
reg = <0x0 0x9b080000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: ipa-gsi@9b090000 {
reg = <0x0 0x9b090000 0x0 0xa000>;
no-map;
};
gpu_micro_code_mem: gpu-micro-code@9b09a000 {
reg = <0x0 0x9b09a000 0x0 0x2000>;
no-map;
};
spss_region_mem: spss@9b0a0000 {
reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
no-map;
};
/* First part of the "SPU secure shared memory" region */
spu_tz_shared_mem: spu-tz-shared@9b280000 {
reg = <0x0 0x9b280000 0x0 0x40000>;
no-map;
};
/* Second part of the "SPU secure shared memory" region */
spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
reg = <0x0 0x9b2c0000 0x0 0x40000>;
no-map;
};
camera_mem: camera@9b300000 {
reg = <0x0 0x9b300000 0x0 0x800000>;
no-map;
};
camera_2_mem: camera-2@9bb00000 {
reg = <0x0 0x9bb00000 0x0 0x800000>;
no-map;
};
video_mem: video@9c300000 {
reg = <0x0 0x9c300000 0x0 0x800000>;
no-map;
};
cvp_mem: cvp@9cb00000 {
reg = <0x0 0x9cb00000 0x0 0x700000>;
no-map;
};
cdsp_mem: cdsp@9d200000 {
reg = <0x0 0x9d200000 0x0 0x1900000>;
no-map;
};
q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
reg = <0x0 0x9eb00000 0x0 0x80000>;
no-map;
};
soccp_mem: soccp@9ec00000 {
reg = <0x0 0x9ec00000 0x0 0x180000>;
no-map;
};
q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
reg = <0x0 0x9ed80000 0x0 0x80000>;
no-map;
};
adspslpi_mem: adspslpi@9ee00000 {
reg = <0x0 0x9ee00000 0x0 0x3a80000>;
no-map;
};
xbl_ramdump_mem: xbl-ramdump@b8000000 {
reg = <0x0 0xb8000000 0x0 0x1c0000>;
no-map;
};
hwfence_shbuf: hwfence-shbuf@d4e23000 {
no-map;
reg = <0x0 0xd4e23000 0x0 0x2dd000>;
};
/* Merged tz_reserved, xbl_sc, and qtee regions */
tz_merged_mem: tz-merged@d8000000 {
reg = <0x0 0xd8000000 0x0 0x600000>;
no-map;
};
trust_ui_vm_mem: trust-ui-vm@f3800000 {
reg = <0x0 0xf3800000 0x0 0x4400000>;
no-map;
};
oem_vm_mem: oem-vm@f7c00000 {
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
no-map;
};
llcc_lpi_mem: llcc-lpi@ff800000 {
reg = <0x0 0xff800000 0x0 0x800000>;
no-map;
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <443>, <429>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <94>, <432>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <435>, <428>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
smp2p_modem_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_modem_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
ipa_smp2p_in: ipa-modem-to-ap {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
/* TODO: smem mailbox in and out */
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0 0 0 0 0x10 0>;
ranges = <0 0 0 0 0x10 0>;
gcc: clock-controller@100000 {
compatible = "qcom,sm8750-gcc";
reg = <0x0 0x00100000 0x0 0x1f4200>;
clocks = <&bi_tcxo_div2>,
<0>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
ipcc: mailbox@406000 {
compatible = "qcom,sm8750-ipcc", "qcom,ipcc";
reg = <0x0 0x00406000 0x0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00800000 0x0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x1e>;
#dma-cells = <3>;
iommus = <&apps_smmu 0x436 0x0>;
status = "disabled";
};
qupv3_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0x423 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c8: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c8_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c9_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi9: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c10_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c11_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c12: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c12_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi12: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c13: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c13_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi13: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart14: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart14_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c15: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c15_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi15: spi@89c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
i2c_master_hub_0: geniqup@9c0000 {
compatible = "qcom,geni-se-i2c-master-hub";
reg = <0x0 0x009c0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
clock-names = "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c_hub_0: i2c@980000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00980000 0x0 0x4000>;
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c0_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_1: i2c@984000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00984000 0x0 0x4000>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c1_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_2: i2c@988000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00988000 0x0 0x4000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c2_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_3: i2c@98c000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x0098c000 0x0 0x4000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c3_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_4: i2c@990000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00990000 0x0 0x4000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c4_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_5: i2c@994000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00994000 0x0 0x4000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c5_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_6: i2c@998000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00998000 0x0 0x4000>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c6_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_7: i2c@99c000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x0099c000 0x0 0x4000>;
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c7_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_8: i2c@9a0000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x009a0000 0x0 0x4000>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c8_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_9: i2c@9a4000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x009a4000 0x0 0x4000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c9_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00a00000 0x0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x1e>;
#dma-cells = <3>;
iommus = <&apps_smmu 0xb6 0x0>;
status = "disabled";
};
qupv3_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xa3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c0_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c1_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c2_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c3_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c4_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c5_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c6_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@a98000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart7: serial@a9c000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a9c000 0x0 0x4000>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart7_default>;
pinctrl-names = "default";
status = "disabled";
};
};
rng: rng@10c3000 {
compatible = "qcom,sm8750-trng", "qcom,trng";
reg = <0x0 0x010c3000 0x0 0x1000>;
};
cnoc_main: interconnect@1500000 {
compatible = "qcom,sm8750-cnoc-main";
reg = <0x0 0x01500000 0x0 0x16080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
config_noc: interconnect@1600000 {
compatible = "qcom,sm8750-config-noc";
reg = <0x0 0x01600000 0x0 0x6200>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,sm8750-system-noc";
reg = <0x0 0x01680000 0x0 0x1d080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
pcie_noc: interconnect@16c0000 {
compatible = "qcom,sm8750-pcie-anoc";
reg = <0x0 0x016c0000 0x0 0x11400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8750-aggre1-noc";
reg = <0x0 0x016e0000 0x0 0x16400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm8750-aggre2-noc";
reg = <0x0 0x01700000 0x0 0x1f400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1780000 {
compatible = "qcom,sm8750-mmss-noc";
reg = <0x0 0x01780000 0x0 0x5b800>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
ice: crypto@1d88000 {
compatible = "qcom,sm8750-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0x0 0x01d88000 0x0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&apps_smmu 0x480 0>,
<&apps_smmu 0x481 0>;
qcom,ee = <0>;
qcom,controlled-remotely;
};
crypto: crypto@1dfa000 {
compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "memory";
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x480 0>,
<&apps_smmu 0x481 0>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
#hwlock-cells = <1>;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8750-mpss-pas";
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MSS>;
power-domain-names = "cx",
"mss";
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
<&dsm_partition_1_mem>,
<&dsm_partition_2_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <1>;
label = "mpss";
};
};
remoteproc_adsp: remoteproc@6800000 {
compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas";
reg = <0x0 0x06800000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx",
"lmx";
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <2>;
label = "lpass";
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1041 0x20>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06aa0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
#sound-dai-cells = <1>;
};
swr3: soundwire@6ab0000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x06ab0000 0x0 0x10000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsa2macro>;
clock-names = "iface";
label = "WSA2";
pinctrl-0 = <&wsa2_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_rxmacro: codec@6ac0000 {
compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
reg = <0x0 0x06ac0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr1: soundwire@6ad0000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x06ad0000 0x0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_rxmacro>;
clock-names = "iface";
label = "RX";
pinctrl-0 = <&rx_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <1>;
qcom,dout-ports = <11>;
qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_txmacro: codec@6ae0000 {
compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
reg = <0x0 0x06ae0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
lpass_wsamacro: codec@6b00000 {
compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06b00000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr0: soundwire@6b10000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x06b10000 0x0 0x10000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsamacro>;
clock-names = "iface";
label = "WSA";
pinctrl-0 = <&wsa_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,sm8750-lpass-ag-noc";
reg = <0x0 0x07e40000 0x0 0xe080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,sm8750-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
lpass_lpicx_noc: interconnect@7420000 {
compatible = "qcom,sm8750-lpass-lpicx-noc";
reg = <0x0 0x07420000 0x0 0x44080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
swr2: soundwire@7630000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x07630000 0x0 0x10000>;
interrupts = <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
clocks = <&lpass_txmacro>;
clock-names = "iface";
label = "TX";
pinctrl-0 = <&tx_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_vamacro: codec@7660000 {
compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
reg = <0x0 0x07660000 0x0 0x2000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
--> --------------------
--> maximum size reached
--> --------------------
[ Dauer der Verarbeitung: 0.19 Sekunden
(vorverarbeitet)
]
|
2026-04-06
|
