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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
/*
* DA7212 Codec settings
*
* for Playback
* > amixer set "Headphone" 40%
* > amixer set "Headphone" on
* > amixer set "Mixout Left DAC Left" on
* > amixer set "Mixout Right DAC Right" on
* > aplay xxx.wav
*
* for Capture (Aux/Mic)
*
* on/off (B)
* CONN3 (HeadSet) ---+----> MSIOF1
* |
* CONN4 AUX ---------+ on/off (A)
*
* > amixer set "Mixin PGA" on
* > amixer set "Mixin PGA" 50%
* > amixer set "ADC" on
* > amixer set "ADC" 80%
* > amixer set "Aux" on ^
* > amixer set "Aux" 80% | (A)
* > amixer set "Mixin Left Aux Left" on |
* > amixer set "Mixin Right Aux Right" on v
* > amixer set "Mic 1" on ^
* > amixer set "Mic 1" 80% | (B)
* > amixer set "Mixin Left Mic 1" on |
* > amixer set "Mixin Right Mic 1" on v
* > arecord -f cd xxx.wav
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "r8a779g3.dtsi"
/ {
model = "Retronix Sparrow Hawk board based on r8a779g3";
compatible = "retronix,sparrow-hawk", "renesas,r8a779g3",
"renesas,r8a779g0";
aliases {
ethernet0 = &avb0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &hscif0;
serial1 = &hscif1;
serial2 = &hscif3;
spi0 = &rpc;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
/* Page 31 / FAN */
fan: pwm-fan {
pinctrl-0 = <&irq4_pins>;
pinctrl-names = "default";
compatible = "pwm-fan";
#cooling-cells = <2>;
interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>;
/*
* The fan model connected to this device can be selected
* by user. Set "cooling-levels" DT property to single 255
* entry to force the fan PWM into constant HIGH, which
* forces the fan to spin at maximum RPM, thus providing
* maximum cooling to this device and protection against
* misconfigured PWM duty cycle to the fan.
*
* User has to configure "pwms" and "pulses-per-revolution"
* DT properties according to fan datasheet first, and then
* extend "cooling-levels = <0 m n ... 255>" property to
* achieve proper fan control compatible with fan model
* installed by user.
*/
cooling-levels = <255>;
pulses-per-revolution = <2>;
pwms = <&pwm0 0 50000>;
};
/*
* Page 15 / LPDDR5
*
* This configuration listed below is for the 8 GiB board variant
* with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board.
*
* A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on
* the board is automatically handled by the bootloader, which
* adjusts the correct DRAM size into the memory nodes below.
*/
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
/* Page 27 / DSI to Display */
mini-dp-con {
compatible = "dp-connector";
label = "CN6";
type = "full-size";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
/* Page 26 / PCIe.0/1 CLK */
pcie_refclk: clk-x8 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* Page 27 / DSI to Display */
sn65dsi86_refclk: clk-x9 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
/* Page 30 / Audio_Codec */
sound_card: sound {
compatible = "audio-graph-card2";
links = <&msiof1_snd>;
};
/* Page 17 uSD-Slot */
vcc_sdhi: regulator-vcc-sdhi {
compatible = "regulator-gpio";
regulator-name = "SDHI VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <1800000 0>, <3300000 1>;
};
};
&audio_clkin {
clock-frequency = <24576000>;
};
/* Page 22 / Ether_AVB0 */
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&avb0_phy>;
tx-internal-delay-ps = <2000>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
/* AVB0_PHY_INT_V */
interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>;
/* GP7_10/AVB0_RESETN_V */
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
/* Page 28 / CANFD_IF */
&can_clk {
clock-frequency = <40000000>;
};
/* Page 28 / CANFD_IF */
&canfd {
pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel3 {
status = "okay";
};
channel4 {
status = "okay";
};
};
/* Page 27 / DSI to Display */
&dsi1 {
status = "okay";
ports {
port@1 {
dsi1_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
/* Page 27 / DSI to Display */
&du {
status = "okay";
};
/* Page 5 / R-Car V4H_INT_I2C */
&extal_clk { /* X3 */
clock-frequency = <16666666>;
};
/* Page 5 / R-Car V4H_INT_I2C */
&extalr_clk { /* X2 */
clock-frequency = <32768>;
};
/* Page 26 / 2230 Key M M.2 */
&gpio4 {
/* 9FGV0441 nOE inputs 0 and 1 */
pcie-m2-oe-hog {
gpio-hog;
gpios = <21 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PCIe-CLK-nOE-M2";
};
/* 9FGV0441 nOE inputs 2 and 3 */
pcie-usb-oe-hog {
gpio-hog;
gpios = <22 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PCIe-CLK-nOE-USB";
};
};
/* Page 23 / DEBUG */
&hscif0 { /* FTDI ADBUS[3:0] */
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bootph-all;
status = "okay";
};
/* Page 23 / DEBUG */
&hscif1 { /* FTDI BDBUS[3:0] */
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
/* Page 24 / UART */
&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */
pinctrl-0 = <&hscif3_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 24 / I2C SWITCH */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
mux@71 {
compatible = "nxp,pca9544"; /* TCA9544 */
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
vdd-supply = <®_3p3v>;
i2c0_mux0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
/* Page 27 / DSI to Display */
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
vccio-supply = <®_1p8v>;
vpll-supply = <®_1p8v>;
vcca-supply = <®_1p2v>;
vcc-supply = <®_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
i2c0_mux1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Page 30 / Audio_Codec */
codec@1a {
compatible = "dlg,da7212";
#sound-dai-cells = <0>;
reg = <0x1a>;
clocks = <&rcar_sound>;
clock-names = "mclk";
VDDA-supply = <®_1p8v>;
VDDMIC-supply = <®_3p3v>;
VDDIO-supply = <®_3p3v>;
port {
da7212_endpoint: endpoint {
bitclock-master;
frame-master;
remote-endpoint = <&msiof1_snd_endpoint>;
};
};
};
};
i2c0_mux2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Page 26 / PCIe.0/1 CLK */
pcie_clk: clk@68 {
compatible = "renesas,9fgv0441";
reg = <0x68>;
clocks = <&pcie_refclk>;
#clock-cells = <1>;
};
};
i2c0_mux3: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* Page 29 / CSI_IF_CN / CAM_CN0 */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
};
/* Page 29 / CSI_IF_CN / CAM_CN1 */
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
};
/* Page 31 / IO_CN */
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
};
/* Page 31 / IO_CN */
&i2c4 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */
&i2c5 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-names = "default";
};
/* Page 17 uSD-Slot */
&mmc0 {
pinctrl-0 = <&sd_pins>;
pinctrl-1 = <&sd_uhs_pins>;
pinctrl-names = "default", "state_uhs";
bus-width = <4>;
cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <®_3p3v>;
vqmmc-supply = <&vcc_sdhi>;
status = "okay";
};
&msiof1 {
pinctrl-0 = <&msiof1_pins>;
pinctrl-names = "default";
status = "okay";
/* ignore DT warning */
/delete-property/#address-cells;
/delete-property/#size-cells;
msiof1_snd: port {
msiof1_snd_endpoint: endpoint {
remote-endpoint = <&da7212_endpoint>;
};
};
};
/* Page 26 / 2230 Key M M.2 */
&pcie0_clkref {
status = "disabled";
};
&pciec0 {
clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>;
reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pciec0_rp {
clocks = <&pcie_clk 1>;
vpcie3v3-supply = <®_3p3v>;
};
/* Page 25 / PCIe to USB */
&pcie1_clkref {
status = "disabled";
};
&pciec1 {
clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>;
/* uPD720201 is PCIe Gen2 x1 device */
num-lanes = <1>;
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pciec1_rp {
clocks = <&pcie_clk 3>;
vpcie3v3-supply = <®_3p3v>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
/* Page 22 / Ether_AVB0 */
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins-mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins-mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
pins-vddq18-25-avb {
pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0";
power-source = <1800>;
};
};
/* Page 28 / CANFD_IF */
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
/* Page 28 / CANFD_IF */
canfd3_pins: canfd3 {
groups = "canfd3_data";
function = "canfd3";
};
/* Page 28 / CANFD_IF */
canfd4_pins: canfd4 {
groups = "canfd4_data";
function = "canfd4";
};
/* Page 23 / DEBUG */
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
/* Page 23 / DEBUG */
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
/* Page 24 / UART */
hscif3_pins: hscif3 {
groups = "hscif3_data_a";
function = "hscif3";
};
/* Page 24 / I2C SWITCH */
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
/* Page 29 / CSI_IF_CN / CAM_CN0 */
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
/* Page 29 / CSI_IF_CN / CAM_CN1 */
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
/* Page 31 / IO_CN */
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
/* Page 31 / IO_CN */
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
/* Page 18 / POWER_CORE */
i2c5_pins: i2c5 {
groups = "i2c5";
function = "i2c5";
};
/* Page 27 / DSI to Display */
irq0_pins: irq0 {
groups = "intc_ex_irq0_a";
function = "intc_ex";
};
/* Page 31 / FAN */
irq4_pins: irq4 {
groups = "intc_ex_irq4_b";
function = "intc_ex";
};
/* Page 31 / FAN */
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
/* Page 31 / CN7 pin 12 */
pwm1_pins: pwm1 {
groups = "pwm1_b";
function = "pwm1";
};
/* Page 31 / CN7 pin 32 */
pwm6_pins: pwm6 {
groups = "pwm6";
function = "pwm6";
};
/* Page 31 / CN7 pin 33 */
pwm7_pins: pwm7 {
groups = "pwm7";
function = "pwm7";
};
/* Page 16 / QSPI_FLASH */
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
bootph-all;
};
/* Page 6 / SCIF_CLK_SOC_V */
scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
/* Page 17 uSD-Slot */
sd_pins: sd {
groups = "mmc_data4", "mmc_ctrl";
function = "mmc";
power-source = <3300>;
};
/* Page 17 uSD-Slot */
sd_uhs_pins: sd-uhs {
groups = "mmc_data4", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
/* Page 30 / Audio_Codec */
msiof1_pins: sound {
groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd";
function = "msiof1";
};
/* Page 30 / Audio_Codec */
sound_clk_pins: sound-clk {
groups = "audio_clkin", "audio_clkout";
function = "audio_clk";
};
};
/* Page 31 / FAN */
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 31 / CN7 pin 12 */
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 31 / CN7 pin 32 */
&pwm6 {
pinctrl-0 = <&pwm6_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 31 / CN7 pin 33 */
&pwm7 {
pinctrl-0 = <&pwm7_pins>;
pinctrl-names = "default";
status = "okay";
};
/* Page 30 / Audio_Codec */
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
/* It is used for ADG output as DA7212_MCLK */
/* audio_clkout */
clock-frequency = <12288000>; /* 48 kHz groups */
status = "okay";
};
/* Page 16 / QSPI_FLASH */
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
bootph-all;
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
bootph-all;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1000000>;
read-only;
};
user@1000000 {
reg = <0x1000000 0x2f80000>;
};
env1@3f80000 {
reg = <0x3f80000 0x40000>;
};
env2@3fc0000 {
reg = <0x3fc0000 0x40000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
/* Page 6 / SCIF_CLK_SOC_V */
&scif_clk { /* X12 */
clock-frequency = <24000000>;
};
[ Verzeichnis aufwärts0.61unsichere Verbindung
]
