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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals
*
* Copyright (C) 2022-2024 Texas Instruments Incorporated -
https://www.ti.com/
*/
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-ti.h>
#include "k3-serdes.h"
/ {
serdes_refclk: clock-serdes {
#clock-cells = <0>;
compatible = "fixed-clock";
/* To be enabled when serdes_wiz* is functional */
status = "disabled";
};
};
&cbass_main {
/*
* MSMC is configured by bootloaders and a runtime fixup is done in the
* DT for this node
*/
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x70000000 0x800000>;
atf-sram@0 {
reg = <0x00 0x20000>;
};
tifs-sram@1f0000 {
reg = <0x1f0000 0x10000>;
};
l3cache-sram@200000 {
reg = <0x200000 0x200000>;
};
};
scm_conf: bus@100000 {
compatible = "simple-bus";
reg = <0x00 0x00100000 0x00 0x1c000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
cpsw1_phy_gmii_sel: phy@4034 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4034 0x4>;
#phy-cells = <1>;
};
cpsw0_phy_gmii_sel: phy@4044 {
compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
reg = <0x4044 0x20>;
#phy-cells = <1>;
ti,qsgmii-main-ports = <7>, <7>;
};
pcie0_ctrl: pcie0-ctrl@4070 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4070 0x4>;
};
pcie1_ctrl: pcie1-ctrl@4074 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4074 0x4>;
};
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x00004080 0x50>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
<0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */
<0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
<0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */
<0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
<0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */
<0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
<0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
<J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_IP3_UNUSED>,
<J784S4_SERDES0_LANE3_USB>,
<J784S4_SERDES1_LANE0_PCIE0_LANE0>,
<J784S4_SERDES1_LANE1_PCIE0_LANE1>,
<J784S4_SERDES1_LANE2_PCIE0_LANE2>,
<J784S4_SERDES1_LANE3_PCIE0_LANE3>,
<J784S4_SERDES2_LANE0_IP2_UNUSED>,
<J784S4_SERDES2_LANE1_IP2_UNUSED>,
<J784S4_SERDES2_LANE2_QSGMII_LANE1>,
<J784S4_SERDES2_LANE3_QSGMII_LANE2>,
<J784S4_SERDES4_LANE0_EDP_LANE0>,
<J784S4_SERDES4_LANE1_EDP_LANE1>,
<J784S4_SERDES4_LANE2_EDP_LANE2>,
<J784S4_SERDES4_LANE3_EDP_LANE3>;
};
usb_serdes_mux: mux-controller@4000 {
compatible = "reg-mux";
reg = <0x4000 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
};
ehrpwm_tbclk: clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
audio_refclk1: clock@82e4 {
compatible = "ti,am62-audio-refclk";
reg = <0x82e4 0x4>;
clocks = <&k3_clks 157 34>;
assigned-clocks = <&k3_clks 157 34>;
assigned-clock-parents = <&k3_clks 157 63>;
#clock-cells = <0>;
};
acspcie0_proxy_ctrl: clock-controller@1a090 {
compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
reg = <0x1a090 0x4>;
};
acspcie1_proxy_ctrl: clock-controller@1a094 {
compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
reg = <0x1a094 0x4>;
};
};
main_ehrpwm0: pwm@3000000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
reg = <0x00 0x3000000 0x00 0x100>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
clock-names = "tbclk", "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
#pwm-cells = <3>;
status = "disabled";
};
main_ehrpwm1: pwm@3010000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
reg = <0x00 0x3010000 0x00 0x100>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
clock-names = "tbclk", "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
#pwm-cells = <3>;
status = "disabled";
};
main_ehrpwm2: pwm@3020000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
reg = <0x00 0x3020000 0x00 0x100>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
clock-names = "tbclk", "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
#pwm-cells = <3>;
status = "disabled";
};
main_ehrpwm3: pwm@3030000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
reg = <0x00 0x3030000 0x00 0x100>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
clock-names = "tbclk", "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
#pwm-cells = <3>;
status = "disabled";
};
main_ehrpwm4: pwm@3040000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
reg = <0x00 0x3040000 0x00 0x100>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
clock-names = "tbclk", "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
#pwm-cells = <3>;
status = "disabled";
};
main_ehrpwm5: pwm@3050000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
reg = <0x00 0x3050000 0x00 0x100>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
clock-names = "tbclk", "fck";
power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>;
#pwm-cells = <3>;
status = "disabled";
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>, /* GICR */
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <10>;
ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c000 0x00 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x00 0x104200 0x00 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000007>;
};
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "ti,j7200-padconf", "pinctrl-single";
reg = <0x00 0x104280 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000001f>;
};
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x4e00000 0x00 0x1200>;
power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
<&main_udmap 0x4a41>;
dma-names = "tx", "rx1", "rx2";
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x00 0x4e10000 0x00 0x7d>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
};
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 97 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 97 2>;
assigned-clock-parents = <&k3_clks 97 3>;
power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 98 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 98 2>;
assigned-clock-parents = <&k3_clks 98 3>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 99 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 99 2>;
assigned-clock-parents = <&k3_clks 99 3>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 100 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 100 2>;
assigned-clock-parents = <&k3_clks 100 3>;
power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 101 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 101 2>;
assigned-clock-parents = <&k3_clks 101 3>;
power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 102 2>;
assigned-clock-parents = <&k3_clks 102 3>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 103 2>;
assigned-clock-parents = <&k3_clks 103 3>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 104 2>;
assigned-clock-parents = <&k3_clks 104 3>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 105 2>;
assigned-clock-parents = <&k3_clks 105 3>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 106 2>;
assigned-clock-parents = <&k3_clks 106 3>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 107 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 107 2>;
assigned-clock-parents = <&k3_clks 107 3>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 108 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 108 2>;
assigned-clock-parents = <&k3_clks 108 3>;
power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer12: timer@24c0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24c0000 0x00 0x400>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 109 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 109 2>;
assigned-clock-parents = <&k3_clks 109 3>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer13: timer@24d0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24d0000 0x00 0x400>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 110 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 110 2>;
assigned-clock-parents = <&k3_clks 110 3>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer14: timer@24e0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24e0000 0x00 0x400>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 111 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 111 2>;
assigned-clock-parents = <&k3_clks 111 3>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer15: timer@24f0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24f0000 0x00 0x400>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 112 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 112 2>;
assigned-clock-parents = <&k3_clks 112 3>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer16: timer@2500000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2500000 0x00 0x400>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 113 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 113 2>;
assigned-clock-parents = <&k3_clks 113 3>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer17: timer@2510000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2510000 0x00 0x400>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 114 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 114 2>;
assigned-clock-parents = <&k3_clks 114 3>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer18: timer@2520000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2520000 0x00 0x400>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 115 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 115 2>;
assigned-clock-parents = <&k3_clks 115 3>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer19: timer@2530000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2530000 0x00 0x400>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 116 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 116 2>;
assigned-clock-parents = <&k3_clks 116 3>;
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x200>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 388 0>;
clock-names = "fclk";
power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x200>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 389 0>;
clock-names = "fclk";
power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x200>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 390 0>;
clock-names = "fclk";
power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x200>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 391 0>;
clock-names = "fclk";
power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x200>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 392 0>;
clock-names = "fclk";
power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x200>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 393 0>;
clock-names = "fclk";
power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x200>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 394 0>;
clock-names = "fclk";
power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x200>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 395 0>;
clock-names = "fclk";
power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x200>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 396 0>;
clock-names = "fclk";
power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <145>, <146>, <147>, <148>, <149>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 163 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio2: gpio@610000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00610000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <154>, <155>, <156>, <157>, <158>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 164 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio4: gpio@620000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00620000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <163>, <164>, <165>, <166>, <167>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 165 0>;
clock-names = "gpio";
status = "disabled";
};
main_gpio6: gpio@630000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00630000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <172>, <173>, <174>, <175>, <176>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 166 0>;
clock-names = "gpio";
status = "disabled";
};
usbss0: usb@4104000 {
bootph-all;
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
dma-coherent;
power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled"; /* Needs lane config */
usb0: usb@6000000 {
bootph-all;
compatible = "cdns,usb3";
reg = <0x00 0x6000000 0x00 0x10000>,
<0x00 0x6010000 0x00 0x10000>,
<0x00 0x6020000 0x00 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
interrupt-names = "host",
"peripheral",
"otg";
};
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02000000 0x00 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 270 2>;
clock-names = "fck";
power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c1: i2c@2010000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02010000 0x00 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 271 2>;
clock-names = "fck";
power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c2: i2c@2020000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02020000 0x00 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 272 2>;
clock-names = "fck";
power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c3: i2c@2030000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02030000 0x00 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 273 2>;
clock-names = "fck";
power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c4: i2c@2040000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02040000 0x00 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 274 2>;
clock-names = "fck";
power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c5: i2c@2050000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02050000 0x00 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 275 2>;
clock-names = "fck";
power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c6: i2c@2060000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02060000 0x00 0x100>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 276 2>;
clock-names = "fck";
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
ti_csi2rx0: ticsi2rx@4500000 {
compatible = "ti,j721e-csi2rx-shim";
reg = <0x00 0x04500000 0x00 0x00001000>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
dmas = <&main_bcdma_csi 0 0x4940 0>;
dma-names = "rx0";
power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
cdns_csi2rx0: csi-bridge@4504000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x04504000 0x00 0x00001000>;
clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
<&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi0_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi0_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi0_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi0_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
ti_csi2rx1: ticsi2rx@4510000 {
compatible = "ti,j721e-csi2rx-shim";
reg = <0x00 0x04510000 0x00 0x1000>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
dmas = <&main_bcdma_csi 0 0x4960 0>;
dma-names = "rx0";
power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
cdns_csi2rx1: csi-bridge@4514000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x04514000 0x00 0x00001000>;
clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
<&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy1>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi1_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi1_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi1_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi1_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi1_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
ti_csi2rx2: ticsi2rx@4520000 {
compatible = "ti,j721e-csi2rx-shim";
reg = <0x00 0x04520000 0x00 0x00001000>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
dmas = <&main_bcdma_csi 0 0x4980 0>;
dma-names = "rx0";
power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
cdns_csi2rx2: csi-bridge@4524000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x04524000 0x00 0x00001000>;
clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
<&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy2>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi2_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi2_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi2_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi2_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
dphy0: phy@4580000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x04580000 0x00 0x00001100>;
#phy-cells = <0>;
power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
dphy1: phy@4590000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x04590000 0x00 0x00001100>;
#phy-cells = <0>;
power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
dphy2: phy@45a0000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x045a0000 0x00 0x00001100>;
#phy-cells = <0>;
power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
vpu0: video-codec@4210000 {
compatible = "ti,j721s2-wave521c", "cnm,wave521c";
reg = <0x00 0x4210000 0x00 0x10000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 241 2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
};
vpu1: video-codec@4220000 {
compatible = "ti,j721s2-wave521c", "cnm,wave521c";
reg = <0x00 0x4220000 0x00 0x10000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 242 2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
};
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
<0x00 0x04f88000 0x00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 140 2>;
assigned-clock-parents = <&k3_clks 140 3>;
bus-width = <8>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
status = "disabled";
};
main_sdhci1: mmc@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x00 0x04fb0000 0x00 0x1000>,
<0x00 0x04fb8000 0x00 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 141 4>;
assigned-clock-parents = <&k3_clks 141 5>;
bus-width = <4>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
pcie0_rc: pcie@2900000 {
compatible = "ti,j784s4-pcie-host";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 332 0>;
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb012>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
<0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM
(4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
pcie1_rc: pcie@2910000 {
compatible = "ti,j784s4-pcie-host";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 333 0>;
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb012>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
dma-coherent;
ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
<0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
serdes_wiz0: wiz@5060000 {
compatible = "ti,j784s4-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
assigned-clocks = <&k3_clks 404 6>;
assigned-clock-parents = <&k3_clks 404 10>;
num-lanes = <4>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x5060000 0x00 0x5060000 0x10000>;
status = "disabled";
serdes0: serdes@5060000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x05060000 0x010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 404 6>,
<&k3_clks 404 6>,
<&k3_clks 404 6>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
status = "disabled";
};
};
serdes_wiz1: wiz@5070000 {
compatible = "ti,j784s4-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
assigned-clocks = <&k3_clks 405 6>;
assigned-clock-parents = <&k3_clks 405 10>;
num-lanes = <4>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x05070000 0x00 0x05070000 0x10000>;
status = "disabled";
serdes1: serdes@5070000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x05070000 0x010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz1 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 405 6>,
<&k3_clks 405 6>,
<&k3_clks 405 6>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
status = "disabled";
};
};
serdes_wiz4: wiz@5050000 {
compatible = "ti,j784s4-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
assigned-clocks = <&k3_clks 407 6>;
assigned-clock-parents = <&k3_clks 407 10>;
num-lanes = <4>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x05050000 0x00 0x05050000 0x10000>,
<0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
status = "disabled";
serdes4: serdes@5050000 {
/*
* Note: we also map DPTX PHY registers as the Torrent
* needs to manage those.
*/
compatible = "ti,j721e-serdes-10g";
reg = <0x05050000 0x010000>,
<0x0a030a00 0x40>; /* DPTX PHY */
reg-names = "torrent_phy";
resets = <&serdes_wiz4 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 407 6>,
<&k3_clks 407 6>,
<&k3_clks 407 6>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
status = "disabled";
};
};
main_navss: bus@30000000 {
bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <280>;
dma-coherent;
dma-ranges;
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <283>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>,
<128 672 64>;
};
main_udmass_inta: msi-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x00 0x33d00000 0x00 0x100000>;
interrupt-controller;
#interrupt-cells = <0>;
interrupt-parent = <&main_navss_intr>;
msi-controller;
ti,sci = <&sms>;
ti,sci-dev-id = <321>;
ti,interrupt-ranges = <0 0 256>;
ti,unmapped-event-sources = <&main_bcdma_csi>;
};
secure_proxy_main: mailbox@32c00000 {
bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
hwspinlock: hwlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f80000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f81000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f82000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f83000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f84000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f85000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f86000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f87000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f88000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f89000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster0: mailbox@31f90000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f90000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster1: mailbox@31f91000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f91000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster2: mailbox@31f92000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f92000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster3: mailbox@31f93000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f93000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster4: mailbox@31f94000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f94000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster5: mailbox@31f95000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f95000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster6: mailbox@31f96000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f96000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster7: mailbox@31f97000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f97000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster8: mailbox@31f98000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f98000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster9: mailbox@31f99000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f99000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster10: mailbox@31f9a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster11: mailbox@31f9b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x3c000000 0x00 0x400000>,
<0x00 0x38000000 0x00 0x400000>,
<0x00 0x31120000 0x00 0x100>,
<0x00 0x33000000 0x00 0x40000>,
<0x00 0x31080000 0x00 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <315>;
msi-parent = <&main_udmass_inta>;
};
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x80000>,
<0x00 0x35000000 0x00 0x200000>,
<0x00 0x30b00000 0x00 0x20000>,
<0x00 0x30c00000 0x00 0x8000>,
<0x00 0x30d00000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <319>;
ti,ringacc = <&main_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>, /* TX_HCHAN */
<0x10>; /* TX_UHCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>, /* RX_HCHAN */
<0x0c>; /* RX_UHCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
main_bcdma_csi: dma-controller@311a0000 {
compatible = "ti,j721s2-dmss-bcdma-csi";
reg = <0x00 0x311a0000 0x00 0x100>,
<0x00 0x35d00000 0x00 0x20000>,
<0x00 0x35c00000 0x00 0x10000>,
<0x00 0x35e00000 0x00 0x80000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <3>;
ti,sci = <&sms>;
ti,sci-dev-id = <281>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x00 0x310d0000 0x00 0x400>;
reg-names = "cpts";
clocks = <&k3_clks 282 0>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
};
main_cpsw0: ethernet@c000000 {
compatible = "ti,j784s4-cpswxg-nuss";
reg = <0x00 0xc000000 0x00 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
clocks = <&k3_clks 64 0>;
clock-names = "fck";
power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_udmap 0xca00>,
<&main_udmap 0xca01>,
<&main_udmap 0xca02>,
<&main_udmap 0xca03>,
<&main_udmap 0xca04>,
<&main_udmap 0xca05>,
<&main_udmap 0xca06>,
<&main_udmap 0xca07>,
<&main_udmap 0x4a00>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
status = "disabled";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
main_cpsw0_port1: port@1 {
reg = <1>;
label = "port1";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port2: port@2 {
reg = <2>;
label = "port2";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port3: port@3 {
reg = <3>;
label = "port3";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port4: port@4 {
reg = <4>;
label = "port4";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port5: port@5 {
reg = <5>;
label = "port5";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port6: port@6 {
reg = <6>;
label = "port6";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port7: port@7 {
reg = <7>;
label = "port7";
ti,mac-only;
status = "disabled";
};
main_cpsw0_port8: port@8 {
reg = <8>;
label = "port8";
ti,mac-only;
status = "disabled";
};
};
main_cpsw0_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x00 0xf00 0x00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 64 0>;
clock-names = "fck";
bus_freq = <1000000>;
status = "disabled";
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x00 0x3d000 0x00 0x400>;
clocks = <&k3_clks 64 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
main_cpsw1: ethernet@c200000 {
compatible = "ti,j721e-cpsw-nuss";
reg = <0x00 0xc200000 0x00 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
clocks = <&k3_clks 62 0>;
clock-names = "fck";
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_udmap 0xc640>,
<&main_udmap 0xc641>,
<&main_udmap 0xc642>,
<&main_udmap 0xc643>,
<&main_udmap 0xc644>,
<&main_udmap 0xc645>,
<&main_udmap 0xc646>,
<&main_udmap 0xc647>,
<&main_udmap 0x4640>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
status = "disabled";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
main_cpsw1_port1: port@1 {
reg = <1>;
label = "port1";
phys = <&cpsw1_phy_gmii_sel 1>;
ti,mac-only;
status = "disabled";
};
};
main_cpsw1_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
reg = <0x00 0xf00 0x00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 62 0>;
clock-names = "fck";
bus_freq = <1000000>;
status = "disabled";
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x00 0x3d000 0x00 0x400>;
clocks = <&k3_clks 62 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
<0x00 0x02708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 245 6>, <&k3_clks 245 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan1: can@2711000 {
compatible = "bosch,m_can";
reg = <0x00 0x02711000 0x00 0x200>,
<0x00 0x02718000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 246 6>, <&k3_clks 246 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan2: can@2721000 {
compatible = "bosch,m_can";
reg = <0x00 0x02721000 0x00 0x200>,
<0x00 0x02728000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 247 6>, <&k3_clks 247 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan3: can@2731000 {
compatible = "bosch,m_can";
reg = <0x00 0x02731000 0x00 0x200>,
<0x00 0x02738000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 248 6>, <&k3_clks 248 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan4: can@2741000 {
compatible = "bosch,m_can";
reg = <0x00 0x02741000 0x00 0x200>,
<0x00 0x02748000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 249 6>, <&k3_clks 249 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan5: can@2751000 {
compatible = "bosch,m_can";
reg = <0x00 0x02751000 0x00 0x200>,
<0x00 0x02758000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 250 6>, <&k3_clks 250 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan6: can@2761000 {
compatible = "bosch,m_can";
reg = <0x00 0x02761000 0x00 0x200>,
<0x00 0x02768000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 251 6>, <&k3_clks 251 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan7: can@2771000 {
compatible = "bosch,m_can";
reg = <0x00 0x02771000 0x00 0x200>,
<0x00 0x02778000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 252 6>, <&k3_clks 252 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan8: can@2781000 {
compatible = "bosch,m_can";
reg = <0x00 0x02781000 0x00 0x200>,
<0x00 0x02788000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 253 6>, <&k3_clks 253 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan9: can@2791000 {
compatible = "bosch,m_can";
reg = <0x00 0x02791000 0x00 0x200>,
<0x00 0x02798000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 254 6>, <&k3_clks 254 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan10: can@27a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027a1000 0x00 0x200>,
<0x00 0x027a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 255 6>, <&k3_clks 255 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan11: can@27b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027b1000 0x00 0x200>,
<0x00 0x027b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 256 6>, <&k3_clks 256 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan12: can@27c1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027c1000 0x00 0x200>,
<0x00 0x027c8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 257 6>, <&k3_clks 257 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan13: can@27d1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027d1000 0x00 0x200>,
<0x00 0x027d8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 258 6>, <&k3_clks 258 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan14: can@2681000 {
compatible = "bosch,m_can";
reg = <0x00 0x02681000 0x00 0x200>,
<0x00 0x02688000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 259 6>, <&k3_clks 259 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan15: can@2691000 {
compatible = "bosch,m_can";
reg = <0x00 0x02691000 0x00 0x200>,
<0x00 0x02698000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 260 6>, <&k3_clks 260 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan16: can@26a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026a1000 0x00 0x200>,
<0x00 0x026a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 261 6>, <&k3_clks 261 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan17: can@26b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026b1000 0x00 0x200>,
<0x00 0x026b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 262 6>, <&k3_clks 262 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
main_spi0: spi@2100000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02100000 0x00 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 376 0>;
status = "disabled";
};
main_spi1: spi@2110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02110000 0x00 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 377 0>;
status = "disabled";
};
main_spi2: spi@2120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02120000 0x00 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 378 0>;
status = "disabled";
};
main_spi3: spi@2130000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02130000 0x00 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 379 0>;
status = "disabled";
};
main_spi4: spi@2140000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02140000 0x00 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 380 0>;
status = "disabled";
};
main_spi5: spi@2150000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02150000 0x00 0x400>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 381 0>;
status = "disabled";
};
main_spi6: spi@2160000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02160000 0x00 0x400>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 382 0>;
status = "disabled";
};
main_spi7: spi@2170000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02170000 0x00 0x400>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 383 0>;
status = "disabled";
};
ufs_wrapper: ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x00 0x4e80000 0x00 0x100>;
power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 387 3>;
assigned-clocks = <&k3_clks 387 3>;
assigned-clock-parents = <&k3_clks 387 6>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
ufs@4e84000 {
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
reg = <0x00 0x4e84000 0x00 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
freq-table-hz = <250000000 250000000>, <19200000 19200000>,
<19200000 19200000>;
clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>;
clock-names = "core_clk", "phy_clk", "ref_clk";
dma-coherent;
};
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <339>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 339 1>;
firmware-name = "j784s4-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5d00000 0x00010000>,
<0x5d10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <340>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 340 1>;
firmware-name = "j784s4-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
<0x5f00000 0x00 0x5f00000 0x20000>;
power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
main_r5fss1_core0: r5f@5e00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5e00000 0x00010000>,
<0x5e10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <341>;
ti,sci-proc-ids = <0x08 0xff>;
resets = <&k3_reset 341 1>;
firmware-name = "j784s4-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@5f00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5f00000 0x00010000>,
<0x5f10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <342>;
ti,sci-proc-ids = <0x09 0xff>;
resets = <&k3_reset 342 1>;
firmware-name = "j784s4-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss2: r5fss@5900000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5900000 0x00 0x5900000 0x20000>,
<0x5a00000 0x00 0x5a00000 0x20000>;
power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
main_r5fss2_core0: r5f@5900000 {
compatible = "ti,j721s2-r5f";
reg = <0x5900000 0x00010000>,
<0x5910000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <343>;
ti,sci-proc-ids = <0x0a 0xff>;
resets = <&k3_reset 343 1>;
firmware-name = "j784s4-main-r5f2_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss2_core1: r5f@5a00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5a00000 0x00010000>,
<0x5a10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <344>;
ti,sci-proc-ids = <0x0b 0xff>;
resets = <&k3_reset 344 1>;
firmware-name = "j784s4-main-r5f2_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c71_0: dsp@64800000 {
--> --------------------
--> maximum size reached
--> --------------------
