/* * We provide two versions of each macro to convert from physical * to virtual and vice versa. The "_r1" versions take one argument * register, but trashes r1 to do the conversion. The other * version takes two arguments: a src and destination register. * However, the source and destination registers can not be * the same register. * * We use add,l to avoid clobbering the C/B bits in the PSW.
*/
.macro shlw r, sa, t
zdep \r, 31-(\sa), 32-(\sa), \t
.endm
/* And the PA 2.0W shift left */
.macro shld r, sa, t
depd,z \r, 63-(\sa), 64-(\sa), \t
.endm
/* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
.macro shr r, sa, t
extru \r, 31-(\sa), 32-(\sa), \t
.endm
/* pa20w version of shift right */
.macro shrd r, sa, t
extrd,u \r, 63-(\sa), 64-(\sa), \t
.endm
/* Extract unsigned for 32- and 64-bit * The extru instruction leaves the most significant 32 bits of the
* target register in an undefined state on PA 2.0 systems. */
.macro extru_safe r, p, len, t #ifdef CONFIG_64BIT
extrd,u \r, 32+(\p), \len, \t #else
extru \r, \p, \len, \t #endif
.endm
/* The depi instruction leaves the most significant 32 bits of the
* target register in an undefined state on PA 2.0 systems. */
.macro depi_safe i, p, len, t #ifdef CONFIG_64BIT
depdi \i, 32+(\p), \len, \t #else
depi \i, \p, \len, \t #endif
.endm
/* The depw instruction leaves the most significant 32 bits of the
* target register in an undefined state on PA 2.0 systems. */
.macro dep_safe i, p, len, t #ifdef CONFIG_64BIT
depd \i, 32+(\p), \len, \t #else
depw \i, \p, \len, \t #endif
.endm
/* load 32-bit 'value' into 'reg' compensating for the ldil * sign-extension when running in wide mode. * WARNING!! neither 'value' nor 'reg' can be expressions
* containing '.'!!!! */
.macro load32 value, reg
ldil L%\value, \reg
ldo R%\value(\reg), \reg
.endm
#ifdef CONFIG_64BIT /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only * reads 5 bits. Use mfctl,w to read all six bits. Otherwise * we lose the 6th bit on a save/restore over interrupt.
*/
mfctl,w %cr11, %r1
STREG %r1, PT_SAR (\regs) #else
SAVE_CR (%cr11, PT_SAR (\regs)) #endif
SAVE_CR (%cr19, PT_IIR (\regs))
/* * Code immediately following this macro (in intr_save) relies * on r8 containing ipsw.
*/
mfctl %cr22, %r8
STREG %r8, PT_PSW(\regs)
.endm
/* First step to create a "relied upon translation" * See PA 2.0 Arch. page F-4 and F-5. * * The ssm was originally necessary due to a "PCxT bug". * But someone decided it needed to be added to the architecture * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. * It's been carried forward into PA 2.0 Arch as well. :^( * * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). * rsm/ssm prevents the ifetch unit from speculatively fetching * instructions past this line in the code stream. * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
*/
.macro pcxt_ssm_bug
rsm PSW_SM_I,%r0
nop /* 1 */
nop /* 2 */
nop /* 3 */
nop /* 4 */
nop /* 5 */
nop /* 6 */
nop /* 7 */
.endm
/* Switch to virtual mapping, trashing only %r1 */
.macro virt_map /* pcxt_ssm_bug */
rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
mtsp %r0, %sr4
mtsp %r0, %sr5
mtsp %r0, %sr6
tovirt_r1 %r29
load32 KERNEL_PSW, %r1
rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
mtctl %r0, %cr17 /* Clear IIASQ tail */
mtctl %r0, %cr17 /* Clear IIASQ head */
mtctl %r1, %ipsw
load32 4f, %r1
mtctl %r1, %cr18 /* Set IIAOQ tail */
ldo 4(%r1), %r1
mtctl %r1, %cr18 /* Set IIAOQ head */
rfir
nop
4:
.endm
/* * ASM_EXCEPTIONTABLE_ENTRY * * Creates an exception table entry. * Do not convert to a assembler macro. This won't work.
*/ #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \
.section __ex_table,"aw" ! \
.align 4 ! \
.word (fault_addr - .), (except_addr - .) ! \ or %r0,%r0,%r0 ! \
.previous
#endif/* __ASSEMBLER__ */ #endif
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