/* * This is necessary to get the definition of PGTABLE_RANGE which we * need for various slices related matters. Note that this isn't the * complete pgtable.h but only a portion of it.
*/ #include <asm/book3s/64/pgtable.h> #include <asm/book3s/64/slice.h> #include <asm/task_size_64.h> #include <asm/cpu_has_feature.h>
/* Values for PP (assumes Ks=0, Kp=1) */ #define PP_RWXX 0 /* Supervisor read/write, User none */ #define PP_RWRX 1 /* Supervisor read/write, User read */ #define PP_RWRW 2 /* Supervisor read/write, User read/write */ #define PP_RXRX 3 /* Supervisor read, User read */ #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
/* Fields for tlbiel instruction in architecture 2.06 */ #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ #define TLBIEL_INVAL_SET_SHIFT 12
struct mmu_hash_ops { void (*hpte_invalidate)(unsignedlong slot, unsignedlong vpn, int bpsize, int apsize, int ssize, int local); long (*hpte_updatepp)(unsignedlong slot, unsignedlong newpp, unsignedlong vpn, int bpsize, int apsize, int ssize, unsignedlong flags); void (*hpte_updateboltedpp)(unsignedlong newpp, unsignedlong ea, int psize, int ssize); long (*hpte_insert)(unsignedlong hpte_group, unsignedlong vpn, unsignedlong prpn, unsignedlong rflags, unsignedlong vflags, int psize, int apsize, int ssize); long (*hpte_remove)(unsignedlong hpte_group); int (*hpte_removebolted)(unsignedlong ea, int psize, int ssize); void (*flush_hash_range)(unsignedlong number, int local); void (*hugepage_invalidate)(unsignedlong vsid, unsignedlong addr, unsignedchar *hpte_slot_array, int psize, int ssize, int local); int (*resize_hpt)(unsignedlong shift); /* * Special for kexec. * To be called in real mode with interrupts disabled. No locks are * taken as such, concurrent access on pre POWER5 hardware could result * in a deadlock. * The linear mapping is destroyed as well.
*/ void (*hpte_clear_all)(void);
}; externstruct mmu_hash_ops mmu_hash_ops;
/* * Segment sizes. * These are the values used by hardware in the B field of * SLB entries and the first dword of MMU hashtable entries. * The B field is 2 bits; the values 2 and 3 are unused and reserved.
*/ #define MMU_SEGSIZE_256M 0 #define MMU_SEGSIZE_1T 1
/* * encode page number shift. * in order to fit the 78 bit va in a 64 bit variable we shift the va by * 12 bits. This enable us to address upto 76 bit va. * For hpt hash from a va we can ignore the page size bits of va and for * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure * we work in all cases including 4k page size.
*/ #define VPN_SHIFT 12
/* * This array is indexed by the LP field of the HPTE second dword. * Since this field may contain some RPN bits, some entries are * replicated so that we get the same value irrespective of RPN. * The top 4 bits are the page size index (MMU_PAGE_*) for the * actual page size, the bottom 4 bits are the base page size.
*/ extern u8 hpte_page_sizes[1 << LP_BITS];
/* Look at the 8 bit LP value */
lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
i = hpte_page_sizes[lp]; if (!i) return 0; if (!is_base_size)
i >>= 4; return 1ul << mmu_psize_defs[i & 0xf].shift;
}
/* * The current system page and segment sizes
*/ externint mmu_kernel_ssize; externint mmu_highuser_ssize; extern u16 mmu_slb_size; externunsignedlong tce_alloc_start, tce_alloc_end;
/* * If the processor supports 64k normal pages but not 64k cache * inhibited pages, we have to be prepared to switch processes * to use 4k pages when they create cache-inhibited mappings. * If this is the case, mmu_ci_restrictions will be set to 1.
*/ externint mmu_ci_restrictions;
/* * This computes the AVPN and B fields of the first dword of a HPTE, * for use when we want to match an existing PTE. The bottom 7 bits * of the returned value are zero.
*/ staticinlineunsignedlong hpte_encode_avpn(unsignedlong vpn, int psize, int ssize)
{ unsignedlong v; /* * The AVA field omits the low-order 23 bits of the 78 bits VA. * These bits are not needed in the PTE, because the * low-order b of these bits are part of the byte offset * into the virtual page and, if b < 23, the high-order * 23-b of these bits are always used in selecting the * PTEGs to be searched
*/
v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
v <<= HPTE_V_AVPN_SHIFT;
v |= ((unsignedlong) ssize) << HPTE_V_SSIZE_SHIFT; return v;
}
/* * ISA v3.0 defines a new HPTE format, which differs from the old * format in having smaller AVPN and ARPN fields, and the B field * in the second dword instead of the first.
*/ staticinlineunsignedlong hpte_old_to_new_v(unsignedlong v)
{ /* trim AVPN, drop B */ return v & HPTE_V_COMMON_BITS;
}
staticinlineunsignedlong hpte_old_to_new_r(unsignedlong v, unsignedlong r)
{ /* move B field from 1st to 2nd dword, trim ARPN */ return (r & ~HPTE_R_3_0_SSIZE_MASK) |
(((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
}
staticinlineunsignedlong hpte_new_to_old_v(unsignedlong v, unsignedlong r)
{ /* insert B field */ return (v & HPTE_V_COMMON_BITS) |
((r & HPTE_R_3_0_SSIZE_MASK) <<
(HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));
}
staticinlineunsignedlong hpte_new_to_old_r(unsignedlong r)
{ /* clear out B field */ return r & ~HPTE_R_3_0_SSIZE_MASK;
}
/* * This function sets the AVPN and L fields of the HPTE appropriately * using the base page size and actual page size.
*/ staticinlineunsignedlong hpte_encode_v(unsignedlong vpn, int base_psize, int actual_psize, int ssize)
{ unsignedlong v;
v = hpte_encode_avpn(vpn, base_psize, ssize); if (actual_psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE; return v;
}
/* * This function sets the ARPN, and LP fields of the HPTE appropriately * for the page size. We assume the pa is already "clean" that is properly * aligned for the requested page size
*/ staticinlineunsignedlong hpte_encode_r(unsignedlong pa, int base_psize, int actual_psize)
{ /* A 4K page needs no special encoding */ if (actual_psize == MMU_PAGE_4K) return pa & HPTE_R_RPN; else { unsignedint penc = mmu_psize_defs[base_psize].penc[actual_psize]; unsignedint shift = mmu_psize_defs[actual_psize].shift; return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
}
}
/* * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
*/ staticinlineunsignedlong hpt_vpn(unsignedlong ea, unsignedlong vsid, int ssize)
{ unsignedlong mask; int s_shift = segment_shift(ssize);
/* * VSID allocation (256MB segment) * * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated * from mmu context id and effective segment id of the address. * * For user processes max context id is limited to MAX_USER_CONTEXT. * more details in get_user_context * * For kernel space get_kernel_context * * The proto-VSIDs are then scrambled into real VSIDs with the * multiplicative hash: * * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS * * VSID_MULTIPLIER is prime, so in particular it is * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. * Because the modulus is 2^n-1 we can compute it efficiently without * a divide or extra multiply (see below). The scramble function gives * robust scattering in the hash table (at least based on some initial * results). * * We use VSID 0 to indicate an invalid VSID. The means we can't use context id * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which * will produce a VSID of 0. * * We also need to avoid the last segment of the last context, because that * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 * because of the modulo operation in vsid scramble.
*/
/* * Max Va bits we support as of now is 68 bits. We want 19 bit * context ID. * Restrictions: * GPU has restrictions of not able to access beyond 128TB * (47 bit effective address). We also cannot do more than 20bit PID. * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS * to 16 bits (ie, we can only have 2^16 pids at the same time).
*/ #define VA_BITS 68 #define CONTEXT_BITS 19 #define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS)) #define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS))
/* * Now certain config support MAX_PHYSMEM more than 512TB. Hence we will need * to use more than one context for linear mapping the kernel. * For vmalloc and memmap, we use just one context with 512TB. With 64 byte * struct page size, we need ony 32 TB in memmap for 2PB (51 bits (MAX_PHYSMEM_BITS)).
*/ #if (H_MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT) #define MAX_KERNEL_CTX_CNT (1UL << (H_MAX_PHYSMEM_BITS - MAX_EA_BITS_PER_CONTEXT)) #else #define MAX_KERNEL_CTX_CNT 1 #endif
/* * 256MB segment * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each * context maps 2^49 bytes (512TB). * * We also need to avoid the last segment of the last context, because that * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 * because of the modulo operation in vsid scramble. *
*/ #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2)
// The + 2 accounts for INVALID_REGION and 1 more to avoid overlap with kernel #define MIN_USER_CONTEXT (MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \
MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT + 2)
/* * For platforms that support on 65bit VA we limit the context bits
*/ #define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2)
/* * This should be computed such that protovosid * vsid_mulitplier * doesn't overflow 64 bits. The vsid_mutliplier should also be * co-prime to vsid_modulus. We also need to make sure that number * of bits in multiplied result (dividend) is less than twice the number of * protovsid bits for our modulus optmization to work. * * The below table shows the current values used. * |-------+------------+----------------------+------------+-------------------| * | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS | * |-------+------------+----------------------+------------+-------------------| * | 1T | 24 | 25 | 49 | 50 | * |-------+------------+----------------------+------------+-------------------| * | 256MB | 24 | 37 | 61 | 74 | * |-------+------------+----------------------+------------+-------------------| * * |-------+------------+----------------------+------------+--------------------| * | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS | * |-------+------------+----------------------+------------+--------------------| * | 1T | 24 | 28 | 52 | 56 | * |-------+------------+----------------------+------------+--------------------| * | 256MB | 24 | 40 | 64 | 80 | * |-------+------------+----------------------+------------+--------------------| *
*/ #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ #define VSID_BITS_256M (VA_BITS - SID_SHIFT) #define VSID_BITS_65_256M (65 - SID_SHIFT) /* * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS
*/ #define VSID_MULINV_256M ASM_CONST(665548017062)
/* 4 bits per slice and we have one slice per 1TB */ #define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) #define LOW_SLICE_ARRAY_SZ (BITS_PER_LONG / BITS_PER_BYTE) #define TASK_SLICE_ARRAY_SZ(x) ((x)->hash_context->slb_addr_limit >> 41) #ifndef __ASSEMBLY__
#ifdef CONFIG_PPC_SUBPAGE_PROT /* * For the sub-page protection option, we extend the PGD with one of * these. Basically we have a 3-level tree, with the top level being * the protptrs array. To optimize speed and memory consumption when * only addresses < 4GB are being protected, pointers to the first * four pages of sub-page protection words are stored in the low_prot * array. * Each page of sub-page protection words protects 1GB (4 bytes * protects 64k). For the 3-level tree, each page of pointers then * protects 8TB.
*/ struct subpage_prot_table { unsignedlong maxaddr; /* only addresses < this are protected */ unsignedint **protptrs[(TASK_SIZE_USER64 >> 43)]; unsignedint *low_prot[4];
};
/* * One bit per slice. We have lower slices which cover 256MB segments * upto 4G range. That gets us 16 low slices. For the rest we track slices * in 1TB size.
*/ struct slice_mask {
u64 low_slices;
DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
};
struct hash_mm_context {
u16 user_psize; /* page size index */
#if 0 /* * The code below is equivalent to this function for arguments * < 2^VSID_BITS, which is all this should ever be called * with. However gcc is not clever enough to compute the * modulus (2^n-1) without a second multiply.
*/ #define vsid_scramble(protovsid, size) \
((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
#else/* 1 */ staticinlineunsignedlong vsid_scramble(unsignedlong protovsid, unsignedlong vsid_multiplier, int vsid_bits)
{ unsignedlong vsid; unsignedlong vsid_modulus = ((1UL << vsid_bits) - 1); /* * We have same multipler for both 256 and 1T segements now
*/
vsid = protovsid * vsid_multiplier;
vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus); return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus;
}
#endif/* 1 */
/* Returns the segment size indicator for a user address */ staticinlineint user_segment_size(unsignedlong addr)
{ /* Use 1T segments if possible for addresses >= 1T */ if (addr >= (1UL << SID_SHIFT_1T)) return mmu_highuser_ssize; return MMU_SEGSIZE_256M;
}
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