/* SPDX-License-Identifier: GPL-2.0 */ /* These get patched into the trap table at boot time * once we know we have a cheetah processor. stxa %g1, [%g0] ASI_DCU_CONTROL_REGsethi %hi (cheetah_fast_ecc), %g2lo (cheetah_fast_ecc), %g0size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vectorstxa %g1, [%g0] ASI_DCU_CONTROL_REGsethi %hi (cheetah_fast_ecc), %g2lo (cheetah_fast_ecc), %g0size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1stxa %g1, [%g0] ASI_DCU_CONTROL_REGsethi %hi (cheetah_cee), %g2lo (cheetah_cee), %g0size cheetah_cee_trap_vector,.-cheetah_cee_trap_vectorstxa %g1, [%g0] ASI_DCU_CONTROL_REGsethi %hi (cheetah_cee), %g2lo (cheetah_cee), %g0size cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1stxa %g1, [%g0] ASI_DCU_CONTROL_REG;sethi %hi (cheetah_deferred_trap), %g2lo (cheetah_deferred_trap), %g0size cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vectorstxa %g1, [%g0] ASI_DCU_CONTROL_REG;sethi %hi (cheetah_deferred_trap), %g2lo (cheetah_deferred_trap), %g0size cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1/* Cheetah+ specific traps. These are for the new I/D cache parity * error traps. The first argument to cheetah_plus_parity_handler * is encoded as follows: * * Bit0: 0=dcache,1=icache * Bit1: 0=recoverable,1=unrecoverable sethi %hi (do_cheetah_plus_data_parity), %g7lo (do_cheetah_plus_data_parity), %g0size cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vectorsize do_cheetah_plus_data_parity,.-do_cheetah_plus_data_paritysethi %hi (do_dcpe_tl1), %g3lo (do_dcpe_tl1), %g0size cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1sethi %hi (do_cheetah_plus_insn_parity), %g7lo (do_cheetah_plus_insn_parity), %g0size cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vectorsize do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_paritysethi %hi (do_icpe_tl1), %g3lo (do_icpe_tl1), %g0size cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1/* If we take one of these traps when tl >= 1, then we * jump to interrupt globals. If some trap level above us * was also using interrupt globals, we cannot recover. * We may use all interrupt global registers except %g6. ! Save original trap level ! Setup TSTATE checking loop sethi %hi (TSTATE_IG), %g3 ! TSTATE mask bit ! Set trap level to check ! Read TSTATE for this level ! Interrupt globals in use? ! Yep, irrecoverable ! Restore original trap level ! Next trap level ! Hit them all yet? ! Not yet ! Restore original trap level /* Ok we may use interrupt globals safely. */ sethi %hi (dcache_parity_tl1_occurred), %g2lo (dcache_parity_tl1_occurred)], %g1lo (dcache_parity_tl1_occurred)]/* Reset D-cache parity */ sethi %hi (1 << 16), %g1 ! D-cache size ! D-cache line size sub %g1, %g2, %g1 ! Move down 1 cacheline srl %g1, 14, %g3 ! Compute UTAG stxa %g3, [%g1] ASI_DCACHE_UTAGsub %g2, 8, %g3 ! 64-bit data word within line stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA! Next 64-bit data word ! Next cacheline sethi %hi (1f), %g7lo (1b), %g7size do_dcpe_tl1,.-do_dcpe_tl1! Save original trap level ! Setup TSTATE checking loop sethi %hi (TSTATE_IG), %g3 ! TSTATE mask bit ! Set trap level to check ! Read TSTATE for this level ! Interrupt globals in use? ! Yep, irrecoverable ! Restore original trap level ! Next trap level ! Hit them all yet? ! Not yet ! Restore original trap level /* Ok we may use interrupt globals safely. */ sethi %hi (icache_parity_tl1_occurred), %g2lo (icache_parity_tl1_occurred)], %g1lo (icache_parity_tl1_occurred)]/* Flush I-cache */ sethi %hi (1 << 15), %g1 ! I-cache size ! I-cache line size sub %g1, %g2, %g1stxa %g0, [%g3] ASI_IC_TAGsethi %hi (1f), %g7lo (1b), %g7size do_icpe_tl1,.-do_icpe_tl1/* Flush D-cache, re-enable D/I caches in DCU and finally * retry the trapping instruction. sethi %hi (1 << 16), %g1 ! D-cache size ! D-cache line size sub %g1, %g2, %g1stxa %g0, [%g1] ASI_DCACHE_TAGstxa %g1, [%g0] ASI_DCU_CONTROL_REGsize dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common/* Capture I/D/E-cache state into per-cpu error scoreboard. * * %g1: (TL>=0) ? 1 : 0 * %g2: scratch * %g3: scratch * %g4: AFSR * %g5: AFAR * %g6: unused, will have current thread ptr after etrap * %g7: scratch /* Put "TL1" software bit into AFSR. */ sllx %g1, 63, %g2/* Get log entry pointer for this cpu at this trap level. */ srlx %g2, 17, %g2srlx %g2, 17, %g2sllx %g2, 9, %g2sethi %hi (cheetah_error_log), %g3ldx [%g3 + %lo (cheetah_error_log)], %g3sllx %g1, 8, %g1/* %g1 holds pointer to the top of the logging scoreboard */ ldx [%g1 + 0x0], %g7stx %g4, [%g1 + 0x0]stx %g5, [%g1 + 0x8]/* %g1 now points to D-cache logging area */ set 0x3ff8, %g2 /* DC_addr mask */ /* DC_addr bits of AFAR */ srlx %g5, 12, %g3/* PHYS tag + valid */ /* TAG match? */ /* Yep, what we want, capture state. */ stx %g2, [%g1 + 0x20]stx %g7, [%g1 + 0x28]/* A membar Sync is required before and after utag access. */ stx %g7, [%g1 + 0x30]stx %g7, [%g1 + 0x38]clr %g3stx %g7, [%g1]sethi %hi (1 << 14), %g7srlx %g2, 14, %g7/* %g1 now points to I-cache logging area */ set 0x1fe0, %g2 /* IC_addr mask */ /* IC_addr bits of AFAR */ sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */ srlx %g5, (13 - 8), %g3 /* Make PTAG */ /* Mask off undefined bits */ /* Yep, what we want, capture state. */ stx %g2, [%g1 + 0x40]stx %g7, [%g1 + 0x48]stx %g7, [%g1 + 0x50]stx %g7, [%g1 + 0x60]stx %g7, [%g1 + 0x68]sub %g2, (3 << 3), %g2stx %g7, [%g1 + 0x58]clr %g3srlx %g2, 2, %g2stx %g7, [%g1]sethi %hi (1 << 14), %g7srlx %g2, 14, %g7/* %g1 now points to E-cache logging area */ stx %g2, [%g1 + 0x20]stx %g7, [%g1 + 0x28]clr %g3stx %g7, [%g1 + %g3]size __cheetah_log_error,.-__cheetah_log_error/* Cheetah FECC trap handling, we get here from tl{0,1}_fecc * in the trap table. That code has done a memory barrier * and has disabled both the I-cache and D-cache in the DCU * control register. The I-cache is disabled so that we may * capture the corrupted cache line, and the D-cache is disabled * because corrupt data may have been placed there and we don't * want to reference it. * * %g1 is one if this trap occurred at %tl >= 1. * * Next, we turn off error reporting so that we don't recurse. stxa %g2, [%g0] ASI_ESTATE_ERROR_EN/* Fetch and clear AFSR/AFAR */ stxa %g4, [%g0] ASI_AFSRsize cheetah_fast_ecc,.-cheetah_fast_eccsize c_fast_ecc,.-c_fast_ecc/* Our caller has disabled I-cache and performed membar Sync. */ stxa %g2, [%g0] ASI_ESTATE_ERROR_EN/* Fetch and clear AFSR/AFAR */ stxa %g4, [%g0] ASI_AFSRsize cheetah_cee,.-cheetah_ceesize c_cee,.-c_cee/* Our caller has disabled I-cache+D-cache and performed membar Sync. */ stxa %g2, [%g0] ASI_ESTATE_ERROR_EN/* Fetch and clear AFSR/AFAR */ stxa %g4, [%g0] ASI_AFSRsize cheetah_deferred_trap,.-cheetah_deferred_trapsize c_deferred,.-c_deferred
Messung V0.5 C=90 H=100 G=95
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