/* SPDX-License-Identifier: GPL-2.0 */ /* * etrap.S: Preparing for entry into the kernel on Sparc V9. * * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu) * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
*/
/* Go to trap time globals so we can save them. */
661: wrpr %g0, ETRAP_PSTATE1, %pstate
.section .sun4v_1insn_patch, "ax"
.word 661b
SET_GL(0)
.previous
stx %g1, [%sp + PTREGS_OFF + PT_V9_G1] stx %g2, [%sp + PTREGS_OFF + PT_V9_G2] sllx %l7, 24, %l7 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
rdpr %cwp, %l0 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4] stx %g5, [%sp + PTREGS_OFF + PT_V9_G5] stx %g6, [%sp + PTREGS_OFF + PT_V9_G6] stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
or %l7, %l0, %l7
661: sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0 /* If userspace is using ADI, it could potentially pass * a pointer with version tag embedded in it. To maintain * the ADI security, we must enable PSTATE.mcde. Userspace * would have already set TTE.mcd in an earlier call to * kernel and set the version tag for the address being * dereferenced. Setting PSTATE.mcde would ensure any * access to userspace data through a system call honors * ADI and does not allow a rogue app to bypass ADI by * using system calls. Setting PSTATE.mcde only affects * accesses to virtual addresses that have TTE.mcd set. * Set PMCDPER to ensure any exceptions caused by ADI * version tag mismatch are exposed before system call * returns to userspace. Setting PMCDPER affects only * writes to virtual addresses that have TTE.mcd set and * have a version tag set as well.
*/
.section .sun_m7_1insn_patch, "ax"
.word 661b sethi %hi(TSTATE_TSO | TSTATE_PEF | TSTATE_MCDE), %l0
.previous
661: nop
.section .sun_m7_1insn_patch, "ax"
.word 661b
.word 0xaf902001 /* wrpr %g0, 1, %pmcdper */
.previous
or %l7, %l0, %l7
wrpr %l2, %tnpc
wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate stx %i0, [%sp + PTREGS_OFF + PT_V9_I0] stx %i1, [%sp + PTREGS_OFF + PT_V9_I1] stx %i2, [%sp + PTREGS_OFF + PT_V9_I2] stx %i3, [%sp + PTREGS_OFF + PT_V9_I3] stx %i4, [%sp + PTREGS_OFF + PT_V9_I4] stx %i5, [%sp + PTREGS_OFF + PT_V9_I5] stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
mov %l6, %g6 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1) ldx [%g6 + TI_TASK], %g4
done
/* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */
sth %l5, [%l6 + TI_SYS_NOERROR]
ba,pt %xcc, 2b
stb %g0, [%l4 + %l3]
nop
etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself. * We place this right after pt_regs on the trap stack. * The layout is: * 0x00 TL1's TSTATE * 0x08 TL1's TPC * 0x10 TL1's TNPC * 0x18 TL1's TT * ... * 0x58 TL4's TT * 0x60 TL
*/
TRAP_LOAD_THREAD_REG(%g6, %g1) sub %sp, ((4 * 8) * 4) + 8, %g2
rdpr %tl, %g1
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