staticvoid pci_fixup_i450nx(struct pci_dev *d)
{ /* * i450NX -- Find and scan all secondary buses on all PXB's.
*/ int pxb, reg;
u8 busno, suba, subb;
dev_warn(&d->dev, "Searching for i450NX host bridges\n");
reg = 0xd0; for(pxb = 0; pxb < 2; pxb++) {
pci_read_config_byte(d, reg++, &busno);
pci_read_config_byte(d, reg++, &suba);
pci_read_config_byte(d, reg++, &subb);
dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
suba, subb); if (busno)
pcibios_scan_root(busno); /* Bus A */ if (suba < subb)
pcibios_scan_root(suba+1); /* Bus B */
}
pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
staticvoid pci_fixup_i450gx(struct pci_dev *d)
{ /* * i450GX and i450KX -- Find and scan all secondary buses. * (called separately for each PCI bridge found)
*/
u8 busno;
pci_read_config_byte(d, 0x4a, &busno);
dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
pcibios_scan_root(busno);
pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
staticvoid pci_fixup_umc_ide(struct pci_dev *d)
{ /* * UM8886BF IDE controller sets region type bits incorrectly, * therefore they look like memory despite of them being I/O.
*/ int i;
dev_warn(&d->dev, "Fixing base address flags\n"); for(i = 0; i < 4; i++)
d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
staticvoid pci_fixup_latency(struct pci_dev *d)
{ /* * SiS 5597 and 5598 chipsets require latency timer set to * at most 32 to avoid lockups.
*/
dev_dbg(&d->dev, "Setting max latency to 32\n");
pcibios_max_latency = 32;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
/* * Addresses issues with problems in the memory write queue timer in * certain VIA Northbridges. This bugfix is per VIA's specifications, * except for the KL133/KM133: clearing bit 5 on those Northbridges seems * to trigger a bug in its integrated ProSavage video card, which * causes screen corruption. We only clear bits 6 and 7 for that chipset, * until VIA can provide us with definitive information on why screen * corruption occurs, and what exactly those bits do. * * VIA 8363,8622,8361 Northbridges: * - bits 5, 6, 7 at offset 0x55 need to be turned off * VIA 8367 (KT266x) Northbridges: * - bits 5, 6, 7 at offset 0x95 need to be turned off * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: * - bits 6, 7 at offset 0x55 need to be turned off
*/
staticvoid pci_fixup_via_northbridge_bug(struct pci_dev *d)
{
u8 v; int where = 0x55; int mask = 0x1f; /* clear bits 5, 6, 7 by default */
if (d->device == PCI_DEVICE_ID_VIA_8367_0) { /* fix pci bus latency issues resulted by NB bios error it appears on bug free^Wreduced kt266x's bios forces
NB latency to zero */
pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
where = 0x95; /* the memory write queue timer register is
different for the KT266x's: 0x95 not 0x55 */
} elseif (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
(d->revision == VIA_8363_KL133_REVISION_ID ||
d->revision == VIA_8363_KM133_REVISION_ID)) {
mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
causes screen corruption on the KL133/KM133 */
}
/* * For some reasons Intel decided that certain parts of their * 815, 845 and some other chipsets must look like PCI-to-PCI bridges * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according * to Intel terminology. These devices do forward all addresses from * system to PCI bus no matter what are their window settings, so they are * "transparent" (or subtractive decoding) from programmers point of view.
*/ staticvoid pci_fixup_transparent_bridge(struct pci_dev *dev)
{ if ((dev->device & 0xff00) == 0x2400)
dev->transparent = 1;
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
/* * Fixup for C1 Halt Disconnect problem on nForce2 systems. * * From information provided by "Allen Martin" <AMartin@nvidia.com>: * * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns. * This allows the state-machine and timer to return to a proper state within * 80 ns of the CONNECT and probe appearing together. Since the CPU will not * issue another HALT within 80 ns of the initial HALT, the failure condition * is avoided.
*/ staticvoid pci_fixup_nforce2(struct pci_dev *dev)
{
u32 val;
/* * Chip Old value New value * C17 0x1F0FFF01 0x1F01FF01 * C18D 0x9F0FFF01 0x9F01FF01 * * Northbridge chip version may be determined by * reading the PCI revision ID (0xC1 or greater is C18D).
*/
pci_read_config_dword(dev, 0x6c, &val);
/* * Apply fixup if needed, but don't touch disconnect state
*/ if ((val & 0x00FF0000) != 0x00010000) {
dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
/* * Replace the original pci bus ops for write with a new one that will filter * the request to insure ASPM cannot be enabled.
*/ staticint quirk_pcie_aspm_write(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 value)
{
u8 offset;
/* * Prevents PCI Express ASPM (Active State Power Management) being enabled. * * Save the register offset, where the ASPM control bits are located, * for each PCI Express device that is in the device list of * the root port in an array for fast indexing. Replace the bus ops * with the modified one.
*/ staticvoid pcie_rootport_aspm_quirk(struct pci_dev *pdev)
{ int i; struct pci_bus *pbus; struct pci_dev *dev;
if ((pbus = pdev->subordinate) == NULL) return;
/* * Check if the DID of pdev matches one of the six root ports. This * check is needed in the case this function is called directly by the * hot-plug driver.
*/ if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
(pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1)) return;
if (list_empty(&pbus->devices)) { /* * If no device is attached to the root port at power-up or * after hot-remove, the pbus->devices is empty and this code * will set the offsets to zero and the bus ops to parent's bus * ops, which is unmodified.
*/ for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
quirk_aspm_offset[i] = 0;
pci_bus_set_ops(pbus, pbus->parent->ops);
} else { /* * If devices are attached to the root port at power-up or * after hot-add, the code loops through the device list of * each root port to save the register offsets and replace the * bus ops.
*/
list_for_each_entry(dev, &pbus->devices, bus_list) /* There are 0 to 8 devices attached to this bus */
quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
dev->pcie_cap + PCI_EXP_LNKCTL;
pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
}
/* * Fixup to mark boot BIOS video selected by BIOS before it changes * * From information provided by "Jon Smirl" <jonsmirl@gmail.com> * * The standard boot ROM sequence for an x86 machine uses the BIOS * to select an initial video card for boot display. This boot video * card will have its BIOS copied to 0xC0000 in system RAM. * IORESOURCE_ROM_SHADOW is used to associate the boot video * card with this copy. On laptops this copy has to be used since * the main ROM may be compressed or combined with another image. * See pci_map_rom() for use of this flag. Before marking the device * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set * by either arch code or vga-arbitration; if so only apply the fixup to this * already-determined primary video card.
*/
/* Is VGA routed to us? */
bus = pdev->bus; while (bus) {
bridge = bus->self;
/* * From information provided by * "David Miller" <davem@davemloft.net> * The bridge control register is valid for PCI header * type BRIDGE, or CARDBUS. Host to PCI controllers use * PCI header type NORMAL.
*/ if (bridge && (pci_is_bridge(bridge))) {
pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
&config); if (!(config & PCI_BRIDGE_CTL_VGA)) return;
}
bus = bus->parent;
} if (!vga_default_device() || pdev == vga_default_device()) {
pci_read_config_word(pdev, PCI_COMMAND, &config); if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
res = &pdev->resource[PCI_ROM_RESOURCE];
pci_disable_rom(pdev); if (res->parent)
release_resource(res);
/* * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound * card if a PCI-soundcard is added. * * The BIOS only gives options "DISABLED" and "AUTO". This code sets * the corresponding register-value to enable the soundcard. * * The soundcard is only enabled, if the mainboard is identified * via DMI-tables and the soundcard is detected to be off.
*/ staticvoid pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
{ unsignedchar val; if (!dmi_check_system(msi_k8t_dmi_table)) return; /* only applies to MSI K8T Neo2-FIR */
pci_read_config_byte(dev, 0x50, &val); if (val & 0x40) {
pci_write_config_byte(dev, 0x50, val & (~0x40));
/* * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. * * We pretend to bring them out of full D3 state, and restore the proper * IRQ, PCI cache line size, and BARs, otherwise the device won't function * properly. In some cases, the device will generate an interrupt on * the wrong IRQ line, causing any devices sharing the line it's * *supposed* to use to be disabled by the kernel's IRQ debug code.
*/ static u16 toshiba_line_size;
staticvoid pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
{ if (!dmi_check_system(toshiba_ohci1394_dmi_table)) return; /* only applies to certain Toshibas (so far) */
staticvoid pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
{ if (!dmi_check_system(toshiba_ohci1394_dmi_table)) return; /* only applies to certain Toshibas (so far) */
/* * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device * configuration space.
*/ staticvoid pci_early_fixup_cyrix_5530(struct pci_dev *dev)
{
u8 r; /* clear 'F4 Video Configuration Trap' bit */
pci_read_config_byte(dev, 0x42, &r);
r &= 0xfd;
pci_write_config_byte(dev, 0x42, r);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
pci_early_fixup_cyrix_5530);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
pci_early_fixup_cyrix_5530);
/* * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: * prevent update of the BAR0, which doesn't look like a normal BAR.
*/ staticvoid pci_siemens_interrupt_controller(struct pci_dev *dev)
{
dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
pci_siemens_interrupt_controller);
/* * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from * confusing the PCI engine:
*/ staticvoid sb600_disable_hpet_bar(struct pci_dev *dev)
{
u8 val;
/* * The SB600 and SB700 both share the same device * ID, but the PM register 0x55 does something different * for the SB700, so make sure we are dealing with the * SB600 before touching the bit:
*/
pci_read_config_byte(dev, 0x08, &val);
if (val < 0x2F) {
outb(0x55, 0xCD6);
val = inb(0xCD7);
/* Set bit 7 in PM register 0x55 */
outb(0x55, 0xCD6);
outb(val | 0x80, 0xCD7);
}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
r->flags |= IORESOURCE_PCI_FIXED;
dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk); #endif
/* * Twinhead H12Y needs us to block out a region otherwise we map devices * there and any access kills the box. * * See: https://bugzilla.kernel.org/show_bug.cgi?id=10231 * * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
*/ staticvoid twinhead_reserve_killing_zone(struct pci_dev *dev)
{ if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
pr_info("Reserving memory on Twinhead H12Y\n");
request_mem_region(0xFFB00000, 0x100000, "twinhead");
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
/* * Device [1022:7808] * 23. USB Wake on Connect/Disconnect with Low Speed Devices * https://support.amd.com/TechDocs/46837.pdf * Appendix A2 * https://support.amd.com/TechDocs/42413.pdf
*/ staticvoid pci_fixup_amd_ehci_pme(struct pci_dev *dev)
{
dev_info(&dev->dev, "PME# does not work under D3, disabling it\n");
dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold)
>> PCI_PM_CAP_PME_SHIFT);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);
/* * Device [1022:7914] * When in D0, PME# doesn't get asserted when plugging USB 2.0 device.
*/ staticvoid pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)
{
dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");
dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
/* * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff] * * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used * for soft poweroff and suspend-to-RAM. * * As far as we know, this is related to the address space, not to the Root * Port itself. Attaching the quirk to the Root Port is a convenience, but * it could probably also be a standalone DMI quirk. * * https://bugzilla.kernel.org/show_bug.cgi?id=103211
*/ staticvoid quirk_apple_mbp_poweroff(struct pci_dev *pdev)
{ struct device *dev = &pdev->dev; struct resource *res;
res = request_mem_region(0x7fa00000, 0x200000, "MacBook Pro poweroff workaround"); if (res)
dev_info(dev, "claimed %s %pR\n", res->name, res); else
dev_info(dev, "can't work around MacBook Pro poweroff issue\n");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
/* * VMD-enabled root ports will change the source ID for all messages * to the VMD device. Rather than doing device matching with the source * ID, the AER driver should traverse the child device tree, reading * AER registers to find the faulting device.
*/ staticvoid quirk_no_aersid(struct pci_dev *pdev)
{ /* VMD Domain */ if (is_vmd(pdev->bus) && pci_is_root_bus(pdev->bus))
pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
PCI_CLASS_BRIDGE_PCI, 8, quirk_no_aersid);
/* * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow * configuring host bridge windows using the _PRS and _SRS methods. * * But this is rarely implemented, so we manually enable a large 64bit BAR for * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors * here.
*/ staticvoid pci_amd_enable_64bit_bar(struct pci_dev *dev)
{ staticconstchar *name = "PCI Bus 0000:00"; struct resource *res, *conflict;
u32 base, limit, high; struct pci_dev *other; unsigned i;
if (!(pci_probe & PCI_BIG_ROOT_WINDOW)) return;
/* Check that we are the only device of that type */
other = pci_get_device(dev->vendor, dev->device, NULL); if (other != dev ||
(other = pci_get_device(dev->vendor, dev->device, other))) { /* This is a multi-socket system, don't touch it for now */
pci_dev_put(other); return;
}
for (i = 0; i < 8; i++) {
pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
/* Is this slot free? */ if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
AMD_141b_MMIO_BASE_WE_MASK))) break;
base >>= 8;
base |= high << 24;
/* Abort if a slot already configures a 64bit BAR. */ if (base > 0x10000) return;
} if (i == 8) return;
res = kzalloc(sizeof(*res), GFP_KERNEL); if (!res) return;
conflict = request_resource_conflict(&iomem_resource, res); if (conflict) {
kfree(res); if (conflict->name != name) return;
/* We are resuming from suspend; just reenable the window */
res = conflict;
} else {
dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
res);
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
pci_bus_add_resource(dev->bus, res);
}
/* * Some BIOS implementations support RAM above 4GB, but do not configure the * PCI host to respond to bus master accesses for these addresses. These * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA * works as expected for addresses below 4GB. * * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57) * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf
*/ staticvoid rs690_fix_64bit_dma(struct pci_dev *pdev)
{
u32 val = 0;
phys_addr_t top_of_dram = __pa(high_memory - 1) + 1;
if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) {
data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK; if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data))
pci_err(dev, "Failed to write data 0x%x\n", data);
} else {
pci_err(dev, "Failed to read data\n");
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0); #endif
/* * When returning from D3cold to D0, firmware on some Google Coral and Reef * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of * both the L1 PM Substates capability and the previous capability for the * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1". * * Save those values at enumeration-time and restore them at resume.
*/
if (!prev_cap || !prev_header || !l1ss_cap || !l1ss_header) return;
/* Fixup the header of L1SS Capability if missing */
pci_read_config_dword(dev, l1ss_cap, &header); if (header != l1ss_header) {
pci_write_config_dword(dev, l1ss_cap, l1ss_header);
pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n",
header, l1ss_header);
}
/* Fixup the link to L1SS Capability if missing */
pci_read_config_dword(dev, prev_cap, &header); if (header != prev_header) {
pci_write_config_dword(dev, prev_cap, prev_header);
pci_info(dev, "restore previous Capability header (was %#010x now %#010x)\n",
header, prev_header);
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
/* * Disable D3cold on Asus B1400 PCI-NVMe bridge * * On this platform with VMD off, the NVMe device cannot successfully power * back on from D3cold. This appears to be an untested transition by the * vendor: Windows leaves the NVMe and parent bridge in D0 during suspend. * * We disable D3cold on the parent bridge for simplicity, and the fact that * both parent bridge and NVMe device share the same power resource. * * This is only needed on BIOS versions before 308; the newer versions flip * StorageD3Enable from 1 to 0.
*/ staticconststruct dmi_system_id asus_nvme_broken_d3cold_table[] = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.304"),
},
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.305"),
},
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.306"),
},
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.307"),
},
},
{}
};
#ifdef CONFIG_SUSPEND /* * Root Ports on some AMD SoCs advertise PME_Support for D3hot and D3cold, but * if the SoC is put into a hardware sleep state by the amd-pmc driver, the * Root Ports don't generate wakeup interrupts for USB devices. * * When suspending, remove D3hot and D3cold from the PME_Support advertised * by the Root Port so we don't use those states if we're expecting wakeup * interrupts. Restore the advertised PME_Support when resuming.
*/ staticvoid amd_rp_pme_suspend(struct pci_dev *dev)
{ struct pci_dev *rp;
/* * If system suspend is not in progress, we're doing runtime suspend, so * amd-pmc will not be involved so PMEs during D3 work as advertised. * * The PMEs *do* work if amd-pmc doesn't put the SoC in the hardware * sleep state, but we assume amd-pmc is always present.
*/ if (!pm_suspend_in_progress()) return;
rp = pcie_find_root_port(dev); if (!rp || !rp->pm_cap) return;
/* * Putting PCIe root ports on Ryzen SoCs with USB4 controllers into D3hot * may cause problems when the system attempts wake up from s2idle. * * On the TUXEDO Sirius 16 Gen 1 with a specific old BIOS this manifests as * a system hang.
*/ staticconststruct dmi_system_id quirk_tuxeo_rp_d3_dmi_table[] = {
{
.matches = {
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "TUXEDO"),
DMI_EXACT_MATCH(DMI_BOARD_NAME, "APX958"),
DMI_EXACT_MATCH(DMI_BIOS_VERSION, "V1.00A00_20240108"),
},
},
{}
};
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