dev_crit_ratelimited(axi->dev, "AXI-bus fault %d: %s at 0x%x%08x\n",
atomic_inc_return(&axi->count),
high & BT1_AXI_WERRH_TYPE ? "no slave" : "slave protocol error",
high, low);
/* * Print backtrace on each CPU. This might be pointless if the fault * has happened on the same CPU as the IRQ handler is executed or * the other core proceeded further execution despite the error. * But if it's not, by looking at the trace we would get straight to * the cause of the problem.
*/
trigger_all_cpu_backtrace();
staticint bt1_axi_request_rst(struct bt1_axi *axi)
{ int ret;
axi->arst = devm_reset_control_get_optional_exclusive(axi->dev, "arst"); if (IS_ERR(axi->arst)) return dev_err_probe(axi->dev, PTR_ERR(axi->arst), "Couldn't get reset control line\n");
ret = reset_control_deassert(axi->arst); if (ret)
dev_err(axi->dev, "Failed to deassert the reset line\n");
return ret;
}
staticint bt1_axi_request_clk(struct bt1_axi *axi)
{
axi->aclk = devm_clk_get_enabled(axi->dev, "aclk"); if (IS_ERR(axi->aclk)) return dev_err_probe(axi->dev, PTR_ERR(axi->aclk), "Couldn't get AXI Interconnect clock\n");
/* * Performing unaligned read from the memory will cause the CM2 bus * error while unaligned writing - the AXI bus write error handled * by this driver.
*/ if (sysfs_streq(data, "bus"))
readb(axi->qos_regs); elseif (sysfs_streq(data, "unaligned"))
writeb(0, axi->qos_regs); else return -EINVAL;
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