staticchar *omap3_l3_code_string(u8 code)
{ switch (code) { case OMAP_L3_CODE_NOERROR: return"No Error"; case OMAP_L3_CODE_UNSUP_CMD: return"Unsupported Command"; case OMAP_L3_CODE_ADDR_HOLE: return"Address Hole"; case OMAP_L3_CODE_PROTECT_VIOLATION: return"Protection Violation"; case OMAP_L3_CODE_IN_BAND_ERR: return"In-band Error"; case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT: return"Request Timeout Not Accepted"; case OMAP_L3_CODE_REQ_TOUT_NO_RESP: return"Request Timeout, no response"; default: return"UNKNOWN error";
}
}
staticchar *omap3_l3_initiator_string(u8 initid)
{ switch (initid) { case OMAP_L3_LCD: return"LCD"; case OMAP_L3_SAD2D: return"SAD2D"; case OMAP_L3_IA_MPU_SS_1: case OMAP_L3_IA_MPU_SS_2: case OMAP_L3_IA_MPU_SS_3: case OMAP_L3_IA_MPU_SS_4: case OMAP_L3_IA_MPU_SS_5: return"MPU"; case OMAP_L3_IA_IVA_SS_1: case OMAP_L3_IA_IVA_SS_2: case OMAP_L3_IA_IVA_SS_3: return"IVA_SS"; case OMAP_L3_IA_IVA_SS_DMA_1: case OMAP_L3_IA_IVA_SS_DMA_2: case OMAP_L3_IA_IVA_SS_DMA_3: case OMAP_L3_IA_IVA_SS_DMA_4: case OMAP_L3_IA_IVA_SS_DMA_5: case OMAP_L3_IA_IVA_SS_DMA_6: return"IVA_SS_DMA"; case OMAP_L3_IA_SGX: return"SGX"; case OMAP_L3_IA_CAM_1: case OMAP_L3_IA_CAM_2: case OMAP_L3_IA_CAM_3: return"CAM"; case OMAP_L3_IA_DAP: return"DAP"; case OMAP_L3_SDMA_WR_1: case OMAP_L3_SDMA_WR_2: return"SDMA_WR"; case OMAP_L3_SDMA_RD_1: case OMAP_L3_SDMA_RD_2: case OMAP_L3_SDMA_RD_3: case OMAP_L3_SDMA_RD_4: return"SDMA_RD"; case OMAP_L3_USBOTG: return"USB_OTG"; case OMAP_L3_USBHOST: return"USB_HOST"; default: return"UNKNOWN Initiator";
}
}
/* * omap3_l3_block_irq - handles a register block's irq * @l3: struct omap3_l3 * * @base: register block base address * @error: L3_ERROR_LOG register of our block * * Called in hard-irq context. Caller should take care of locking * * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error * Analysis Sequence, we are following that sequence here, please * refer to that Figure for more information on the subject.
*/ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
u64 error, int error_addr)
{
u8 code = omap3_l3_decode_error_code(error);
u8 initid = omap3_l3_decode_initid(error);
u8 multi = error & L3_ERROR_LOG_MULTI;
u32 address = omap3_l3_decode_addr(error_addr);
pr_err("%s seen by %s %s at address %x\n",
omap3_l3_code_string(code),
omap3_l3_initiator_string(initid),
multi ? "Multiple Errors" : "", address);
WARN_ON(1);
int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; if (!int_type)
status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); else
status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
/* identify the error source */
err_source = __ffs(status);
base = l3->rt + omap3_l3_bases[int_type][err_source];
error = omap3_l3_readll(base, L3_ERROR_LOG); if (error) {
error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
ret |= omap3_l3_block_irq(l3, error, error_addr);
}
/* * if we have a timeout error, there's nothing we can * do besides rebooting the board. So let's BUG on any * of such errors and handle the others. timeout error * is severe and not expected to occur.
*/
BUG_ON(!int_type && status & L3_STATUS_0_TIMEOUT_MASK);
/* Clear the status register */
clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
L3_AGENT_STATUS_CLEAR_TA;
omap3_l3_writell(base, L3_AGENT_STATUS, clear);
/* clear the error log register */
omap3_l3_writell(base, L3_ERROR_LOG, error);
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