/* System Bus Controller registers */ #define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */ #define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */ #define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */ #define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */ #define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */ #define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */ #define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
#define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */ #define UNIPHIER_SBC_NR_BANKS 8 /* number of banks (chip select) */ #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
dev_dbg(priv->dev, "range added: bank = %d, addr = %08x, end = %08x\n",
bank, priv->bank[bank].base, priv->bank[bank].end);
return 0;
}
staticint uniphier_system_bus_check_overlap( conststruct uniphier_system_bus_priv *priv)
{ int i, j;
for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) { if (priv->bank[i].end > priv->bank[j].base &&
priv->bank[i].base < priv->bank[j].end) {
dev_err(priv->dev, "region overlap between bank%d and bank%d\n",
i, j); return -EINVAL;
}
}
}
/* * If BOOT_SWAP was asserted on power-on-reset, the CS0 and CS1 are * swapped. In this case, bank0 and bank1 should be swapped as well.
*/ if (is_swapped)
swap(priv->bank[0], priv->bank[1]);
}
for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
base = priv->bank[i].base;
end = priv->bank[i].end;
if (base == end) { /* * If SBC_BASE0 or SBC_BASE1 is set to zero, the access * to anywhere in the system bus space is routed to * bank 0 (if boot swap if off) or bank 1 (if boot swap * if on). It means that CPUs cannot get access to * bank 2 or later. In other words, bank 0/1 cannot * be disabled even if its bank_enable bits is cleared. * This seems odd, but it is how this hardware goes. * As a workaround, dummy data (0xffffffff) should be * set when the bank 0/1 is unused. As for bank 2 and * later, they can be simply disable by clearing the * bank_enable bit.
*/ if (i < 2)
val = UNIPHIER_SBC_BASE_DUMMY; else
val = 0;
} else {
mask = base ^ (end - 1);
val = base & 0xfffe0000;
val |= (~mask >> 16) & 0xfffe;
val |= UNIPHIER_SBC_BASE_BE;
}
dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val);
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