// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2010,2015 Broadcom * Copyright (C) 2012 Stephen Warren /** * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) * * The clock tree on the 2835 has several levels. There's a root * oscillator running at 19.2Mhz. After the oscillator there are 5 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", * and "HDMI displays". Those 5 PLLs each can divide their output to * produce up to 4 channels. Finally, there is the level of clocks to * be consumed by other hardware components (like "H264" or "HDMI * state machine"), which divide off of some subset of the PLL * channels. * * All of the clocks in the tree are exposed in the DT, because the DT * may want to make assignments of the final layer of clocks to the * PLL channels, and some components of the hardware will actually * skip layers of the tree (for example, the pixel clock comes * directly from the PLLH PIX channel without using a CM_*CTL clock * generator). #include <linux/clk-provider.h>#include <linux/clkdev.h>#include <linux/clk.h>#include <linux/debugfs.h>#include <linux/delay.h>#include <linux/io.h>#include <linux/math.h>#include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/slab.h>#include <dt-bindings/clock/bcm2835.h>#define CM_PASSWORD 0x5a000000#define CM_GNRICCTL 0x000#define CM_GNRICDIV 0x004# define CM_DIV_FRAC_BITS 12# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)#define CM_VPUCTL 0x008#define CM_VPUDIV 0x00c#define CM_SYSCTL 0x010#define CM_SYSDIV 0x014#define CM_PERIACTL 0x018#define CM_PERIADIV 0x01c#define CM_PERIICTL 0x020#define CM_PERIIDIV 0x024#define CM_H264CTL 0x028#define CM_H264DIV 0x02c#define CM_ISPCTL 0x030#define CM_ISPDIV 0x034#define CM_V3DCTL 0x038#define CM_V3DDIV 0x03c#define CM_CAM0CTL 0x040#define CM_CAM0DIV 0x044#define CM_CAM1CTL 0x048#define CM_CAM1DIV 0x04c#define CM_CCP2CTL 0x050#define CM_CCP2DIV 0x054#define CM_DSI0ECTL 0x058#define CM_DSI0EDIV 0x05c#define CM_DSI0PCTL 0x060#define CM_DSI0PDIV 0x064#define CM_DPICTL 0x068#define CM_DPIDIV 0x06c#define CM_GP0CTL 0x070#define CM_GP0DIV 0x074#define CM_GP1CTL 0x078#define CM_GP1DIV 0x07c#define CM_GP2CTL 0x080#define CM_GP2DIV 0x084#define CM_HSMCTL 0x088#define CM_HSMDIV 0x08c#define CM_OTPCTL 0x090#define CM_OTPDIV 0x094#define CM_PCMCTL 0x098#define CM_PCMDIV 0x09c#define CM_PWMCTL 0x0a0#define CM_PWMDIV 0x0a4#define CM_SLIMCTL 0x0a8#define CM_SLIMDIV 0x0ac#define CM_SMICTL 0x0b0#define CM_SMIDIV 0x0b4/* no definition for 0x0b8 and 0x0bc */ #define CM_TCNTCTL 0x0c0# define CM_TCNT_SRC1_SHIFT 12#define CM_TCNTCNT 0x0c4#define CM_TECCTL 0x0c8#define CM_TECDIV 0x0cc#define CM_TD0CTL 0x0d0#define CM_TD0DIV 0x0d4#define CM_TD1CTL 0x0d8#define CM_TD1DIV 0x0dc#define CM_TSENSCTL 0x0e0#define CM_TSENSDIV 0x0e4#define CM_TIMERCTL 0x0e8#define CM_TIMERDIV 0x0ec#define CM_UARTCTL 0x0f0#define CM_UARTDIV 0x0f4#define CM_VECCTL 0x0f8#define CM_VECDIV 0x0fc#define CM_PULSECTL 0x190#define CM_PULSEDIV 0x194#define CM_SDCCTL 0x1a8#define CM_SDCDIV 0x1ac#define CM_ARMCTL 0x1b0#define CM_AVEOCTL 0x1b8#define CM_AVEODIV 0x1bc#define CM_EMMCCTL 0x1c0#define CM_EMMCDIV 0x1c4#define CM_EMMC2CTL 0x1d0#define CM_EMMC2DIV 0x1d4/* General bits for the CM_*CTL regs */ # define CM_ENABLE BIT(4)# define CM_KILL BIT(5)# define CM_GATE_BIT 6# define CM_GATE BIT(CM_GATE_BIT)# define CM_BUSY BIT(7)# define CM_BUSYD BIT(8)# define CM_FRAC BIT(9)# define CM_SRC_SHIFT 0# define CM_SRC_BITS 4# define CM_SRC_MASK 0xf# define CM_SRC_GND 0# define CM_SRC_OSC 1# define CM_SRC_TESTDEBUG0 2# define CM_SRC_TESTDEBUG1 3# define CM_SRC_PLLA_CORE 4# define CM_SRC_PLLA_PER 4# define CM_SRC_PLLC_CORE0 5# define CM_SRC_PLLC_PER 5# define CM_SRC_PLLC_CORE1 8# define CM_SRC_PLLD_CORE 6# define CM_SRC_PLLD_PER 6# define CM_SRC_PLLH_AUX 7# define CM_SRC_PLLC_CORE1 8# define CM_SRC_PLLC_CORE2 9#define CM_OSCCOUNT 0x100#define CM_PLLA 0x104# define CM_PLL_ANARST BIT(8)# define CM_PLLA_HOLDPER BIT(7)# define CM_PLLA_LOADPER BIT(6)# define CM_PLLA_HOLDCORE BIT(5)# define CM_PLLA_LOADCORE BIT(4)# define CM_PLLA_HOLDCCP2 BIT(3)# define CM_PLLA_LOADCCP2 BIT(2)# define CM_PLLA_HOLDDSI0 BIT(1)# define CM_PLLA_LOADDSI0 BIT(0)#define CM_PLLC 0x108# define CM_PLLC_HOLDPER BIT(7)# define CM_PLLC_LOADPER BIT(6)# define CM_PLLC_HOLDCORE2 BIT(5)# define CM_PLLC_LOADCORE2 BIT(4)# define CM_PLLC_HOLDCORE1 BIT(3)# define CM_PLLC_LOADCORE1 BIT(2)# define CM_PLLC_HOLDCORE0 BIT(1)# define CM_PLLC_LOADCORE0 BIT(0)#define CM_PLLD 0x10c# define CM_PLLD_HOLDPER BIT(7)# define CM_PLLD_LOADPER BIT(6)# define CM_PLLD_HOLDCORE BIT(5)# define CM_PLLD_LOADCORE BIT(4)# define CM_PLLD_HOLDDSI1 BIT(3)# define CM_PLLD_LOADDSI1 BIT(2)# define CM_PLLD_HOLDDSI0 BIT(1)# define CM_PLLD_LOADDSI0 BIT(0)#define CM_PLLH 0x110# define CM_PLLH_LOADRCAL BIT(2)# define CM_PLLH_LOADAUX BIT(1)# define CM_PLLH_LOADPIX BIT(0)#define CM_LOCK 0x114# define CM_LOCK_FLOCKH BIT(12)# define CM_LOCK_FLOCKD BIT(11)# define CM_LOCK_FLOCKC BIT(10)# define CM_LOCK_FLOCKB BIT(9)# define CM_LOCK_FLOCKA BIT(8)#define CM_EVENT 0x118#define CM_DSI1ECTL 0x158#define CM_DSI1EDIV 0x15c#define CM_DSI1PCTL 0x160#define CM_DSI1PDIV 0x164#define CM_DFTCTL 0x168#define CM_DFTDIV 0x16c#define CM_PLLB 0x170# define CM_PLLB_HOLDARM BIT(1)# define CM_PLLB_LOADARM BIT(0)#define A2W_PLLA_CTRL 0x1100#define A2W_PLLC_CTRL 0x1120#define A2W_PLLD_CTRL 0x1140#define A2W_PLLH_CTRL 0x1160#define A2W_PLLB_CTRL 0x11e0# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)# define A2W_PLL_CTRL_PWRDN BIT(16)# define A2W_PLL_CTRL_PDIV_MASK 0x000007000# define A2W_PLL_CTRL_PDIV_SHIFT 12# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff# define A2W_PLL_CTRL_NDIV_SHIFT 0#define A2W_PLLA_ANA0 0x1010#define A2W_PLLC_ANA0 0x1030#define A2W_PLLD_ANA0 0x1050#define A2W_PLLH_ANA0 0x1070#define A2W_PLLB_ANA0 0x10f0#define A2W_PLL_KA_SHIFT 7#define A2W_PLL_KA_MASK GENMASK(9, 7)#define A2W_PLL_KI_SHIFT 19#define A2W_PLL_KI_MASK GENMASK(21, 19)#define A2W_PLL_KP_SHIFT 15#define A2W_PLL_KP_MASK GENMASK(18, 15)#define A2W_PLLH_KA_SHIFT 19#define A2W_PLLH_KA_MASK GENMASK(21, 19)#define A2W_PLLH_KI_LOW_SHIFT 22#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)#define A2W_PLLH_KI_HIGH_SHIFT 0#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)#define A2W_PLLH_KP_SHIFT 1#define A2W_PLLH_KP_MASK GENMASK(4, 1)#define A2W_XOSC_CTRL 0x1190# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)#define A2W_PLLA_FRAC 0x1200#define A2W_PLLC_FRAC 0x1220#define A2W_PLLD_FRAC 0x1240#define A2W_PLLH_FRAC 0x1260#define A2W_PLLB_FRAC 0x12e0# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)# define A2W_PLL_FRAC_BITS 20#define A2W_PLL_CHANNEL_DISABLE BIT(8)#define A2W_PLL_DIV_BITS 8#define A2W_PLL_DIV_SHIFT 0#define A2W_PLLA_DSI0 0x1300#define A2W_PLLA_CORE 0x1400#define A2W_PLLA_PER 0x1500#define A2W_PLLA_CCP2 0x1600#define A2W_PLLC_CORE2 0x1320#define A2W_PLLC_CORE1 0x1420#define A2W_PLLC_PER 0x1520#define A2W_PLLC_CORE0 0x1620#define A2W_PLLD_DSI0 0x1340#define A2W_PLLD_CORE 0x1440#define A2W_PLLD_PER 0x1540#define A2W_PLLD_DSI1 0x1640#define A2W_PLLH_AUX 0x1360#define A2W_PLLH_RCAL 0x1460#define A2W_PLLH_PIX 0x1560#define A2W_PLLH_STS 0x1660#define A2W_PLLH_CTRLR 0x1960#define A2W_PLLH_FRACR 0x1a60#define A2W_PLLH_AUXR 0x1b60#define A2W_PLLH_RCALR 0x1c60#define A2W_PLLH_PIXR 0x1d60#define A2W_PLLH_STSR 0x1e60#define A2W_PLLB_ARM 0x13e0#define A2W_PLLB_SP0 0x14e0#define A2W_PLLB_SP1 0x15e0#define A2W_PLLB_SP2 0x16e0#define LOCK_TIMEOUT_NS 100000000#define BCM2835_MAX_FB_RATE 1750000000u#define SOC_BCM2835 BIT(0)#define SOC_BCM2711 BIT(1)#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)/* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that * the clocks node in the DT references external clocks. static const char *const cprman_parent_names[] = {"xosc" ,"dsi0_byte" ,"dsi0_ddr2" ,"dsi0_ddr" ,"dsi1_byte" ,"dsi1_ddr2" ,"dsi1_ddr" ,struct bcm2835_cprman {struct device *dev;void __iomem *regs;/* spinlock for all clocks */ unsigned int soc;/* * Real names of cprman clock parents looked up through * of_clk_get_parent_name(), which will be used in the * parent_names[] arrays for clock registration. const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];/* Must be last */ struct clk_hw_onecell_data onecell;struct cprman_plat_data {unsigned int soc;static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)return readl(cprman->regs + reg);/* Does a cycle of measuring a clock through the TCNT clock, which may * source from many other clocks in the system. static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,/* 1ms */ /* do a kind delay at the start */ /* Finish off whatever is left of OSCCOUNT */ while (cprman_read(cprman, CM_OSCCOUNT)) {if (ktime_after(ktime_get(), timeout)) {"timeout waiting for OSCCOUNT\n" );goto out;/* Wait for BUSY to clear. */ while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {if (ktime_after(ktime_get(), timeout)) {"timeout waiting for !BUSY\n" );goto out;return count * 1000;static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,const struct debugfs_reg32 *regs,struct dentry *dentry)struct debugfs_regset32 *regset;sizeof (*regset), GFP_KERNEL);if (!regset)return ;"regdump" , S_IRUGO, dentry, regset);struct bcm2835_pll_data {const char *name;/* Bit in CM_LOCK to indicate when the PLL has locked. */ const struct bcm2835_pll_ana_bits *ana;unsigned long min_rate;unsigned long max_rate;/* * Highest rate for the VCO before we have to use the * pre-divide-by-2. unsigned long max_fb_rate;struct bcm2835_pll_ana_bits {static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {struct bcm2835_pll_divider_data {const char *name;const char *source_pll;struct bcm2835_clock_data {const char *name;const char *const *parents;int num_mux_parents;/* Bitmap encoding which parents accept rate change propagation. */ unsigned int set_rate_parent;/* Number of integer bits in the divider */ /* Number of fractional bits in the divider */ bool is_vpu_clock;bool is_mash_clock;bool low_jitter;bool round_up;struct bcm2835_gate_data {const char *name;const char *parent;struct bcm2835_pll {struct clk_hw hw;struct bcm2835_cprman *cprman;const struct bcm2835_pll_data *data;static int bcm2835_pll_is_on(struct clk_hw *hw)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);struct bcm2835_cprman *cprman = pll->cprman;const struct bcm2835_pll_data *data = pll->data;return cprman_read(cprman, data->a2w_ctrl_reg) &static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,const struct bcm2835_pll_data *data)/* * On BCM2711 there isn't a pre-divisor available in the PLL feedback * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed * for to for VCO RANGE bits. if (cprman->soc & SOC_BCM2711)return 0;return data->ana->fb_prediv_mask;static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,unsigned long parent_rate,static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,if (pdiv == 0)return 0;return rate >> A2W_PLL_FRAC_BITS;static int bcm2835_pll_determine_rate(struct clk_hw *hw,struct clk_rate_request *req)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);const struct bcm2835_pll_data *data = pll->data;return 0;static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,unsigned long parent_rate)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);struct bcm2835_cprman *cprman = pll->cprman;const struct bcm2835_pll_data *data = pll->data;bool using_prediv;if (parent_rate == 0)return 0;if (using_prediv) {return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);static void bcm2835_pll_off(struct clk_hw *hw)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);struct bcm2835_cprman *cprman = pll->cprman;const struct bcm2835_pll_data *data = pll->data;static int bcm2835_pll_on(struct clk_hw *hw)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);struct bcm2835_cprman *cprman = pll->cprman;const struct bcm2835_pll_data *data = pll->data;/* Take the PLL out of reset. */ /* Wait for the PLL to lock. */ while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {if (ktime_after(ktime_get(), timeout)) {"%s: couldn't lock PLL\n" ,return -ETIMEDOUT;return 0;static void struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)int i;/* * ANA register setup is done as a series of writes to * ANA3-ANA0, in that order. This lets us write all 4 * registers as a single cycle of the serdes interface (taking * 100 xosc clocks), whereas if we were to update ana0, 1, and * 3 individually through their partial-write registers, each * would be their own serdes cycle. for (i = 3; i >= 0; i--)static int bcm2835_pll_set_rate(struct clk_hw *hw,unsigned long rate, unsigned long parent_rate)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);struct bcm2835_cprman *cprman = pll->cprman;const struct bcm2835_pll_data *data = pll->data;bool was_using_prediv, use_fb_prediv, do_ana_setup_first;int i;if (rate > data->max_fb_rate) {true ;else {false ;for (i = 3; i >= 0; i--)if (was_using_prediv && !use_fb_prediv) {true ;else if (!was_using_prediv && use_fb_prediv) {false ;else {true ;/* Unmask the reference clock from the oscillator. */ if (do_ana_setup_first)/* Set the PLL multiplier from the oscillator. */ if (!do_ana_setup_first)return 0;static void bcm2835_pll_debug_init(struct clk_hw *hw,struct dentry *dentry)struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);struct bcm2835_cprman *cprman = pll->cprman;const struct bcm2835_pll_data *data = pll->data;struct debugfs_reg32 *regs;sizeof (*regs), GFP_KERNEL);if (!regs)return ;"cm_ctrl" ;"a2w_ctrl" ;"frac" ;"ana0" ;"ana1" ;"ana2" ;"ana3" ;static const struct clk_ops bcm2835_pll_clk_ops = {struct bcm2835_pll_divider {struct clk_divider div;struct bcm2835_cprman *cprman;const struct bcm2835_pll_divider_data *data;static struct bcm2835_pll_divider *struct clk_hw *hw)return container_of(hw, struct bcm2835_pll_divider, div.hw);static int bcm2835_pll_divider_is_on(struct clk_hw *hw)struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);struct bcm2835_cprman *cprman = divider->cprman;const struct bcm2835_pll_divider_data *data = divider->data;return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,struct clk_rate_request *req)return clk_divider_ops.determine_rate(hw, req);static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,unsigned long parent_rate)return clk_divider_ops.recalc_rate(hw, parent_rate);static void bcm2835_pll_divider_off(struct clk_hw *hw)struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);struct bcm2835_cprman *cprman = divider->cprman;const struct bcm2835_pll_divider_data *data = divider->data;static int bcm2835_pll_divider_on(struct clk_hw *hw)struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);struct bcm2835_cprman *cprman = divider->cprman;const struct bcm2835_pll_divider_data *data = divider->data;return 0;static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,unsigned long rate,unsigned long parent_rate)struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);struct bcm2835_cprman *cprman = divider->cprman;const struct bcm2835_pll_divider_data *data = divider->data;if (div == max_div)return 0;static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,struct dentry *dentry)struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);struct bcm2835_cprman *cprman = divider->cprman;const struct bcm2835_pll_divider_data *data = divider->data;struct debugfs_reg32 *regs;sizeof (*regs), GFP_KERNEL);if (!regs)return ;"cm" ;"a2w" ;static const struct clk_ops bcm2835_pll_divider_clk_ops = {/* * The CM dividers do fixed-point division, so we can't use the * generic integer divider code like the PLL dividers do (and we can't * fake it by having some fixed shifts preceding it in the clock tree, * because we'd run out of bits in a 32-bit unsigned long). struct bcm2835_clock {struct clk_hw hw;struct bcm2835_cprman *cprman;const struct bcm2835_clock_data *data;static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)return container_of(hw, struct bcm2835_clock, hw);static int bcm2835_clock_is_on(struct clk_hw *hw)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;static u32 bcm2835_clock_choose_div(struct clk_hw *hw,unsigned long rate,unsigned long parent_rate)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);const struct bcm2835_clock_data *data = clock->data;/* different clamping limits apply for a mash clock */ if (data->is_mash_clock) {/* clamp to min divider of 2 */ /* clamp to the highest possible integer divider */ else {/* clamp to min divider of 1 */ /* clamp to the highest possible fractional divider */ /* apply the clamping limits */ return div;static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,unsigned long parent_rate,const struct bcm2835_clock_data *data = clock->data;if (data->int_bits == 0 && data->frac_bits == 0)return parent_rate;/* * The divisor is a 12.12 fixed point field, but only some of * the bits are populated in any given clock. if (div == 0)return 0;return temp;static unsigned long bcm2835_round_rate(unsigned long rate)unsigned long scaler;unsigned long limit;while (scaler < limit)/* * If increasing a clock by less than 0.1% changes it * from ..999.. to ..000.., round up. if ((rate + scaler - 1) / scaler % 1000 == 0)return rate;static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,unsigned long parent_rate)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;unsigned long rate;if (data->int_bits == 0 && data->frac_bits == 0)return parent_rate;if (data->round_up)return rate;static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {if (ktime_after(ktime_get(), timeout)) {"%s: couldn't lock PLL\n" ,return ;static void bcm2835_clock_off(struct clk_hw *hw)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;/* BUSY will remain high until the divider completes its cycle. */ static int bcm2835_clock_on(struct clk_hw *hw)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;/* Debug code to measure the clock once it's turned on to see * if it's ticking at the rate we expect. if (data->tcnt_mux && false ) {"clk %s: rate %ld, measure %ld\n" ,return 0;static int bcm2835_clock_set_rate(struct clk_hw *hw,unsigned long rate, unsigned long parent_rate)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;/* * Setting up frac support * * In principle it is recommended to stop/start the clock first, * but as we set CLK_SET_RATE_GATE during registration of the * clock this requirement should be take care of by the * clk-framework. return 0;static bool struct clk_hw *hw)if (!hw)return false ;return strncmp(clk_hw_get_name(hw), "pllc" , 4) == 0;static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,int parent_idx,unsigned long rate,unsigned long *prate,unsigned long *avgrate)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;unsigned long best_rate = 0;struct clk_hw *parent;if (!(BIT(parent_idx) & data->set_rate_parent)) {if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {unsigned long high, low;/* * Return a value which is the maximum deviation * below the ideal rate, for use as a metric. return *avgrate - max(*avgrate - low, high - *avgrate);return *avgrate;if (data->frac_bits)"frac bits are not used when propagating rate change" );/* clamp to min divider of 2 if we're dealing with a mash clock */ /* TODO: Be smart, and only test a subset of the available divisors. */ for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {unsigned long tmp_rate;if (curdiv == mindiv ||if (best_rate == rate)break ;return best_rate;static int bcm2835_clock_determine_rate(struct clk_hw *hw,struct clk_rate_request *req)struct clk_hw *parent, *best_parent = NULL;bool current_parent_is_pllc;unsigned long rate, best_rate = 0;unsigned long prate, best_prate = 0;unsigned long avgrate, best_avgrate = 0;/* * Select parent clock that results in the closest but lower rate for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {if (!parent)continue ;/* * Don't choose a PLLC-derived clock as our parent * unless it had been manually set that way. PLLC's * frequency gets adjusted by the firmware due to * over-temp or under-voltage conditions, without * prior notification to our clock consumer. if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)continue ;if (abs(req->rate - rate) < abs(req->rate - best_rate)) {if (!best_parent)return -EINVAL;return 0;static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;return 0;static u8 bcm2835_clock_get_parent(struct clk_hw *hw)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {"ctl" ,"div" ,static void bcm2835_clock_debug_init(struct clk_hw *hw,struct dentry *dentry)struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);struct bcm2835_cprman *cprman = clock->cprman;const struct bcm2835_clock_data *data = clock->data;static const struct clk_ops bcm2835_clock_clk_ops = {static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)return true ;/* * The VPU clock can never be disabled (it doesn't have an ENABLE * bit), so it gets its own set of clock ops. static const struct clk_ops bcm2835_vpu_clock_clk_ops = {static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,const void *data)const struct bcm2835_pll_data *pll_data = data;struct bcm2835_pll *pll;struct clk_init_data init;int ret;sizeof (init));/* All of the PLLs derive from the external oscillator. */ sizeof (*pll), GFP_KERNEL);if (!pll)return NULL;if (ret) {return NULL;return &pll->hw;static struct clk_hw *struct bcm2835_cprman *cprman,const void *data)const struct bcm2835_pll_divider_data *divider_data = data;struct bcm2835_pll_divider *divider;struct clk_init_data init;const char *divider_name;int ret;if (divider_data->fixed_divider != 1) {"%s_prediv" , divider_data->name);if (!divider_name)return NULL;else {sizeof (init));sizeof (*divider), GFP_KERNEL);if (!divider)return NULL;if (ret)return ERR_PTR(ret);/* * PLLH's channels have a fixed divide by 10 afterwards, which * is what our consumers are actually using. if (divider_data->fixed_divider != 1) {return clk_hw_register_fixed_factor(cprman->dev,return ÷r->div.hw;static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,const void *data)const struct bcm2835_clock_data *clock_data = data;struct bcm2835_clock *clock;struct clk_init_data init;const char *parents[1 << CM_SRC_BITS];int ret;/* * Replace our strings referencing parent clocks with the * actual clock-output-name of the parent. for (i = 0; i < clock_data->num_mux_parents; i++) {if (ret >= 0)sizeof (init));/* * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate * rate changes on at least of the parents. if (clock_data->set_rate_parent)if (clock_data->is_vpu_clock) {else {/* If the clock wasn't actually enabled at boot, it's not * critical. if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))sizeof (*clock), GFP_KERNEL);if (!clock)return NULL;if (ret)return ERR_PTR(ret);return &clock->hw;static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,const void *data)const struct bcm2835_gate_data *gate_data = data;return clk_hw_register_gate(cprman->dev, gate_data->name,struct bcm2835_clk_desc {struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,const void *data);unsigned int supported;const void *data;/* assignment helper macros for different clock types */ #define _REGISTER (f, s, ...) { .clk_register = f, \#define REGISTER_PLL(s, ...) _REGISTER (&bcm2835_register_pll, \struct bcm2835_pll_data) \#define REGISTER_PLL_DIV(s, ...) _REGISTER (&bcm2835_register_pll_divider, \struct bcm2835_pll_divider_data) \#define REGISTER_CLK(s, ...) _REGISTER (&bcm2835_register_clock, \struct bcm2835_clock_data) \#define REGISTER_GATE(s, ...) _REGISTER (&bcm2835_register_gate, \struct bcm2835_gate_data) \/* parent mux arrays plus helper macros */ /* main oscillator parent mux */ static const char *const bcm2835_clock_osc_parents[] = {"gnd" ,"xosc" ,"testdebug0" ,"testdebug1" #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \/* main peripheral parent mux */ static const char *const bcm2835_clock_per_parents[] = {"gnd" ,"xosc" ,"testdebug0" ,"testdebug1" ,"plla_per" ,"pllc_per" ,"plld_per" ,"pllh_aux" ,#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \/* * Restrict clock sources for the PCM peripheral to the oscillator and * PLLD_PER because other source may have varying rates or be switched * off. * * Prevent other sources from being selected by replacing their names in * the list of potential parents with dummy entries (entry index is * significant). static const char *const bcm2835_pcm_per_parents[] = {"-" ,"xosc" ,"-" ,"-" ,"-" ,"-" ,"plld_per" ,"-" ,#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \/* main vpu parent mux */ static const char *const bcm2835_clock_vpu_parents[] = {"gnd" ,"xosc" ,"testdebug0" ,"testdebug1" ,"plla_core" ,"pllc_core0" ,"plld_core" ,"pllh_aux" ,"pllc_core1" ,"pllc_core2" ,#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \/* * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI * analog PHY. The _inv variants are generated internally to cprman, * but we don't use them so they aren't hooked up. static const char *const bcm2835_clock_dsi0_parents[] = {"gnd" ,"xosc" ,"testdebug0" ,"testdebug1" ,"dsi0_ddr" ,"dsi0_ddr_inv" ,"dsi0_ddr2" ,"dsi0_ddr2_inv" ,"dsi0_byte" ,"dsi0_byte_inv" ,static const char *const bcm2835_clock_dsi1_parents[] = {"gnd" ,"xosc" ,"testdebug0" ,"testdebug1" ,"dsi1_ddr" ,"dsi1_ddr_inv" ,"dsi1_ddr2" ,"dsi1_ddr2_inv" ,"dsi1_byte" ,"dsi1_byte_inv" ,#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \/* * the real definition of all the pll, pll_dividers and clocks * these make use of the above REGISTER_* macros static const struct bcm2835_clk_desc clk_desc_array[] = {/* the PLL + PLL dividers */ /* * PLLA is the auxiliary PLL, used to drive the CCP2 * (Compact Camera Port 2) transmitter clock. * * It is in the PX LDO power domain, which is on when the * AUDIO domain is on. "plla" ,"plla_core" ,"plla" ,"plla_per" ,"plla" ,"plla_dsi0" ,"plla" ,"plla_ccp2" ,"plla" ,/* PLLB is used for the ARM's clock. */ "pllb" ,"pllb_arm" ,"pllb" ,/* * PLLC is the core PLL, used to drive the core VPU clock. * * It is in the PX LDO power domain, which is on when the * AUDIO domain is on. "pllc" ,"pllc_core0" ,"pllc" ,"pllc_core1" ,"pllc" ,"pllc_core2" ,"pllc" ,"pllc_per" ,"pllc" ,/* * PLLD is the display PLL, used to drive DSI display panels. * * It is in the PX LDO power domain, which is on when the * AUDIO domain is on. "plld" ,"plld_core" ,"plld" ,/* * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core. * Otherwise this could cause firmware lookups. That's why we mark * it as critical. "plld_per" ,"plld" ,"plld_dsi0" ,"plld" ,"plld_dsi1" ,"plld" ,/* * PLLH is used to supply the pixel clock or the AUX clock for the * TV encoder. * * It is in the HDMI power domain. "pllh" ,"pllh_rcal" ,"pllh" ,"pllh_aux" ,"pllh" ,"pllh_pix" ,"pllh" ,/* the clocks */ /* clocks with oscillator parent mux */ /* One Time Programmable Memory clock. Maximum 10Mhz. */ "otp" ,/* * Used for a 1Mhz clock for the system clocksource, and also used * bythe watchdog timer and the camera pulse generator. "timer" ,/* * Clock for the temperature sensor. * Generally run at 2Mhz, max 5Mhz. "tsens" ,"tec" ,/* clocks with vpu parent mux */ "h264" ,"isp" ,/* * Secondary SDRAM clock. Used for low-voltage modes when the PLL * in the SDRAM controller can't be used. "sdram" ,"v3d" ,/* * VPU clock. This doesn't have an enable bit, since it drives * the bus for everything else, and is special so it doesn't need * to be gated for rate changes. It is also known as "clk_audio" * in various hardware documentation. "vpu" ,true ,/* clocks with per parent mux */ "aveo" ,"cam0" ,"cam1" ,"dft" ,"dpi" ,/* Arasan EMMC clock */ "emmc" ,/* EMMC2 clock (only available for BCM2711) */ "emmc2" ,/* General purpose (GPIO) clocks */ "gp0" ,true ,"gp1" ,true ,"gp2" ,/* HDMI state machine */ "hsm" ,"pcm" ,true ,true ,"pwm" ,true ,"slim" ,true ,"smi" ,"uart" ,true ),/* TV encoder clock. Only operating frequency is 108Mhz. */ "vec" ,/* * Allow rate change propagation only on PLLH_AUX which is * assigned index 7 in the parent array. /* dsi clocks */ "dsi0e" ,"dsi1e" ,"dsi0p" ,"dsi1p" ,/* the gates */ /* * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if * you have the debug bit set in the power manager, which we * don't bother exposing) are individual gates off of the * non-stop vpu clock. "peri_image" ,"vpu" ,/* * Permanently take a reference on the parent of the SDRAM clock. * * While the SDRAM is being driven by its dedicated PLL most of the * time, there is a little loop running in the firmware that * periodically switches the SDRAM to using our CM clock to do PVT * recalibration, with the assumption that the previously configured * SDRAM parent is still enabled and running. static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)struct clk *parent = clk_get_parent(sdc);if (IS_ERR(parent))return PTR_ERR(parent);return clk_prepare_enable(parent);static int bcm2835_clk_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct clk_hw **hws;struct bcm2835_cprman *cprman;const struct bcm2835_clk_desc *desc;const size_t asize = ARRAY_SIZE(clk_desc_array);const struct cprman_plat_data *pdata;int ret;if (!pdata)return -ENODEV;if (!cprman)return -ENOMEM;if (IS_ERR(cprman->regs))return PTR_ERR(cprman->regs);sizeof (cprman_parent_names));/* * Make sure the external oscillator has been registered. * * The other (DSI) clocks are not present on older device * trees, which we still need to support for backwards * compatibility. if (!cprman->real_parent_names[0])return -ENODEV;for (i = 0; i < asize; i++) {if (desc->clk_register && desc->data &&if (ret)return ret;return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,static const struct cprman_plat_data cprman_bcm2835_plat_data = {static const struct cprman_plat_data cprman_bcm2711_plat_data = {static const struct of_device_id bcm2835_clk_of_match[] = {"brcm,bcm2835-cprman" , .data = &cprman_bcm2835_plat_data },"brcm,bcm2711-cprman" , .data = &cprman_bcm2711_plat_data },static struct platform_driver bcm2835_clk_driver = {"bcm2835-clk" ,"Eric Anholt " );"BCM2835 clock driver" );
Messung V0.5 C=96 H=96 G=95
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