// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018 MediaTek Inc. * Author: Ryder Lee <ryder.lee@mediatek.com> #include <linux/clk-provider.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/of_platform.h>#include <linux/platform_device.h>#include "clk-mtk.h" #include "clk-gate.h" #include <dt-bindings/clock/mt2701-clk.h>#define GATE_AUDIO0(_id, _name, _parent, _shift) \#define GATE_AUDIO1(_id, _name, _parent, _shift) \#define GATE_AUDIO2(_id, _name, _parent, _shift) \#define GATE_AUDIO3(_id, _name, _parent, _shift) \static const struct mtk_gate_regs audio0_cg_regs = {static const struct mtk_gate_regs audio1_cg_regs = {static const struct mtk_gate_regs audio2_cg_regs = {static const struct mtk_gate_regs audio3_cg_regs = {static const struct mtk_gate audio_clks[] = {"aud_dummy" ),/* AUDIO0 */ "audio_afe" , "aud_intbus_sel" , 2),"audio_lrck_detect_dummy" ),"audio_i2c_dummy" ),"audio_apll_tuner_dummy" ),"audio_hdmi" , "audpll_sel" , 20),"audio_spdf" , "audpll_sel" , 21),"audio_spdf2" , "audpll_sel" , 22),"audio_apll" , "audpll_sel" , 23),"audio_tml_dummy" ),"audio_ahb_idle_ext_dummy" ),"audio_ahb_idle_int_dummy" ),/* AUDIO1 */ "audio_i2sin1" , "aud_mux1_sel" , 0),"audio_i2sin2" , "aud_mux1_sel" , 1),"audio_i2sin3" , "aud_mux1_sel" , 2),"audio_i2sin4" , "aud_mux1_sel" , 3),"audio_i2sin5" , "aud_mux1_sel" , 4),"audio_i2sin6" , "aud_mux1_sel" , 5),"audio_i2so1" , "aud_mux1_sel" , 6),"audio_i2so2" , "aud_mux1_sel" , 7),"audio_i2so3" , "aud_mux1_sel" , 8),"audio_i2so4" , "aud_mux1_sel" , 9),"audio_i2so5" , "aud_mux1_sel" , 10),"audio_i2so6" , "aud_mux1_sel" , 11),"audio_asrci1" , "asm_h_sel" , 12),"audio_asrci2" , "asm_h_sel" , 13),"audio_asrco1" , "asm_h_sel" , 14),"audio_asrco2" , "asm_h_sel" , 15),"audio_hdmirx_dummy" ),"audio_intdir" , "intdir_sel" , 20),"audio_a1sys" , "aud_mux1_sel" , 21),"audio_a2sys" , "aud_mux2_sel" , 22),"audio_afe_conn" , "aud_mux1_sel" , 23),"audio_afe_pcmif_dummy" ),"audio_afe_mrgif" , "aud_mux1_sel" , 25),/* AUDIO2 */ "audio_ul1" , "aud_mux1_sel" , 0),"audio_ul2" , "aud_mux1_sel" , 1),"audio_ul3" , "aud_mux1_sel" , 2),"audio_ul4" , "aud_mux1_sel" , 3),"audio_ul5" , "aud_mux1_sel" , 4),"audio_ul6" , "aud_mux1_sel" , 5),"audio_dl1" , "aud_mux1_sel" , 6),"audio_dl2" , "aud_mux1_sel" , 7),"audio_dl3" , "aud_mux1_sel" , 8),"audio_dl4" , "aud_mux1_sel" , 9),"audio_dl5" , "aud_mux1_sel" , 10),"audio_dl6" , "aud_mux1_sel" , 11),"audio_dlmch" , "aud_mux1_sel" , 12),"audio_arb1" , "aud_mux1_sel" , 13),"audio_awb" , "aud_mux1_sel" , 14),"audio_awb2" , "aud_mux1_sel" , 15),"audio_dai" , "aud_mux1_sel" , 16),/* AUDIO3 */ "audio_dmic1_dummy" ),"audio_dmic2_dummy" ),"audio_asrci3" , "asm_h_sel" , 2),"audio_asrci4" , "asm_h_sel" , 3),"audio_asrci5" , "asm_h_sel" , 4),"audio_asrci6" , "asm_h_sel" , 5),"audio_asrco3" , "asm_h_sel" , 6),"audio_asrco4" , "asm_h_sel" , 7),"audio_asrco5" , "asm_h_sel" , 8),"audio_asrco6" , "asm_h_sel" , 9),"audio_mem_asrc1" , "asm_h_sel" , 10),"audio_mem_asrc2" , "asm_h_sel" , 11),"audio_mem_asrc3" , "asm_h_sel" , 12),"audio_mem_asrc4" , "asm_h_sel" , 13),"audio_mem_asrc5" , "asm_h_sel" , 14),static const struct mtk_clk_desc audio_desc = {static const struct of_device_id of_match_clk_mt2701_aud[] = {"mediatek,mt2701-audsys" , .data = &audio_desc },/* sentinel */ } static int clk_mt2701_aud_probe(struct platform_device *pdev)int r;if (r) {"could not register clock provider: %s: %d\n" ,return r;if (r)goto err_plat_populate;return 0;return r;static void clk_mt2701_aud_remove(struct platform_device *pdev)static struct platform_driver clk_mt2701_aud_drv = {"clk-mt2701-aud" ,"MediaTek MT2701 audio clocks driver" );"GPL" );
Messung V0.5 C=97 H=96 G=96
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