// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017 MediaTek Inc. * Author: Weiyi Lu <weiyi.lu@mediatek.com> #include <linux/clk.h>#include <linux/delay.h>#include <linux/mfd/syscon.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <linux/slab.h>#include "clk-gate.h" #include "clk-mtk.h" #include <dt-bindings/clock/mt2712-clk.h>static DEFINE_SPINLOCK(mt2712_clk_lock);static const struct mtk_fixed_clk top_fixed_clks[] = {"vpll3_dpix" , NULL, 200000000),"vpll_dpix" , NULL, 200000000),"ltepll_fs26m" , NULL, 26000000),"dmpll_ck" , NULL, 350000000),"dsi0_lntc" , NULL, 143000000),"dsi1_lntc" , NULL, 143000000),"lvdstx3" , NULL, 140000000),"lvdstx" , NULL, 140000000),"clkrtc_ext" , NULL, 32768),"clkrtc_int" , NULL, 32747),"csi0" , NULL, 26000000),"cvbspll" , NULL, 108000000),static const struct mtk_fixed_factor top_divs[] = {"sys_26m" , "clk26m" , 1, 1),"clk26m_d2" , "sys_26m" , 1, 2),"armca35pll_ck" , "armca35pll" , 1, 1),"armca35pll_600m" , "armca35pll_ck" , 1, 2),"armca35pll_400m" , "armca35pll_ck" , 1, 3),"armca72pll_ck" , "armca72pll" , 1, 1),"syspll_ck" , "mainpll" , 1, 1),"syspll_d2" , "syspll_ck" , 1, 2),"syspll1_d2" , "syspll_d2" , 1, 2),"syspll1_d4" , "syspll_d2" , 1, 4),"syspll1_d8" , "syspll_d2" , 1, 8),"syspll1_d16" , "syspll_d2" , 1, 16),"syspll_d3" , "syspll_ck" , 1, 3),"syspll2_d2" , "syspll_d3" , 1, 2),"syspll2_d4" , "syspll_d3" , 1, 4),"syspll_d5" , "syspll_ck" , 1, 5),"syspll3_d2" , "syspll_d5" , 1, 2),"syspll3_d4" , "syspll_d5" , 1, 4),"syspll_d7" , "syspll_ck" , 1, 7),"syspll4_d2" , "syspll_d7" , 1, 2),"syspll4_d4" , "syspll_d7" , 1, 4),"univpll_ck" , "univpll" , 1, 1),"univpll_d7" , "univpll_ck" , 1, 7),"univpll_d26" , "univpll_ck" , 1, 26),"univpll_d52" , "univpll_ck" , 1, 52),"univpll_d104" , "univpll_ck" , 1, 104),"univpll_d208" , "univpll_ck" , 1, 208),"univpll_d2" , "univpll_ck" , 1, 2),"univpll1_d2" , "univpll_d2" , 1, 2),"univpll1_d4" , "univpll_d2" , 1, 4),"univpll1_d8" , "univpll_d2" , 1, 8),"univpll_d3" , "univpll_ck" , 1, 3),"univpll2_d2" , "univpll_d3" , 1, 2),"univpll2_d4" , "univpll_d3" , 1, 4),"univpll2_d8" , "univpll_d3" , 1, 8),"univpll_d5" , "univpll_ck" , 1, 5),"univpll3_d2" , "univpll_d5" , 1, 2),"univpll3_d4" , "univpll_d5" , 1, 4),"univpll3_d8" , "univpll_d5" , 1, 8),"f_mp0_pll1_ck" , "univpll_d2" , 1, 1),"f_mp0_pll2_ck" , "univpll1_d2" , 1, 1),"f_big_pll1_ck" , "univpll_d2" , 1, 1),"f_big_pll2_ck" , "univpll1_d2" , 1, 1),"f_bus_pll1_ck" , "univpll_d2" , 1, 1),"f_bus_pll2_ck" , "univpll1_d2" , 1, 1),"apll1_ck" , "apll1" , 1, 1),"apll1_d2" , "apll1_ck" , 1, 2),"apll1_d4" , "apll1_ck" , 1, 4),"apll1_d8" , "apll1_ck" , 1, 8),"apll1_d16" , "apll1_ck" , 1, 16),"apll2_ck" , "apll2" , 1, 1),"apll2_d2" , "apll2_ck" , 1, 2),"apll2_d4" , "apll2_ck" , 1, 4),"apll2_d8" , "apll2_ck" , 1, 8),"apll2_d16" , "apll2_ck" , 1, 16),"lvdspll_ck" , "lvdspll" , 1, 1),"lvdspll_d2" , "lvdspll_ck" , 1, 2),"lvdspll_d4" , "lvdspll_ck" , 1, 4),"lvdspll_d8" , "lvdspll_ck" , 1, 8),"lvdspll2_ck" , "lvdspll2" , 1, 1),"lvdspll2_d2" , "lvdspll2_ck" , 1, 2),"lvdspll2_d4" , "lvdspll2_ck" , 1, 4),"lvdspll2_d8" , "lvdspll2_ck" , 1, 8),"etherpll_125m" , "etherpll" , 1, 1),"etherpll_50m" , "etherpll" , 1, 1),"cvbs" , "cvbspll" , 1, 1),"cvbs_d2" , "cvbs" , 1, 2),"mmpll_ck" , "mmpll" , 1, 1),"mmpll_d2" , "mmpll_ck" , 1, 2),"vencpll_ck" , "vencpll" , 1, 1),"vencpll_d2" , "vencpll_ck" , 1, 2),"vcodecpll_ck" , "vcodecpll" , 1, 1),"vcodecpll_d2" , "vcodecpll_ck" , 1, 2),"tvdpll_ck" , "tvdpll" , 1, 1),"tvdpll_d2" , "tvdpll_ck" , 1, 2),"tvdpll_d4" , "tvdpll_ck" , 1, 4),"tvdpll_d8" , "tvdpll_ck" , 1, 8),"tvdpll_429m" , "tvdpll" , 1, 1),"tvdpll_429m_d2" , "tvdpll_429m" , 1, 2),"tvdpll_429m_d4" , "tvdpll_429m" , 1, 4),"msdcpll_ck" , "msdcpll" , 1, 1),"msdcpll_d2" , "msdcpll_ck" , 1, 2),"msdcpll_d4" , "msdcpll_ck" , 1, 4),"msdcpll2_ck" , "msdcpll2" , 1, 1),"msdcpll2_d2" , "msdcpll2_ck" , 1, 2),"msdcpll2_d4" , "msdcpll2_ck" , 1, 4),"d2a_ulclk_6p5m" , "clk26m" , 1, 4),"apll1_d3" , "apll1_ck" , 1, 3),"apll2_d3" , "apll2_ck" , 1, 3),static const char * const axi_parents[] = {"clk26m" ,"syspll1_d2" ,"syspll_d5" ,"syspll1_d4" ,"univpll_d5" ,"univpll2_d2" ,"msdcpll2_ck" static const char * const mem_parents[] = {"clk26m" ,"dmpll_ck" static const char * const mm_parents[] = {"clk26m" ,"vencpll_ck" ,"syspll_d3" ,"syspll1_d2" ,"syspll_d5" ,"syspll1_d4" ,"univpll1_d2" ,"univpll2_d2" static const char * const pwm_parents[] = {"clk26m" ,"univpll2_d4" ,"univpll3_d2" ,"univpll1_d4" static const char * const vdec_parents[] = {"clk26m" ,"vcodecpll_ck" ,"tvdpll_429m" ,"univpll_d3" ,"vencpll_ck" ,"syspll_d3" ,"univpll1_d2" ,"mmpll_d2" ,"syspll3_d2" ,"tvdpll_ck" static const char * const venc_parents[] = {"clk26m" ,"univpll1_d2" ,"mmpll_d2" ,"tvdpll_d2" ,"syspll1_d2" ,"univpll_d5" ,"vcodecpll_d2" ,"univpll2_d2" ,"syspll3_d2" static const char * const mfg_parents[] = {"clk26m" ,"mmpll_ck" ,"univpll_d3" ,"clk26m" ,"clk26m" ,"clk26m" ,"clk26m" ,"clk26m" ,"clk26m" ,"syspll_d3" ,"syspll1_d2" ,"syspll_d5" ,"univpll_d3" ,"univpll1_d2" ,"univpll_d5" ,"univpll2_d2" static const char * const camtg_parents[] = {"clk26m" ,"univpll_d52" ,"univpll_d208" ,"univpll_d104" ,"clk26m_d2" ,"univpll_d26" ,"univpll2_d8" ,"syspll3_d4" ,"syspll3_d2" ,"univpll1_d4" ,"univpll2_d2" static const char * const uart_parents[] = {"clk26m" ,"univpll2_d8" static const char * const spi_parents[] = {"clk26m" ,"univpll2_d4" ,"univpll1_d4" ,"univpll2_d2" ,"univpll3_d2" ,"univpll1_d8" static const char * const usb20_parents[] = {"clk26m" ,"univpll1_d8" ,"univpll3_d4" static const char * const usb30_parents[] = {"clk26m" ,"univpll3_d2" ,"univpll3_d4" ,"univpll2_d4" static const char * const msdc50_0_h_parents[] = {"clk26m" ,"syspll1_d2" ,"syspll2_d2" ,"syspll4_d2" ,"univpll_d5" ,"univpll1_d4" static const char * const msdc50_0_parents[] = {"clk26m" ,"msdcpll_ck" ,"msdcpll_d2" ,"univpll1_d4" ,"syspll2_d2" ,"msdcpll_d4" ,"vencpll_d2" ,"univpll1_d2" ,"msdcpll2_ck" ,"msdcpll2_d2" ,"msdcpll2_d4" static const char * const msdc30_1_parents[] = {"clk26m" ,"univpll2_d2" ,"msdcpll_d2" ,"univpll1_d4" ,"syspll2_d2" ,"univpll_d7" ,"vencpll_d2" static const char * const msdc30_3_parents[] = {"clk26m" ,"msdcpll2_ck" ,"msdcpll2_d2" ,"univpll2_d2" ,"msdcpll2_d4" ,"univpll1_d4" ,"syspll2_d2" ,"syspll_d7" ,"univpll_d7" ,"vencpll_d2" ,"msdcpll_ck" ,"msdcpll_d2" ,"msdcpll_d4" static const char * const audio_parents[] = {"clk26m" ,"syspll3_d4" ,"syspll4_d4" ,"syspll1_d16" static const char * const aud_intbus_parents[] = {"clk26m" ,"syspll1_d4" ,"syspll4_d2" ,"univpll3_d2" ,"univpll2_d8" ,"syspll3_d2" ,"syspll3_d4" static const char * const pmicspi_parents[] = {"clk26m" ,"syspll1_d8" ,"syspll3_d4" ,"syspll1_d16" ,"univpll3_d4" ,"univpll_d26" ,"syspll3_d4" static const char * const dpilvds1_parents[] = {"clk26m" ,"lvdspll2_ck" ,"lvdspll2_d2" ,"lvdspll2_d4" ,"lvdspll2_d8" ,"clkfpc" static const char * const atb_parents[] = {"clk26m" ,"syspll1_d2" ,"univpll_d5" ,"syspll_d5" static const char * const nr_parents[] = {"clk26m" ,"univpll1_d4" ,"syspll2_d2" ,"syspll1_d4" ,"univpll1_d8" ,"univpll3_d2" ,"univpll2_d2" ,"syspll_d5" static const char * const nfi2x_parents[] = {"clk26m" ,"syspll4_d4" ,"univpll3_d4" ,"univpll1_d8" ,"syspll2_d4" ,"univpll3_d2" ,"syspll_d7" ,"syspll2_d2" ,"univpll2_d2" ,"syspll_d5" ,"syspll1_d2" static const char * const irda_parents[] = {"clk26m" ,"univpll2_d4" ,"syspll2_d4" ,"univpll2_d8" static const char * const cci400_parents[] = {"clk26m" ,"vencpll_ck" ,"armca35pll_600m" ,"armca35pll_400m" ,"univpll_d2" ,"syspll_d2" ,"msdcpll_ck" ,"univpll_d3" static const char * const aud_1_parents[] = {"clk26m" ,"apll1_ck" ,"univpll2_d4" ,"univpll2_d8" static const char * const aud_2_parents[] = {"clk26m" ,"apll2_ck" ,"univpll2_d4" ,"univpll2_d8" static const char * const mem_mfg_parents[] = {"clk26m" ,"mmpll_ck" ,"univpll_d3" static const char * const axi_mfg_parents[] = {"clk26m" ,"axi_sel" ,"univpll_d5" static const char * const scam_parents[] = {"clk26m" ,"syspll3_d2" ,"univpll2_d4" ,"syspll2_d4" static const char * const nfiecc_parents[] = {"clk26m" ,"nfi2x_sel" ,"syspll_d7" ,"syspll2_d2" ,"univpll2_d2" ,"univpll_d5" ,"syspll1_d2" static const char * const pe2_mac_p0_parents[] = {"clk26m" ,"syspll1_d8" ,"syspll4_d2" ,"syspll2_d4" ,"univpll2_d4" ,"syspll3_d2" static const char * const dpilvds_parents[] = {"clk26m" ,"lvdspll_ck" ,"lvdspll_d2" ,"lvdspll_d4" ,"lvdspll_d8" ,"clkfpc" static const char * const hdcp_parents[] = {"clk26m" ,"syspll4_d2" ,"syspll3_d4" ,"univpll2_d4" static const char * const hdcp_24m_parents[] = {"clk26m" ,"univpll_d26" ,"univpll_d52" ,"univpll2_d8" static const char * const rtc_parents[] = {"clkrtc_int" ,"clkrtc_ext" ,"clk26m" ,"univpll3_d8" static const char * const spinor_parents[] = {"clk26m" ,"clk26m_d2" ,"syspll4_d4" ,"univpll2_d8" ,"univpll3_d4" ,"syspll4_d2" ,"syspll2_d4" ,"univpll2_d4" ,"etherpll_125m" ,"syspll1_d4" static const char * const apll_parents[] = {"clk26m" ,"apll1_ck" ,"apll1_d2" ,"apll1_d4" ,"apll1_d8" ,"apll1_d16" ,"apll2_ck" ,"apll2_d2" ,"apll2_d4" ,"apll2_d8" ,"apll2_d16" ,"clk26m" ,"clk26m" static const char * const a1sys_hp_parents[] = {"clk26m" ,"apll1_ck" ,"apll1_d2" ,"apll1_d4" ,"apll1_d8" ,"apll1_d3" static const char * const a2sys_hp_parents[] = {"clk26m" ,"apll2_ck" ,"apll2_d2" ,"apll2_d4" ,"apll2_d8" ,"apll2_d3" static const char * const asm_l_parents[] = {"clk26m" ,"univpll2_d4" ,"univpll2_d2" ,"syspll_d5" static const char * const i2so1_parents[] = {"clk26m" ,"apll1_ck" ,"apll2_ck" static const char * const ether_125m_parents[] = {"clk26m" ,"etherpll_125m" ,"univpll3_d2" static const char * const ether_50m_parents[] = {"clk26m" ,"etherpll_50m" ,"apll1_d3" ,"univpll3_d4" static const char * const jpgdec_parents[] = {"clk26m" ,"univpll_d3" ,"tvdpll_429m" ,"vencpll_ck" ,"syspll_d3" ,"vcodecpll_ck" ,"univpll1_d2" ,"armca35pll_400m" ,"tvdpll_429m_d2" ,"tvdpll_429m_d4" static const char * const spislv_parents[] = {"clk26m" ,"univpll2_d4" ,"univpll1_d4" ,"univpll2_d2" ,"univpll3_d2" ,"univpll1_d8" ,"univpll1_d2" ,"univpll_d5" static const char * const ether_parents[] = {"clk26m" ,"etherpll_50m" ,"univpll_d26" static const char * const di_parents[] = {"clk26m" ,"tvdpll_d2" ,"tvdpll_d4" ,"tvdpll_d8" ,"vencpll_ck" ,"vencpll_d2" ,"cvbs" ,"cvbs_d2" static const char * const tvd_parents[] = {"clk26m" ,"cvbs_d2" ,"univpll2_d8" static const char * const i2c_parents[] = {"clk26m" ,"univpll_d26" ,"univpll2_d4" ,"univpll3_d2" ,"univpll1_d4" static const char * const msdc0p_aes_parents[] = {"clk26m" ,"syspll_d2" ,"univpll_d3" ,"vcodecpll_ck" static const char * const cmsys_parents[] = {"clk26m" ,"univpll_d3" ,"syspll_d3" ,"syspll1_d2" ,"syspll2_d2" static const char * const gcpu_parents[] = {"clk26m" ,"syspll_d3" ,"syspll1_d2" ,"univpll1_d2" ,"univpll_d5" ,"univpll3_d2" ,"univpll_d3" static const char * const aud_apll1_parents[] = {"apll1" ,"clkaud_ext_i_1" static const char * const aud_apll2_parents[] = {"apll2" ,"clkaud_ext_i_2" static const char * const apll1_ref_parents[] = {"clkaud_ext_i_2" ,"clkaud_ext_i_1" ,"clki2si0_mck_i" ,"clki2si1_mck_i" ,"clki2si2_mck_i" ,"clktdmin_mclk_i" ,"clki2si2_mck_i" ,"clktdmin_mclk_i" static const char * const audull_vtx_parents[] = {"d2a_ulclk_6p5m" ,"clkaud_ext_i_0" static struct mtk_composite top_muxes[] = {/* CLK_CFG_0 */ "axi_sel" , axi_parents, 0x040, 0, 3,"mem_sel" , mem_parents, 0x040, 8, 1,"mm_sel" , mm_parents, 0x040, 24, 3, 31),/* CLK_CFG_1 */ "pwm_sel" , pwm_parents, 0x050, 0, 2, 7),"vdec_sel" , vdec_parents, 0x050, 8, 4, 15),"venc_sel" , venc_parents, 0x050, 16, 4, 23),"mfg_sel" , mfg_parents, 0x050, 24, 4, 31),/* CLK_CFG_2 */ "camtg_sel" , camtg_parents, 0x060, 0, 4, 7),"uart_sel" , uart_parents, 0x060, 8, 1, 15),"spi_sel" , spi_parents, 0x060, 16, 3, 23),"usb20_sel" , usb20_parents, 0x060, 24, 2, 31),/* CLK_CFG_3 */ "usb30_sel" , usb30_parents, 0x070, 0, 2, 7),"msdc50_0_h_sel" , msdc50_0_h_parents,"msdc50_0_sel" , msdc50_0_parents,"msdc30_1_sel" , msdc30_1_parents,/* CLK_CFG_4 */ "msdc30_2_sel" , msdc30_1_parents,"msdc30_3_sel" , msdc30_3_parents,"audio_sel" , audio_parents,"aud_intbus_sel" , aud_intbus_parents,/* CLK_CFG_5 */ "pmicspi_sel" , pmicspi_parents, 0x090, 0, 3, 7),"dpilvds1_sel" , dpilvds1_parents,"atb_sel" , atb_parents, 0x090, 16, 2, 23),"nr_sel" , nr_parents, 0x090, 24, 3, 31),/* CLK_CFG_6 */ "nfi2x_sel" , nfi2x_parents, 0x0a0, 0, 4, 7),"irda_sel" , irda_parents, 0x0a0, 8, 2, 15),"cci400_sel" , cci400_parents, 0x0a0, 16, 3, 23),"aud_1_sel" , aud_1_parents, 0x0a0, 24, 2, 31),/* CLK_CFG_7 */ "aud_2_sel" , aud_2_parents, 0x0b0, 0, 2, 7),"mem_mfg_sel" , mem_mfg_parents,"axi_mfg_sel" , axi_mfg_parents,"scam_sel" , scam_parents, 0x0b0, 24, 2, 31),/* CLK_CFG_8 */ "nfiecc_sel" , nfiecc_parents, 0x0c0, 0, 3, 7),"pe2_mac_p0_sel" , pe2_mac_p0_parents,"pe2_mac_p1_sel" , pe2_mac_p0_parents,"dpilvds_sel" , dpilvds_parents, 0x0c0, 24, 3, 31),/* CLK_CFG_9 */ "msdc50_3_h_sel" , msdc50_0_h_parents,"hdcp_sel" , hdcp_parents, 0x0d0, 8, 2, 15),"hdcp_24m_sel" , hdcp_24m_parents,"rtc_sel" , rtc_parents,/* CLK_CFG_10 */ "spinor_sel" , spinor_parents, 0x500, 0, 4, 7),"apll_sel" , apll_parents, 0x500, 8, 4, 15),"apll2_sel" , apll_parents, 0x500, 16, 4, 23),"a1sys_hp_sel" , a1sys_hp_parents,/* CLK_CFG_11 */ "a2sys_hp_sel" , a2sys_hp_parents, 0x510, 0, 3, 7),"asm_l_sel" , asm_l_parents, 0x510, 8, 2, 15),"asm_m_sel" , asm_l_parents, 0x510, 16, 2, 23),"asm_h_sel" , asm_l_parents, 0x510, 24, 2, 31),/* CLK_CFG_12 */ "i2so1_sel" , i2so1_parents, 0x520, 0, 2, 7),"i2so2_sel" , i2so1_parents, 0x520, 8, 2, 15),"i2so3_sel" , i2so1_parents, 0x520, 16, 2, 23),"tdmo0_sel" , i2so1_parents, 0x520, 24, 2, 31),/* CLK_CFG_13 */ "tdmo1_sel" , i2so1_parents, 0x530, 0, 2, 7),"i2si1_sel" , i2so1_parents, 0x530, 8, 2, 15),"i2si2_sel" , i2so1_parents, 0x530, 16, 2, 23),"i2si3_sel" , i2so1_parents, 0x530, 24, 2, 31),/* CLK_CFG_14 */ "ether_125m_sel" , ether_125m_parents,"ether_50m_sel" , ether_50m_parents,"jpgdec_sel" , jpgdec_parents, 0x540, 16, 4, 23),"spislv_sel" , spislv_parents, 0x540, 24, 3, 31),/* CLK_CFG_15 */ "ether_sel" , ether_parents, 0x550, 0, 2, 7),"cam2tg_sel" , camtg_parents, 0x550, 8, 4, 15),"di_sel" , di_parents, 0x550, 16, 3, 23),"tvd_sel" , tvd_parents, 0x550, 24, 2, 31),/* CLK_CFG_16 */ "i2c_sel" , i2c_parents, 0x560, 0, 3, 7),"pwm_infra_sel" , pwm_parents, 0x560, 8, 2, 15),"msdc0p_aes_sel" , msdc0p_aes_parents,"cmsys_sel" , cmsys_parents, 0x560, 24, 3, 31),/* CLK_CFG_17 */ "gcpu_sel" , gcpu_parents, 0x570, 0, 3, 7),/* CLK_AUDDIV_4 */ "aud_apll1_sel" , aud_apll1_parents, 0x134, 0, 1),"aud_apll2_sel" , aud_apll2_parents, 0x134, 1, 1),"audull_vtx_sel" , audull_vtx_parents,"apll1_ref_sel" , apll1_ref_parents, 0x134, 4, 3),"apll2_ref_sel" , apll1_ref_parents, 0x134, 7, 3),static const char * const mcu_mp0_parents[] = {"clk26m" ,"armca35pll_ck" ,"f_mp0_pll1_ck" ,"f_mp0_pll2_ck" static const char * const mcu_mp2_parents[] = {"clk26m" ,"armca72pll_ck" ,"f_big_pll1_ck" ,"f_big_pll2_ck" static const char * const mcu_bus_parents[] = {"clk26m" ,"cci400_sel" ,"f_bus_pll1_ck" ,"f_bus_pll2_ck" static struct mtk_composite mcu_muxes[] = {/* mp0_pll_divider_cfg */ "mcu_mp0_sel" , mcu_mp0_parents, 0x7A0,/* mp2_pll_divider_cfg */ "mcu_mp2_sel" , mcu_mp2_parents, 0x7A8,/* bus_pll_divider_cfg */ "mcu_bus_sel" , mcu_bus_parents, 0x7C0,static const struct mtk_clk_divider top_adj_divs[] = {"apll_div0" , "i2so1_sel" , 0x124, 0, 8),"apll_div1" , "i2so2_sel" , 0x124, 8, 8),"apll_div2" , "i2so3_sel" , 0x124, 16, 8),"apll_div3" , "tdmo0_sel" , 0x124, 24, 8),"apll_div4" , "tdmo1_sel" , 0x128, 0, 8),"apll_div5" , "i2si1_sel" , 0x128, 8, 8),"apll_div6" , "i2si2_sel" , 0x128, 16, 8),"apll_div7" , "i2si3_sel" , 0x128, 24, 8),static const struct mtk_gate_regs top0_cg_regs = {static const struct mtk_gate_regs top1_cg_regs = {#define GATE_TOP0(_id, _name, _parent, _shift) \#define GATE_TOP1(_id, _name, _parent, _shift) \static const struct mtk_gate top_clks[] = {/* TOP0 */ "apll_div_pdn0" , "i2so1_sel" , 0),"apll_div_pdn1" , "i2so2_sel" , 1),"apll_div_pdn2" , "i2so3_sel" , 2),"apll_div_pdn3" , "tdmo0_sel" , 3),"apll_div_pdn4" , "tdmo1_sel" , 4),"apll_div_pdn5" , "i2si1_sel" , 5),"apll_div_pdn6" , "i2si2_sel" , 6),"apll_div_pdn7" , "i2si3_sel" , 7),/* TOP1 */ "nfi2x_en" , "nfi2x_sel" , 0),"nfiecc_en" , "nfiecc_sel" , 1),"nfi1x_ck_en" , "nfi2x_sel" , 2),static const struct mtk_gate_regs infra_cg_regs = {#define GATE_INFRA(_id, _name, _parent, _shift) \static const struct mtk_gate infra_clks[] = {"infra_dbgclk" , "axi_sel" , 0),"infra_gce" , "axi_sel" , 6),"infra_m4u" , "mem_sel" , 8),"infra_kp" , "axi_sel" , 16),"infra_ao_spi0" , "spi_sel" , 24),"infra_ao_spi1" , "spislv_sel" , 25),"infra_ao_uart5" , "axi_sel" , 26),static const struct mtk_gate_regs peri0_cg_regs = {static const struct mtk_gate_regs peri1_cg_regs = {static const struct mtk_gate_regs peri2_cg_regs = {#define GATE_PERI0(_id, _name, _parent, _shift) \#define GATE_PERI1(_id, _name, _parent, _shift) \#define GATE_PERI2(_id, _name, _parent, _shift) \static const struct mtk_gate peri_clks[] = {/* PERI0 */ "per_nfi" , "axi_sel" , 0),"per_therm" , "axi_sel" , 1),"per_pwm0" , "pwm_sel" , 2),"per_pwm1" , "pwm_sel" , 3),"per_pwm2" , "pwm_sel" , 4),"per_pwm3" , "pwm_sel" , 5),"per_pwm4" , "pwm_sel" , 6),"per_pwm5" , "pwm_sel" , 7),"per_pwm6" , "pwm_sel" , 8),"per_pwm7" , "pwm_sel" , 9),"per_pwm" , "pwm_sel" , 10),"per_ap_dma" , "axi_sel" , 13),"per_msdc30_0" , "msdc50_0_sel" , 14),"per_msdc30_1" , "msdc30_1_sel" , 15),"per_msdc30_2" , "msdc30_2_sel" , 16),"per_msdc30_3" , "msdc30_3_sel" , 17),"per_uart0" , "uart_sel" , 20),"per_uart1" , "uart_sel" , 21),"per_uart2" , "uart_sel" , 22),"per_uart3" , "uart_sel" , 23),"per_i2c0" , "axi_sel" , 24),"per_i2c1" , "axi_sel" , 25),"per_i2c2" , "axi_sel" , 26),"per_i2c3" , "axi_sel" , 27),"per_i2c4" , "axi_sel" , 28),"per_auxadc" , "ltepll_fs26m" , 29),"per_spi0" , "spi_sel" , 30),/* PERI1 */ "per_spi" , "spinor_sel" , 1),"per_i2c5" , "axi_sel" , 3),"per_spi2" , "spi_sel" , 5),"per_spi3" , "spi_sel" , 6),"per_spi5" , "spi_sel" , 8),"per_uart4" , "uart_sel" , 9),"per_sflash" , "uart_sel" , 11),"per_gmac" , "uart_sel" , 12),"per_pcie0" , "uart_sel" , 14),"per_pcie1" , "uart_sel" , 15),"per_gmac_pclk" , "uart_sel" , 16),/* PERI2 */ "per_msdc50_0_en" , "msdc50_0_sel" , 0),"per_msdc30_1_en" , "msdc30_1_sel" , 1),"per_msdc30_2_en" , "msdc30_2_sel" , 2),"per_msdc30_3_en" , "msdc30_3_sel" , 3),"per_msdc50_0_h" , "msdc50_0_h_sel" , 4),"per_msdc50_3_h" , "msdc50_3_h_sel" , 5),"per_msdc30_0_q" , "axi_sel" , 6),"per_msdc30_3_q" , "mem_sel" , 7),static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };static const struct mtk_clk_rst_desc clk_rst_desc[] = {/* infra */ /* peri */ static const struct mtk_clk_desc topck_desc = {static const struct mtk_clk_desc mcu_desc = {static const struct mtk_clk_desc infra_desc = {static const struct mtk_clk_desc peri_desc = {static const struct of_device_id of_match_clk_mt2712[] = {"mediatek,mt2712-infracfg" , .data = &infra_desc },"mediatek,mt2712-mcucfg" , .data = &mcu_desc },"mediatek,mt2712-pericfg" , .data = &peri_desc, },"mediatek,mt2712-topckgen" , .data = &topck_desc },/* sentinel */ } static struct platform_driver clk_mt2712_drv = {"clk-mt2712" ,"MediaTek MT2712 main clocks driver" );"GPL" );
Messung V0.5 C=96 H=100 G=97
¤ Dauer der Verarbeitung: 0.7 Sekunden
¤ *© Formatika GbR, Deutschland
