// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022 Collabora Ltd. * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #include <dt-bindings/clock/mediatek,mt6795-clk.h>#include <linux/module.h>#include <linux/platform_device.h>#include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" /* * For some clocks, we don't care what their actual rates are. And these * clocks may change their rate on different products or different scenarios. * So we model these clocks' rate as 0, to denote it's not an actual rate. #define DUMMY_RATE 0#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \static DEFINE_SPINLOCK(mt6795_top_clk_lock);static const char * const aud_1_parents[] = {"clk26m" ,"apll1_ck" ,"univpll2_d4" ,"univpll2_d8" static const char * const aud_2_parents[] = {"clk26m" ,"apll2_ck" ,"univpll2_d4" ,"univpll2_d8" static const char * const aud_intbus_parents[] = {"clk26m" ,"syspll1_d4" ,"syspll4_d2" ,"univpll3_d2" ,"univpll2_d8" ,"dmpll_d4" ,"dmpll_d8" static const char * const audio_parents[] = {"clk26m" ,"syspll3_d4" ,"syspll4_d4" ,"syspll1_d16" static const char * const axi_mfg_in_parents[] = {"clk26m" ,"axi_sel" ,"dmpll_d2" static const char * const axi_parents[] = {"clk26m" ,"syspll1_d2" ,"syspll_d5" ,"syspll1_d4" ,"univpll_d5" ,"univpll2_d2" ,"dmpll_d2" ,"dmpll_d4" static const char * const camtg_parents[] = {"clk26m" ,"univpll_d26" ,"univpll2_d2" ,"syspll3_d2" ,"syspll3_d4" ,"univpll1_d4" ,"dmpll_d8" static const char * const cci400_parents[] = {"clk26m" ,"vencpll_ck" ,"clk26m" ,"clk26m" ,"univpll_d2" ,"syspll_d2" ,"msdcpll_ck" ,"dmpll_ck" static const char * const ddrphycfg_parents[] = {"clk26m" ,"syspll1_d8" static const char * const dpi0_parents[] = {"clk26m" ,"tvdpll_d2" ,"tvdpll_d4" ,"clk26m" ,"clk26m" ,"tvdpll_d8" ,"tvdpll_d16" static const char * const i2s0_m_ck_parents[] = {"apll1_div1" ,"apll2_div1" static const char * const i2s1_m_ck_parents[] = {"apll1_div2" ,"apll2_div2" static const char * const i2s2_m_ck_parents[] = {"apll1_div3" ,"apll2_div3" static const char * const i2s3_m_ck_parents[] = {"apll1_div4" ,"apll2_div4" static const char * const i2s3_b_ck_parents[] = {"apll1_div5" ,"apll2_div5" static const char * const irda_parents[] = {"clk26m" ,"univpll2_d4" ,"syspll2_d4" ,"dmpll_d8" ,static const char * const mem_mfg_in_parents[] = {"clk26m" ,"mmpll_ck" ,"dmpll_ck" static const char * const mem_parents[] = {"clk26m" ,"dmpll_ck" static const char * const mfg_parents[] = {"clk26m" ,"mmpll_ck" ,"dmpll_ck" ,"clk26m" ,"clk26m" ,"clk26m" ,"clk26m" ,"clk26m" ,"clk26m" ,"syspll_d3" ,"syspll1_d2" ,"syspll_d5" ,"univpll_d3" ,"univpll1_d2" ,"univpll_d5" ,"univpll2_d2" static const char * const mm_parents[] = {"clk26m" ,"vencpll_d2" ,"syspll_d3" ,"syspll1_d2" ,"syspll_d5" ,"syspll1_d4" ,"univpll1_d2" ,"univpll2_d2" ,"dmpll_d2" static const char * const mjc_parents[] = {"clk26m" ,"univpll_d3" ,"vcodecpll_ck" ,"tvdpll_445p5m" ,"vencpll_d2" ,"syspll_d3" ,"univpll1_d2" ,"syspll_d5" ,"syspll1_d2" ,"univpll_d5" ,"univpll2_d2" ,"dmpll_ck" static const char * const msdc50_0_h_parents[] = {"clk26m" ,"syspll1_d2" ,"syspll2_d2" ,"syspll4_d2" ,"univpll_d5" ,"univpll1_d4" static const char * const msdc50_0_parents[] = {"clk26m" ,"msdcpll_ck" ,"msdcpll_d2" ,"univpll1_d4" ,"syspll2_d2" ,"syspll_d7" ,"msdcpll_d4" ,"vencpll_d4" ,"tvdpll_ck" ,"univpll_d2" ,"univpll1_d2" ,"mmpll_ck" static const char * const msdc30_1_parents[] = {"clk26m" ,"univpll2_d2" ,"msdcpll_d4" ,"univpll1_d4" ,"syspll2_d2" ,"syspll_d7" ,"univpll_d7" ,"vencpll_d4" static const char * const msdc30_2_parents[] = {"clk26m" ,"univpll2_d2" ,"msdcpll_d4" ,"univpll1_d4" ,"syspll2_d2" ,"syspll_d7" ,"univpll_d7" ,"vencpll_d2" static const char * const msdc30_3_parents[] = {"clk26m" ,"univpll2_d2" ,"msdcpll_d4" ,"univpll1_d4" ,"syspll2_d2" ,"syspll_d7" ,"univpll_d7" ,"vencpll_d4" static const char * const pmicspi_parents[] = {"clk26m" ,"syspll1_d8" ,"syspll3_d4" ,"syspll1_d16" ,"univpll3_d4" ,"univpll_d26" ,"dmpll_d8" ,"dmpll_d16" static const char * const pwm_parents[] = {"clk26m" ,"univpll2_d4" ,"univpll3_d2" ,"univpll1_d4" static const char * const scam_parents[] = {"clk26m" ,"syspll3_d2" ,"univpll2_d4" ,"dmpll_d4" static const char * const scp_parents[] = {"clk26m" ,"syspll1_d2" ,"univpll_d5" ,"syspll_d5" ,"dmpll_d2" ,"dmpll_d4" static const char * const spi_parents[] = {"clk26m" ,"syspll3_d2" ,"syspll1_d4" ,"syspll4_d2" ,"univpll3_d2" ,"univpll2_d4" ,"univpll1_d8" static const char * const uart_parents[] = {"clk26m" ,"univpll2_d8" static const char * const usb20_parents[] = {"clk26m" ,"univpll1_d8" ,"univpll3_d4" static const char * const usb30_parents[] = {"clk26m" ,"univpll3_d2" ,"usb_syspll_125m" ,"univpll2_d4" static const char * const vdec_parents[] = {"clk26m" ,"vcodecpll_ck" ,"tvdpll_445p5m" ,"univpll_d3" ,"vencpll_d2" ,"syspll_d3" ,"univpll1_d2" ,"mmpll_d2" ,"dmpll_d2" ,"dmpll_d4" static const char * const venc_parents[] = {"clk26m" ,"vcodecpll_ck" ,"tvdpll_445p5m" ,"univpll_d3" ,"vencpll_d2" ,"syspll_d3" ,"univpll1_d2" ,"univpll2_d2" ,"dmpll_d2" ,"dmpll_d4" static const struct mtk_fixed_clk fixed_clks[] = {"adsys_26m" , "clk26m" , 26 * MHZ),"clkph_mck_o" , "clk26m" , DUMMY_RATE),"usb_syspll_125m" , "clk26m" , 125 * MHZ),"dsi0_dig" , "clk26m" , DUMMY_RATE),"dsi1_dig" , "clk26m" , DUMMY_RATE),static const struct mtk_fixed_factor top_divs[] = {"armca53pll_754m" , "clk26m" , 1, 2),"armca53pll_502m" , "clk26m" , 1, 3),"main_h546m" , "mainpll" , 1, 2, 0),"main_h364m" , "mainpll" , 1, 3, 0),"main_h218p4m" , "mainpll" , 1, 5, 0),"main_h156m" , "mainpll" , 1, 7, 0),"tvdpll_445p5m" , "tvdpll" , 1, 4),"tvdpll_594m" , "tvdpll" , 1, 3),"univ_624m" , "univpll" , 1, 2, 0),"univ_416m" , "univpll" , 1, 3, 0),"univ_249p6m" , "univpll" , 1, 5, 0),"univ_178p3m" , "univpll" , 1, 7, 0),"univ_48m" , "univpll" , 1, 26, 0),"clkrtc_ext" , "clk32k" , 1, 1),"clkrtc_int" , "clk26m" , 1, 793),"fpc_ck" , "clk26m" , 1, 1),"hdmitxpll_d2" , "clk26m" , 1, 2),"hdmitxpll_d3" , "clk26m" , 1, 3),"armca53pll_d2" , "clk26m" , 1, 1),"armca53pll_d3" , "clk26m" , 1, 1),"apll1_ck" , "apll1" , 1, 1),"apll2_ck" , "apll2" , 1, 1),"dmpll_ck" , "clkph_mck_o" , 1, 1),"dmpll_d2" , "clkph_mck_o" , 1, 2),"dmpll_d4" , "clkph_mck_o" , 1, 4),"dmpll_d8" , "clkph_mck_o" , 1, 8),"dmpll_d16" , "clkph_mck_o" , 1, 16),"mmpll_ck" , "mmpll" , 1, 1),"mmpll_d2" , "mmpll" , 1, 2),"msdcpll_ck" , "msdcpll" , 1, 1),"msdcpll_d2" , "msdcpll" , 1, 2),"msdcpll_d4" , "msdcpll" , 1, 4),"msdcpll2_ck" , "msdcpll2" , 1, 1),"msdcpll2_d2" , "msdcpll2" , 1, 2),"msdcpll2_d4" , "msdcpll2" , 1, 4),"syspll_d2" , "main_h546m" , 1, 1, 0),"syspll1_d2" , "main_h546m" , 1, 2, 0),"syspll1_d4" , "main_h546m" , 1, 4, 0),"syspll1_d8" , "main_h546m" , 1, 8, 0),"syspll1_d16" , "main_h546m" , 1, 16, 0),"syspll_d3" , "main_h364m" , 1, 1, 0),"syspll2_d2" , "main_h364m" , 1, 2, 0),"syspll2_d4" , "main_h364m" , 1, 4, 0),"syspll_d5" , "main_h218p4m" , 1, 1, 0),"syspll3_d2" , "main_h218p4m" , 1, 2, 0),"syspll3_d4" , "main_h218p4m" , 1, 4, 0),"syspll_d7" , "main_h156m" , 1, 1, 0),"syspll4_d2" , "main_h156m" , 1, 2, 0),"syspll4_d4" , "main_h156m" , 1, 4, 0),"tvdpll_ck" , "tvdpll_594m" , 1, 1),"tvdpll_d2" , "tvdpll_594m" , 1, 2),"tvdpll_d4" , "tvdpll_594m" , 1, 4),"tvdpll_d8" , "tvdpll_594m" , 1, 8),"tvdpll_d16" , "tvdpll_594m" , 1, 16),"univpll_d2" , "univ_624m" , 1, 1, 0),"univpll1_d2" , "univ_624m" , 1, 2, 0),"univpll1_d4" , "univ_624m" , 1, 4, 0),"univpll1_d8" , "univ_624m" , 1, 8, 0),"univpll_d3" , "univ_416m" , 1, 1, 0),"univpll2_d2" , "univ_416m" , 1, 2, 0),"univpll2_d4" , "univ_416m" , 1, 4, 0),"univpll2_d8" , "univ_416m" , 1, 8, 0),"univpll_d5" , "univ_249p6m" , 1, 1, 0),"univpll3_d2" , "univ_249p6m" , 1, 2, 0),"univpll3_d4" , "univ_249p6m" , 1, 4, 0),"univpll3_d8" , "univ_249p6m" , 1, 8, 0),"univpll_d7" , "univ_178p3m" , 1, 1, 0),"univpll_d26" , "univ_48m" , 1, 1, 0),"univpll_d52" , "univ_48m" , 1, 2, 0),"vcodecpll_ck" , "vcodecpll" , 1, 3),"vcodecpll_370p5" , "vcodecpll" , 1, 4),"vencpll_ck" , "vencpll" , 1, 1),"vencpll_d2" , "vencpll" , 1, 2),"vencpll_d4" , "vencpll" , 1, 4),static const struct mtk_mux top_muxes[] = {/* CLK_CFG_0 */ "axi_sel" , axi_parents,"mem_sel" , mem_parents,"ddrphycfg_sel" , ddrphycfg_parents,"mm_sel" , mm_parents, 0x40, 24, 3, 31, 0),/* CLK_CFG_1 */ "pwm_sel" , pwm_parents, 0x50, 0, 2, 7, 0),"vdec_sel" , vdec_parents, 0x50, 8, 4, 15, 0),"venc_sel" , venc_parents, 0x50, 16, 4, 23, 0),"mfg_sel" , mfg_parents, 0x50, 24, 4, 31, 0),/* CLK_CFG_2 */ "camtg_sel" , camtg_parents, 0x60, 0, 3, 7, 0),"uart_sel" , uart_parents, 0x60, 8, 1, 15, 0),"spi_sel" , spi_parents, 0x60, 16, 3, 23, 0),"usb20_sel" , usb20_parents, 0x60, 24, 2, 31, 0),/* CLK_CFG_3 */ "usb30_sel" , usb30_parents, 0x70, 0, 2, 7, 0),"msdc50_0_h_sel" , msdc50_0_h_parents,"msdc50_0_sel" , msdc50_0_parents, 0x70, 16, 4, 23, 0),"msdc30_1_sel" , msdc30_1_parents, 0x70, 24, 3, 31, 0),/* CLK_CFG_4 */ "msdc30_2_sel" , msdc30_2_parents, 0x80, 0, 3, 7, 0),"msdc30_3_sel" , msdc30_3_parents, 0x80, 8, 3, 15, 0),"audio_sel" , audio_parents, 0x80, 16, 2, 23, 0),"aud_intbus_sel" , aud_intbus_parents,/* CLK_CFG_5 */ "pmicspi_sel" , pmicspi_parents, 0x90, 0, 3, 5, 0),"scp_sel" , scp_parents, 0x90, 8, 3, 15, 0),"mjc_sel" , mjc_parents, 0x90, 24, 4, 31, 0),/* CLK_CFG_6 */ /* * The dpi0_sel clock should not propagate rate changes to its parent * clock so the dpi driver can have full control over PLL and divider. "dpi0_sel" , dpi0_parents, 0xa0, 0, 3, 7, 0),"irda_sel" , irda_parents, 0xa0, 8, 2, 15, 0),"cci400_sel" , cci400_parents,"aud_1_sel" , aud_1_parents, 0xa0, 24, 2, 31, 0),/* CLK_CFG_7 */ "aud_2_sel" , aud_2_parents, 0xb0, 0, 2, 7, 0),"mem_mfg_in_sel" , mem_mfg_in_parents,"axi_mfg_in_sel" , axi_mfg_in_parents,"scam_sel" , scam_parents, 0xb0, 24, 2, 31, 0),static struct mtk_composite top_aud_divs[] = {"i2s0_m_ck_sel" , i2s0_m_ck_parents, 0x120, 4, 1),"i2s1_m_ck_sel" , i2s1_m_ck_parents, 0x120, 5, 1),"i2s2_m_ck_sel" , i2s2_m_ck_parents, 0x120, 6, 1),"i2s3_m_ck_sel" , i2s3_m_ck_parents, 0x120, 7, 1),"i2s3_b_ck_sel" , i2s3_b_ck_parents, 0x120, 8, 1),"apll1_div0" , "aud_1_sel" , 0x12c, 8, 0x120, 4, 24),"apll1_div1" , "aud_1_sel" , 0x12c, 9, 0x124, 8, 0),"apll1_div2" , "aud_1_sel" , 0x12c, 10, 0x124, 8, 8),"apll1_div3" , "aud_1_sel" , 0x12c, 11, 0x124, 8, 16),"apll1_div4" , "aud_1_sel" , 0x12c, 12, 0x124, 8, 24),"apll1_div5" , "apll1_div4" , 0x12c, 13, 0x12c, 4, 0),"apll2_div0" , "aud_2_sel" , 0x12c, 16, 0x120, 4, 28),"apll2_div1" , "aud_2_sel" , 0x12c, 17, 0x128, 8, 0),"apll2_div2" , "aud_2_sel" , 0x12c, 18, 0x128, 8, 8),"apll2_div3" , "aud_2_sel" , 0x12c, 19, 0x128, 8, 16),"apll2_div4" , "aud_2_sel" , 0x12c, 20, 0x128, 8, 24),"apll2_div5" , "apll2_div4" , 0x12c, 21, 0x12c, 4, 4),static const struct mtk_clk_desc topck_desc = {static const struct of_device_id of_match_clk_mt6795_topckgen[] = {"mediatek,mt6795-topckgen" , .data = &topck_desc },/* sentinel */ } static struct platform_driver clk_mt6795_topckgen_drv = {"clk-mt6795-topckgen" ,"MediaTek MT6795 topckgen clocks driver" );"GPL" );
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