// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao <jamesjj.liao@mediatek.com> #include <linux/clk.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/platform_device.h>#include <linux/slab.h>#include <linux/mfd/syscon.h>#include <dt-bindings/clock/mt8135-clk.h>#include "clk-gate.h" #include "clk-mtk.h" #include "clk-pll.h" static DEFINE_SPINLOCK(mt8135_clk_lock);static const struct mtk_fixed_factor top_divs[] = {"top_divs_dummy" , "clk_null" , 1, 1),"dsi0_lntc_dsiclk" , "clk_null" , 1, 1),"hdmitx_clkdig_cts" , "clk_null" , 1, 1),"clkph_mck" , "clk_null" , 1, 1),"cpum_tck_in" , "clk_null" , 1, 1),"mainpll_806m" , "mainpll" , 1, 2),"mainpll_537p3m" , "mainpll" , 1, 3),"mainpll_322p4m" , "mainpll" , 1, 5),"mainpll_230p3m" , "mainpll" , 1, 7),"univpll_624m" , "univpll" , 1, 2),"univpll_416m" , "univpll" , 1, 3),"univpll_249p6m" , "univpll" , 1, 5),"univpll_178p3m" , "univpll" , 1, 7),"univpll_48m" , "univpll" , 1, 26),"mmpll_d2" , "mmpll" , 1, 2),"mmpll_d3" , "mmpll" , 1, 3),"mmpll_d5" , "mmpll" , 1, 5),"mmpll_d7" , "mmpll" , 1, 7),"mmpll_d4" , "mmpll_d2" , 1, 2),"mmpll_d6" , "mmpll_d3" , 1, 2),"syspll_d2" , "mainpll_806m" , 1, 1),"syspll_d4" , "mainpll_806m" , 1, 2),"syspll_d6" , "mainpll_806m" , 1, 3),"syspll_d8" , "mainpll_806m" , 1, 4),"syspll_d10" , "mainpll_806m" , 1, 5),"syspll_d12" , "mainpll_806m" , 1, 6),"syspll_d16" , "mainpll_806m" , 1, 8),"syspll_d24" , "mainpll_806m" , 1, 12),"syspll_d3" , "mainpll_537p3m" , 1, 1),"syspll_d2p5" , "mainpll_322p4m" , 2, 1),"syspll_d5" , "mainpll_322p4m" , 1, 1),"syspll_d3p5" , "mainpll_230p3m" , 2, 1),"univpll1_d2" , "univpll_624m" , 1, 2),"univpll1_d4" , "univpll_624m" , 1, 4),"univpll1_d6" , "univpll_624m" , 1, 6),"univpll1_d8" , "univpll_624m" , 1, 8),"univpll1_d10" , "univpll_624m" , 1, 10),"univpll2_d2" , "univpll_416m" , 1, 2),"univpll2_d4" , "univpll_416m" , 1, 4),"univpll2_d6" , "univpll_416m" , 1, 6),"univpll2_d8" , "univpll_416m" , 1, 8),"univpll_d3" , "univpll_416m" , 1, 1),"univpll_d5" , "univpll_249p6m" , 1, 1),"univpll_d7" , "univpll_178p3m" , 1, 1),"univpll_d10" , "univpll_249p6m" , 1, 2),"univpll_d26" , "univpll_48m" , 1, 1),"apll_ck" , "audpll" , 1, 1),"apll_d4" , "audpll" , 1, 4),"apll_d8" , "audpll" , 1, 8),"apll_d16" , "audpll" , 1, 16),"apll_d24" , "audpll" , 1, 24),"lvdspll_d2" , "lvdspll" , 1, 2),"lvdspll_d4" , "lvdspll" , 1, 4),"lvdspll_d8" , "lvdspll" , 1, 8),"lvdstx_clkdig_cts" , "lvdspll" , 1, 1),"vpll_dpix_ck" , "lvdspll" , 1, 1),"tvhdmi_h_ck" , "tvdpll" , 1, 1),"hdmitx_clkdig_d2" , "hdmitx_clkdig_cts" , 1, 2),"hdmitx_clkdig_d3" , "hdmitx_clkdig_cts" , 1, 3),"tvhdmi_d2" , "tvhdmi_h_ck" , 1, 2),"tvhdmi_d4" , "tvhdmi_h_ck" , 1, 4),"mempll_mck_d4" , "clkph_mck" , 1, 4),static const char * const axi_parents[] = {"clk26m" ,"syspll_d3" ,"syspll_d4" ,"syspll_d6" ,"univpll_d5" ,"univpll2_d2" ,"syspll_d3p5" static const char * const smi_parents[] = {"clk26m" ,"clkph_mck" ,"syspll_d2p5" ,"syspll_d3" ,"syspll_d8" ,"univpll_d5" ,"univpll1_d2" ,"univpll1_d6" ,"mmpll_d3" ,"mmpll_d4" ,"mmpll_d5" ,"mmpll_d6" ,"mmpll_d7" ,"vdecpll" ,"lvdspll" static const char * const mfg_parents[] = {"clk26m" ,"univpll1_d4" ,"syspll_d2" ,"syspll_d2p5" ,"syspll_d3" ,"univpll_d5" ,"univpll1_d2" ,"mmpll_d2" ,"mmpll_d3" ,"mmpll_d4" ,"mmpll_d5" ,"mmpll_d6" ,"mmpll_d7" static const char * const irda_parents[] = {"clk26m" ,"univpll2_d8" ,"univpll1_d6" static const char * const cam_parents[] = {"clk26m" ,"syspll_d3" ,"syspll_d3p5" ,"syspll_d4" ,"univpll_d5" ,"univpll2_d2" ,"univpll_d7" ,"univpll1_d4" static const char * const aud_intbus_parents[] = {"clk26m" ,"syspll_d6" ,"univpll_d10" static const char * const jpg_parents[] = {"clk26m" ,"syspll_d5" ,"syspll_d4" ,"syspll_d3" ,"univpll_d7" ,"univpll2_d2" ,"univpll_d5" static const char * const disp_parents[] = {"clk26m" ,"syspll_d3p5" ,"syspll_d3" ,"univpll2_d2" ,"univpll_d5" ,"univpll1_d2" ,"lvdspll" ,"vdecpll" static const char * const msdc30_parents[] = {"clk26m" ,"syspll_d6" ,"syspll_d5" ,"univpll1_d4" ,"univpll2_d4" ,"msdcpll" static const char * const usb20_parents[] = {"clk26m" ,"univpll2_d6" ,"univpll1_d10" static const char * const venc_parents[] = {"clk26m" ,"syspll_d3" ,"syspll_d8" ,"univpll_d5" ,"univpll1_d6" ,"mmpll_d4" ,"mmpll_d5" ,"mmpll_d6" static const char * const spi_parents[] = {"clk26m" ,"syspll_d6" ,"syspll_d8" ,"syspll_d10" ,"univpll1_d6" ,"univpll1_d8" static const char * const uart_parents[] = {"clk26m" ,"univpll2_d8" static const char * const mem_parents[] = {"clk26m" ,"clkph_mck" static const char * const camtg_parents[] = {"clk26m" ,"univpll_d26" ,"univpll1_d6" ,"syspll_d16" ,"syspll_d8" static const char * const audio_parents[] = {"clk26m" ,"syspll_d24" static const char * const fix_parents[] = {"rtc32k" ,"clk26m" ,"univpll_d5" ,"univpll_d7" ,"univpll1_d2" ,"univpll1_d4" ,"univpll1_d6" ,"univpll1_d8" static const char * const vdec_parents[] = {"clk26m" ,"vdecpll" ,"clkph_mck" ,"syspll_d2p5" ,"syspll_d3" ,"syspll_d3p5" ,"syspll_d4" ,"syspll_d5" ,"syspll_d6" ,"syspll_d8" ,"univpll1_d2" ,"univpll2_d2" ,"univpll_d7" ,"univpll_d10" ,"univpll2_d4" ,"lvdspll" static const char * const ddrphycfg_parents[] = {"clk26m" ,"axi_sel" ,"syspll_d12" static const char * const dpilvds_parents[] = {"clk26m" ,"lvdspll" ,"lvdspll_d2" ,"lvdspll_d4" ,"lvdspll_d8" static const char * const pmicspi_parents[] = {"clk26m" ,"univpll2_d6" ,"syspll_d8" ,"syspll_d10" ,"univpll1_d10" ,"mempll_mck_d4" ,"univpll_d26" ,"syspll_d24" static const char * const smi_mfg_as_parents[] = {"clk26m" ,"smi_sel" ,"mfg_sel" ,"mem_sel" static const char * const gcpu_parents[] = {"clk26m" ,"syspll_d4" ,"univpll_d7" ,"syspll_d5" ,"syspll_d6" static const char * const dpi1_parents[] = {"clk26m" ,"tvhdmi_h_ck" ,"tvhdmi_d2" ,"tvhdmi_d4" static const char * const cci_parents[] = {"clk26m" ,"mainpll_537p3m" ,"univpll_d3" ,"syspll_d2p5" ,"syspll_d3" ,"syspll_d5" static const char * const apll_parents[] = {"clk26m" ,"apll_ck" ,"apll_d4" ,"apll_d8" ,"apll_d16" ,"apll_d24" static const char * const hdmipll_parents[] = {"clk26m" ,"hdmitx_clkdig_cts" ,"hdmitx_clkdig_d2" ,"hdmitx_clkdig_d3" static const struct mtk_composite top_muxes[] = {/* CLK_CFG_0 */ "axi_sel" , axi_parents,"smi_sel" , smi_parents, 0x0140, 8, 4, 15),"mfg_sel" , mfg_parents, 0x0140, 16, 4, 23),"irda_sel" , irda_parents, 0x0140, 24, 2, 31),/* CLK_CFG_1 */ "cam_sel" , cam_parents, 0x0144, 0, 3, 7),"aud_intbus_sel" , aud_intbus_parents,"jpg_sel" , jpg_parents, 0x0144, 16, 3, 23),"disp_sel" , disp_parents, 0x0144, 24, 3, 31),/* CLK_CFG_2 */ "msdc30_1_sel" , msdc30_parents, 0x0148, 0, 3, 7),"msdc30_2_sel" , msdc30_parents, 0x0148, 8, 3, 15),"msdc30_3_sel" , msdc30_parents, 0x0148, 16, 3, 23),"msdc30_4_sel" , msdc30_parents, 0x0148, 24, 3, 31),/* CLK_CFG_3 */ "usb20_sel" , usb20_parents, 0x014c, 0, 2, 7),/* CLK_CFG_4 */ "venc_sel" , venc_parents, 0x0150, 8, 3, 15),"spi_sel" , spi_parents, 0x0150, 16, 3, 23),"uart_sel" , uart_parents, 0x0150, 24, 2, 31),/* CLK_CFG_6 */ "mem_sel" , mem_parents, 0x0158, 0, 2, 7),"camtg_sel" , camtg_parents, 0x0158, 8, 3, 15),"audio_sel" , audio_parents, 0x0158, 24, 2, 31),/* CLK_CFG_7 */ "fix_sel" , fix_parents, 0x015c, 0, 3, 7),"vdec_sel" , vdec_parents, 0x015c, 8, 4, 15),"ddrphycfg_sel" , ddrphycfg_parents,"dpilvds_sel" , dpilvds_parents, 0x015c, 24, 3, 31),/* CLK_CFG_8 */ "pmicspi_sel" , pmicspi_parents, 0x0164, 0, 3, 7),"msdc30_0_sel" , msdc30_parents, 0x0164, 8, 3, 15),"smi_mfg_as_sel" , smi_mfg_as_parents,"gcpu_sel" , gcpu_parents, 0x0164, 24, 3, 31),/* CLK_CFG_9 */ "dpi1_sel" , dpi1_parents, 0x0168, 0, 2, 7),"cci_sel" , cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL),"apll_sel" , apll_parents, 0x0168, 16, 3, 23),"hdmipll_sel" , hdmipll_parents, 0x0168, 24, 2, 31),static const struct mtk_gate_regs infra_cg_regs = {#define GATE_ICG(_id, _name, _parent, _shift) \#define GATE_ICG_AO(_id, _name, _parent, _shift) \static const struct mtk_gate infra_clks[] = {"infra_dummy" ),"pmic_wrap_ck" , "axi_sel" , 23),"pmicspi_ck" , "pmicspi_sel" , 22),"ccif1_ap_ctrl" , "axi_sel" , 21),"ccif0_ap_ctrl" , "axi_sel" , 20),"kp_ck" , "axi_sel" , 16),"cpum_ck" , "cpum_tck_in" , 15),"m4u_ck" , "mem_sel" , 8),"mfgaxi_ck" , "axi_sel" , 7),"devapc_ck" , "axi_sel" , 6),"audio_ck" , "aud_intbus_sel" , 5),"mfg_bus_ck" , "axi_sel" , 2),"smi_ck" , "smi_sel" , 1),"dbgclk_ck" , "axi_sel" , 0),static const struct mtk_gate_regs peri0_cg_regs = {static const struct mtk_gate_regs peri1_cg_regs = {#define GATE_PERI0(_id, _name, _parent, _shift) \#define GATE_PERI1(_id, _name, _parent, _shift) \static const struct mtk_gate peri_gates[] = {"peri_dummy" ),/* PERI0 */ "i2c5_ck" , "axi_sel" , 31),"i2c4_ck" , "axi_sel" , 30),"i2c3_ck" , "axi_sel" , 29),"i2c2_ck" , "axi_sel" , 28),"i2c1_ck" , "axi_sel" , 27),"i2c0_ck" , "axi_sel" , 26),"uart3_ck" , "axi_sel" , 25),"uart2_ck" , "axi_sel" , 24),"uart1_ck" , "axi_sel" , 23),"uart0_ck" , "axi_sel" , 22),"irda_ck" , "irda_sel" , 21),"nli_ck" , "axi_sel" , 20),"md_hif_ck" , "axi_sel" , 19),"ap_hif_ck" , "axi_sel" , 18),"msdc30_3_ck" , "msdc30_4_sel" , 17),"msdc30_2_ck" , "msdc30_3_sel" , 16),"msdc30_1_ck" , "msdc30_2_sel" , 15),"msdc20_2_ck" , "msdc30_1_sel" , 14),"msdc20_1_ck" , "msdc30_0_sel" , 13),"ap_dma_ck" , "axi_sel" , 12),"usb1_ck" , "usb20_sel" , 11),"usb0_ck" , "usb20_sel" , 10),"pwm_ck" , "axi_sel" , 9),"pwm7_ck" , "axi_sel" , 8),"pwm6_ck" , "axi_sel" , 7),"pwm5_ck" , "axi_sel" , 6),"pwm4_ck" , "axi_sel" , 5),"pwm3_ck" , "axi_sel" , 4),"pwm2_ck" , "axi_sel" , 3),"pwm1_ck" , "axi_sel" , 2),"therm_ck" , "axi_sel" , 1),"nfi_ck" , "axi_sel" , 0),/* PERI1 */ "usbslv_ck" , "axi_sel" , 8),"usb1_mcu_ck" , "axi_sel" , 7),"usb0_mcu_ck" , "axi_sel" , 6),"gcpu_ck" , "gcpu_sel" , 5),"fhctl_ck" , "clk26m" , 4),"spi1_ck" , "spi_sel" , 3),"auxadc_ck" , "clk26m" , 2),"peri_pwrap_ck" , "axi_sel" , 1),"i2c6_ck" , "axi_sel" , 0),static const char * const uart_ck_sel_parents[] = {"clk26m" ,"uart_sel" ,static const struct mtk_composite peri_clks[] = {"uart0_ck_sel" , uart_ck_sel_parents, 0x40c, 0, 1),"uart1_ck_sel" , uart_ck_sel_parents, 0x40c, 1, 1),"uart2_ck_sel" , uart_ck_sel_parents, 0x40c, 2, 1),"uart3_ck_sel" , uart_ck_sel_parents, 0x40c, 3, 1),static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };static const struct mtk_clk_rst_desc clk_rst_desc[] = {/* infrasys */ /* pericfg */ static const struct mtk_clk_desc infra_desc = {static const struct mtk_clk_desc peri_desc = {static const struct mtk_clk_desc topck_desc = {static const struct of_device_id of_match_clk_mt8135[] = {"mediatek,mt8135-infracfg" , .data = &infra_desc },"mediatek,mt8135-pericfg" , .data = &peri_desc },"mediatek,mt8135-topckgen" , .data = &topck_desc },/* sentinel */ } static struct platform_driver clk_mt8135_drv = {"clk-mt8135" ,"MediaTek MT8135 clocks driver" );"GPL" );
Messung V0.5 C=97 H=100 G=98
¤ Dauer der Verarbeitung: 0.5 Sekunden
¤ *© Formatika GbR, Deutschland
