// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (c) 2018 BayLibre, SAS. * Author: Jerome Brunet <jbrunet@baylibre.com> #include <linux/auxiliary_bus.h>#include <linux/clk.h>#include <linux/clk-provider.h>#include <linux/init.h>#include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/regmap.h>#include <linux/reset.h>#include <linux/slab.h>#include "meson-clkc-utils.h" #include "clk-regmap.h" #include "clk-phase.h" #include "sclk-div.h" #include <dt-bindings/clock/axg-audio-clkc.h>/* Audio clock register offsets */ #define AUDIO_CLK_GATE_EN 0x000#define AUDIO_MCLK_A_CTRL 0x004#define AUDIO_MCLK_B_CTRL 0x008#define AUDIO_MCLK_C_CTRL 0x00C#define AUDIO_MCLK_D_CTRL 0x010#define AUDIO_MCLK_E_CTRL 0x014#define AUDIO_MCLK_F_CTRL 0x018#define AUDIO_MST_PAD_CTRL0 0x01c#define AUDIO_MST_PAD_CTRL1 0x020#define AUDIO_SW_RESET 0x024#define AUDIO_MST_A_SCLK_CTRL0 0x040#define AUDIO_MST_A_SCLK_CTRL1 0x044#define AUDIO_MST_B_SCLK_CTRL0 0x048#define AUDIO_MST_B_SCLK_CTRL1 0x04C#define AUDIO_MST_C_SCLK_CTRL0 0x050#define AUDIO_MST_C_SCLK_CTRL1 0x054#define AUDIO_MST_D_SCLK_CTRL0 0x058#define AUDIO_MST_D_SCLK_CTRL1 0x05C#define AUDIO_MST_E_SCLK_CTRL0 0x060#define AUDIO_MST_E_SCLK_CTRL1 0x064#define AUDIO_MST_F_SCLK_CTRL0 0x068#define AUDIO_MST_F_SCLK_CTRL1 0x06C#define AUDIO_CLK_TDMIN_A_CTRL 0x080#define AUDIO_CLK_TDMIN_B_CTRL 0x084#define AUDIO_CLK_TDMIN_C_CTRL 0x088#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C#define AUDIO_CLK_TDMOUT_A_CTRL 0x090#define AUDIO_CLK_TDMOUT_B_CTRL 0x094#define AUDIO_CLK_TDMOUT_C_CTRL 0x098#define AUDIO_CLK_SPDIFIN_CTRL 0x09C#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4#define AUDIO_CLK_LOCKER_CTRL 0x0A8#define AUDIO_CLK_PDMIN_CTRL0 0x0AC#define AUDIO_CLK_PDMIN_CTRL1 0x0B0#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4/* SM1 introduce new register and some shifts :( */ #define AUDIO_CLK_GATE_EN1 0x004#define AUDIO_SM1_MCLK_A_CTRL 0x008#define AUDIO_SM1_MCLK_B_CTRL 0x00C#define AUDIO_SM1_MCLK_C_CTRL 0x010#define AUDIO_SM1_MCLK_D_CTRL 0x014#define AUDIO_SM1_MCLK_E_CTRL 0x018#define AUDIO_SM1_MCLK_F_CTRL 0x01C#define AUDIO_SM1_MST_PAD_CTRL0 0x020#define AUDIO_SM1_MST_PAD_CTRL1 0x024#define AUDIO_SM1_SW_RESET0 0x028#define AUDIO_SM1_SW_RESET1 0x02C#define AUDIO_CLK81_CTRL 0x030#define AUDIO_CLK81_EN 0x034#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \struct clk_regmap_gate_data){ \struct clk_init_data) { \"aud_" #_ name, \const char *[]){ #_ pname }, \#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \struct clk_regmap_mux_data){ \struct clk_init_data){ \"aud_" #_ name, \#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \struct clk_regmap_div_data){ \struct clk_init_data){ \"aud_" #_ name, \const char *[]){ #_ pname }, \#define AUD_PCLK_GATE(_name, _reg, _bit) { \struct clk_regmap_gate_data){ \struct clk_init_data) { \"aud_" #_ name, \const char *[]){ "aud_top" }, \#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \struct meson_sclk_div_data) { \struct clk_init_data) { \"aud_" #_ name, \const char *[]){ #_ pname }, \#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \struct meson_clk_triphase_data) { \struct clk_init_data) { \"aud_" #_ name, \const char *[]){ #_ pname }, \#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \struct meson_clk_phase_data) { \struct clk_init_data) { \"aud_" #_ name, \const char *[]){ #_ pname }, \#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \struct meson_sclk_ws_inv_data) { \struct clk_init_data) { \"aud_" #_ name, \const char *[]){ #_ pname }, \/* Audio Master Clocks */ static const struct clk_parent_data mst_mux_parent_data[] = {"mst_in0" , },"mst_in1" , },"mst_in2" , },"mst_in3" , },"mst_in4" , },"mst_in5" , },"mst_in6" , },"mst_in7" , },#define AUD_MST_MUX(_name, _reg, _flag) \## _sel, _reg, 0x7, 24, _flag, \#define AUD_MST_DIV(_name, _reg, _flag) \## _div, _reg, 0, 16, _flag, \## _name## _sel, CLK_SET_RATE_PARENT)#define AUD_MST_MCLK_GATE(_name, _reg) \## _name## _div, \#define AUD_MST_MCLK_MUX(_name, _reg) \#define AUD_MST_MCLK_DIV(_name, _reg) \#define AUD_MST_SYS_MUX(_name, _reg) \#define AUD_MST_SYS_DIV(_name, _reg) \/* Sample Clocks */ #define AUD_MST_SCLK_PRE_EN(_name, _reg) \## _name## _sclk_pre_en, _reg, 31, \## _name## _mclk, 0)#define AUD_MST_SCLK_DIV(_name, _reg) \## _name## _sclk_div, _reg, 20, 10, 0, 0, \## _name## _sclk_pre_en, \#define AUD_MST_SCLK_POST_EN(_name, _reg) \## _name## _sclk_post_en, _reg, 30, \## _name## _sclk_div, CLK_SET_RATE_PARENT)#define AUD_MST_SCLK(_name, _reg) \## _name## _sclk, _reg, 1, 0, 2, 4, \## _name## _sclk_post_en, CLK_SET_RATE_PARENT)#define AUD_MST_LRCLK_DIV(_name, _reg) \## _name## _lrclk_div, _reg, 0, 10, 10, 10, \## _name## _sclk_post_en, 0)#define AUD_MST_LRCLK(_name, _reg) \## _name## _lrclk, _reg, 1, 1, 3, 5, \## _name## _lrclk_div, CLK_SET_RATE_PARENT)/* TDM bit clock sources */ static const struct clk_parent_data tdm_sclk_parent_data[] = {"aud_mst_a_sclk" , .index = -1, },"aud_mst_b_sclk" , .index = -1, },"aud_mst_c_sclk" , .index = -1, },"aud_mst_d_sclk" , .index = -1, },"aud_mst_e_sclk" , .index = -1, },"aud_mst_f_sclk" , .index = -1, },"slv_sclk0" , },"slv_sclk1" , },"slv_sclk2" , },"slv_sclk3" , },"slv_sclk4" , },"slv_sclk5" , },"slv_sclk6" , },"slv_sclk7" , },"slv_sclk8" , },"slv_sclk9" , },/* TDM sample clock sources */ static const struct clk_parent_data tdm_lrclk_parent_data[] = {"aud_mst_a_lrclk" , .index = -1, },"aud_mst_b_lrclk" , .index = -1, },"aud_mst_c_lrclk" , .index = -1, },"aud_mst_d_lrclk" , .index = -1, },"aud_mst_e_lrclk" , .index = -1, },"aud_mst_f_lrclk" , .index = -1, },"slv_lrclk0" , },"slv_lrclk1" , },"slv_lrclk2" , },"slv_lrclk3" , },"slv_lrclk4" , },"slv_lrclk5" , },"slv_lrclk6" , },"slv_lrclk7" , },"slv_lrclk8" , },"slv_lrclk9" , },#define AUD_TDM_SCLK_MUX(_name, _reg) \## _name## _sclk_sel, _reg, 0xf, 24, \#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \## _name## _sclk_pre_en, _reg, 31, \## _name## _sclk_sel, CLK_SET_RATE_PARENT)#define AUD_TDM_SCLK_POST_EN(_name, _reg) \## _name## _sclk_post_en, _reg, 30, \## _name## _sclk_pre_en, CLK_SET_RATE_PARENT)#define AUD_TDM_SCLK(_name, _reg) \## _name## _sclk, _reg, 1, 29, \## _name## _sclk_post_en, \#define AUD_TDM_SCLK_WS(_name, _reg) \## _name## _sclk, _reg, 1, 29, 28, \## _name## _sclk_post_en, \#define AUD_TDM_LRLCK(_name, _reg) \## _name## _lrclk, _reg, 0xf, 20, \/* Pad master clock sources */ static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {"aud_mst_a_mclk" , .index = -1, },"aud_mst_b_mclk" , .index = -1, },"aud_mst_c_mclk" , .index = -1, },"aud_mst_d_mclk" , .index = -1, },"aud_mst_e_mclk" , .index = -1, },"aud_mst_f_mclk" , .index = -1, },/* Pad bit clock sources */ static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {"aud_mst_a_sclk" , .index = -1, },"aud_mst_b_sclk" , .index = -1, },"aud_mst_c_sclk" , .index = -1, },"aud_mst_d_sclk" , .index = -1, },"aud_mst_e_sclk" , .index = -1, },"aud_mst_f_sclk" , .index = -1, },/* Pad sample clock sources */ static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {"aud_mst_a_lrclk" , .index = -1, },"aud_mst_b_lrclk" , .index = -1, },"aud_mst_c_lrclk" , .index = -1, },"aud_mst_d_lrclk" , .index = -1, },"aud_mst_e_lrclk" , .index = -1, },"aud_mst_f_lrclk" , .index = -1, },#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \/* Common Clocks */ static struct clk_regmap ddr_arb =static struct clk_regmap pdm =static struct clk_regmap tdmin_a =static struct clk_regmap tdmin_b =static struct clk_regmap tdmin_c =static struct clk_regmap tdmin_lb =static struct clk_regmap tdmout_a =static struct clk_regmap tdmout_b =static struct clk_regmap tdmout_c =static struct clk_regmap frddr_a =static struct clk_regmap frddr_b =static struct clk_regmap frddr_c =static struct clk_regmap toddr_a =static struct clk_regmap toddr_b =static struct clk_regmap toddr_c =static struct clk_regmap loopback =static struct clk_regmap spdifin =static struct clk_regmap spdifout =static struct clk_regmap resample =static struct clk_regmap power_detect =static struct clk_regmap spdifout_clk_sel =static struct clk_regmap pdm_dclk_sel =static struct clk_regmap spdifin_clk_sel =static struct clk_regmap pdm_sysclk_sel =static struct clk_regmap spdifout_b_clk_sel =static struct clk_regmap spdifout_clk_div =static struct clk_regmap pdm_dclk_div =static struct clk_regmap spdifin_clk_div =static struct clk_regmap pdm_sysclk_div =static struct clk_regmap spdifout_b_clk_div =static struct clk_regmap spdifout_clk =static struct clk_regmap spdifin_clk =static struct clk_regmap pdm_dclk =static struct clk_regmap pdm_sysclk =static struct clk_regmap spdifout_b_clk =static struct clk_regmap mst_a_sclk_pre_en =static struct clk_regmap mst_b_sclk_pre_en =static struct clk_regmap mst_c_sclk_pre_en =static struct clk_regmap mst_d_sclk_pre_en =static struct clk_regmap mst_e_sclk_pre_en =static struct clk_regmap mst_f_sclk_pre_en =static struct clk_regmap mst_a_sclk_div =static struct clk_regmap mst_b_sclk_div =static struct clk_regmap mst_c_sclk_div =static struct clk_regmap mst_d_sclk_div =static struct clk_regmap mst_e_sclk_div =static struct clk_regmap mst_f_sclk_div =static struct clk_regmap mst_a_sclk_post_en =static struct clk_regmap mst_b_sclk_post_en =static struct clk_regmap mst_c_sclk_post_en =static struct clk_regmap mst_d_sclk_post_en =static struct clk_regmap mst_e_sclk_post_en =static struct clk_regmap mst_f_sclk_post_en =static struct clk_regmap mst_a_sclk =static struct clk_regmap mst_b_sclk =static struct clk_regmap mst_c_sclk =static struct clk_regmap mst_d_sclk =static struct clk_regmap mst_e_sclk =static struct clk_regmap mst_f_sclk =static struct clk_regmap mst_a_lrclk_div =static struct clk_regmap mst_b_lrclk_div =static struct clk_regmap mst_c_lrclk_div =static struct clk_regmap mst_d_lrclk_div =static struct clk_regmap mst_e_lrclk_div =static struct clk_regmap mst_f_lrclk_div =static struct clk_regmap mst_a_lrclk =static struct clk_regmap mst_b_lrclk =static struct clk_regmap mst_c_lrclk =static struct clk_regmap mst_d_lrclk =static struct clk_regmap mst_e_lrclk =static struct clk_regmap mst_f_lrclk =static struct clk_regmap tdmin_a_sclk_sel =static struct clk_regmap tdmin_b_sclk_sel =static struct clk_regmap tdmin_c_sclk_sel =static struct clk_regmap tdmin_lb_sclk_sel =static struct clk_regmap tdmout_a_sclk_sel =static struct clk_regmap tdmout_b_sclk_sel =static struct clk_regmap tdmout_c_sclk_sel =static struct clk_regmap tdmin_a_sclk_pre_en =static struct clk_regmap tdmin_b_sclk_pre_en =static struct clk_regmap tdmin_c_sclk_pre_en =static struct clk_regmap tdmin_lb_sclk_pre_en =static struct clk_regmap tdmout_a_sclk_pre_en =static struct clk_regmap tdmout_b_sclk_pre_en =static struct clk_regmap tdmout_c_sclk_pre_en =static struct clk_regmap tdmin_a_sclk_post_en =static struct clk_regmap tdmin_b_sclk_post_en =static struct clk_regmap tdmin_c_sclk_post_en =static struct clk_regmap tdmin_lb_sclk_post_en =static struct clk_regmap tdmout_a_sclk_post_en =static struct clk_regmap tdmout_b_sclk_post_en =static struct clk_regmap tdmout_c_sclk_post_en =static struct clk_regmap tdmin_a_sclk =static struct clk_regmap tdmin_b_sclk =static struct clk_regmap tdmin_c_sclk =static struct clk_regmap tdmin_lb_sclk =static struct clk_regmap tdmin_a_lrclk =static struct clk_regmap tdmin_b_lrclk =static struct clk_regmap tdmin_c_lrclk =static struct clk_regmap tdmin_lb_lrclk =static struct clk_regmap tdmout_a_lrclk =static struct clk_regmap tdmout_b_lrclk =static struct clk_regmap tdmout_c_lrclk =/* AXG Clocks */ static struct clk_regmap axg_tdmout_a_sclk =static struct clk_regmap axg_tdmout_b_sclk =static struct clk_regmap axg_tdmout_c_sclk =/* AXG/G12A Clocks */ static struct clk_hw axg_aud_top = {struct clk_init_data) {/* Provide aud_top signal name on axg and g12a */ "aud_top" ,const struct clk_ops) {},const struct clk_parent_data) {"pclk" ,static struct clk_regmap mst_a_mclk_sel =static struct clk_regmap mst_b_mclk_sel =static struct clk_regmap mst_c_mclk_sel =static struct clk_regmap mst_d_mclk_sel =static struct clk_regmap mst_e_mclk_sel =static struct clk_regmap mst_f_mclk_sel =static struct clk_regmap mst_a_mclk_div =static struct clk_regmap mst_b_mclk_div =static struct clk_regmap mst_c_mclk_div =static struct clk_regmap mst_d_mclk_div =static struct clk_regmap mst_e_mclk_div =static struct clk_regmap mst_f_mclk_div =static struct clk_regmap mst_a_mclk =static struct clk_regmap mst_b_mclk =static struct clk_regmap mst_c_mclk =static struct clk_regmap mst_d_mclk =static struct clk_regmap mst_e_mclk =static struct clk_regmap mst_f_mclk =/* G12a clocks */ static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(static struct clk_regmap g12a_tdmout_a_sclk =static struct clk_regmap g12a_tdmout_b_sclk =static struct clk_regmap g12a_tdmout_c_sclk =static struct clk_regmap toram =static struct clk_regmap spdifout_b =static struct clk_regmap eqdrc =/* SM1 Clocks */ static struct clk_regmap sm1_clk81_en = {struct clk_regmap_gate_data){struct clk_init_data) {"aud_clk81_en" ,const struct clk_parent_data) {"pclk" ,static struct clk_regmap sm1_sysclk_a_div = {struct clk_regmap_div_data){struct clk_init_data) {"aud_sysclk_a_div" ,const struct clk_hw *[]) {static struct clk_regmap sm1_sysclk_a_en = {struct clk_regmap_gate_data){struct clk_init_data) {"aud_sysclk_a_en" ,const struct clk_hw *[]) {static struct clk_regmap sm1_sysclk_b_div = {struct clk_regmap_div_data){struct clk_init_data) {"aud_sysclk_b_div" ,const struct clk_hw *[]) {static struct clk_regmap sm1_sysclk_b_en = {struct clk_regmap_gate_data){struct clk_init_data) {"aud_sysclk_b_en" ,const struct clk_hw *[]) {static const struct clk_hw *sm1_aud_top_parents[] = {static struct clk_regmap sm1_aud_top = {struct clk_regmap_mux_data){struct clk_init_data){"aud_top" ,static struct clk_regmap resample_b =static struct clk_regmap tovad =static struct clk_regmap locker =static struct clk_regmap spdifin_lb =static struct clk_regmap frddr_d =static struct clk_regmap toddr_d =static struct clk_regmap loopback_b =static struct clk_regmap earcrx =static struct clk_regmap sm1_mst_a_mclk_sel =static struct clk_regmap sm1_mst_b_mclk_sel =static struct clk_regmap sm1_mst_c_mclk_sel =static struct clk_regmap sm1_mst_d_mclk_sel =static struct clk_regmap sm1_mst_e_mclk_sel =static struct clk_regmap sm1_mst_f_mclk_sel =static struct clk_regmap sm1_earcrx_cmdc_clk_sel =static struct clk_regmap sm1_earcrx_dmac_clk_sel =static struct clk_regmap sm1_mst_a_mclk_div =static struct clk_regmap sm1_mst_b_mclk_div =static struct clk_regmap sm1_mst_c_mclk_div =static struct clk_regmap sm1_mst_d_mclk_div =static struct clk_regmap sm1_mst_e_mclk_div =static struct clk_regmap sm1_mst_f_mclk_div =static struct clk_regmap sm1_earcrx_cmdc_clk_div =static struct clk_regmap sm1_earcrx_dmac_clk_div =static struct clk_regmap sm1_mst_a_mclk =static struct clk_regmap sm1_mst_b_mclk =static struct clk_regmap sm1_mst_c_mclk =static struct clk_regmap sm1_mst_d_mclk =static struct clk_regmap sm1_mst_e_mclk =static struct clk_regmap sm1_mst_f_mclk =static struct clk_regmap sm1_earcrx_cmdc_clk =static struct clk_regmap sm1_earcrx_dmac_clk =static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(/* * Array of all clocks provided by this provider * The input clocks of the controller will be populated at runtime static struct clk_hw *axg_audio_hw_clks[] = {/* * Array of all G12A clocks provided by this provider * The input clocks of the controller will be populated at runtime static struct clk_hw *g12a_audio_hw_clks[] = {/* * Array of all SM1 clocks provided by this provider * The input clocks of the controller will be populated at runtime static struct clk_hw *sm1_audio_hw_clks[] = {static struct regmap_config axg_audio_regmap_cfg = {struct audioclk_data {struct meson_clk_hw_data hw_clks;const char *rst_drvname;unsigned int max_register;static int axg_audio_clkc_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;const struct audioclk_data *data;struct auxiliary_device *auxdev;struct regmap *map;void __iomem *regs;struct clk_hw *hw;struct clk *clk;int ret, i;if (!data)return -EINVAL;if (IS_ERR(regs))return PTR_ERR(regs);if (IS_ERR(map)) {"failed to init regmap: %ld\n" , PTR_ERR(map));return PTR_ERR(map);/* Get the mandatory peripheral clock */ "pclk" );if (IS_ERR(clk))return PTR_ERR(clk);if (ret) {"failed to reset device\n" );return ret;/* Take care to skip the registered input clocks */ for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {const char *name;/* array might be sparse */ if (!hw)continue ;if (ret) {"failed to register clock %s\n" , name);return ret;void *)&data->hw_clks);if (ret)return ret;/* Register auxiliary reset driver when applicable */ if (data->rst_drvname) {if (!auxdev)return -ENODEV;return 0;static const struct audioclk_data axg_audioclk_data = {static const struct audioclk_data g12a_audioclk_data = {"rst-g12a" ,static const struct audioclk_data sm1_audioclk_data = {"rst-sm1" ,static const struct of_device_id clkc_match_table[] = {"amlogic,axg-audio-clkc" ,"amlogic,g12a-audio-clkc" ,"amlogic,sm1-audio-clkc" ,static struct platform_driver axg_audio_driver = {"axg-audio-clkc" ,"Amlogic AXG/G12A/SM1 Audio Clock driver" );"Jerome Brunet " );"GPL" );"CLK_MESON" );
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