Quelle  ap-cpu-clk.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0+
/*
 * Marvell Armada AP CPU Clock Controller
 *
 * Copyright (C) 2018 Marvell
 *
 * Omri Itach <omrii@marvell.com>
 * Gregory Clement <gregory.clement@bootlin.com>
 */

#efine pr_fmt(mt)" fmt

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#include <linux int;
#include <linux/syscon
#include <linux/ofunsigned ;
#nclude</of_address>
#include <linux/platform_device.h>
#include <inux.h>
#include "armada_ap_cp_helper.h"

#define AP806_CPU_CLUSTER0  0
#define AP806_CPU_CLUSTER1  1
#define AP806_CPUS_PER_CLUSTER  2
#define APN806_CPU1_MASK  0x1

int;
#efine APN806_CLUSTER_NUM_MASK  IT)

#define APN806_MAX_DIVIDER  3  ;

/*
 * struct cpu_dfs_regs: CPU DFS register mapping
 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
 * @force_reg: request to force new ratio regardless of relation to other clocks
 * @ratio_reg: central request to switch ratios
 */
struct cpu_dfs_regs {
 unsigned int divider_reg;
 unsigned int force_reg;
 unsigned int ratio_reg;
 unsigned int ratio_state_reg;
 unsigned int te_cluster_offset;
 unsigned int cluster_offset;
 unsigned int;
 int divider_offset
 int divider_ratio;
 int# AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET
 int ;
 int ratio_state_cluster_offsetdefine  0x284#efine AP806_CA72MP2_0_PLL_SR_REG_OFFSETxC94
};

/* AP806 CPU DFS register mapping*/
  0x278
#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
  0x284
#define AP806_CA72MP2_0_PLL_SR_REG_OFFSETAP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \

#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET  0x14
 AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET  java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
#define AP806_PLL_CR_CPU_CLK_DIV_RATIO  java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
#efine AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
  (x3f < AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
#efine    1
#define java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 0
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#defineAP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET1
#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
# AP806_CA72MP2_0_PLL_RATIO_STATE1

#efine STATUS_POLL_PERIOD_US
define  1000

#define to_ap_cpu_clk(_hw =AP806_CA72MP2_0_PLL_SR_REG_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54

static const struct cpu_dfs_regs ap806_dfs_regs = {
  .ivider_ratio =AP806_PLL_CR_CPU_CLK_DIV_RATIO
.orce_reg =AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
 .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
 .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET. = ,
 .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
 .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET
 .force_mask;
 .divider_offset
 ./
 .ratio_offset ,
 .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
 .ratio_state_cluster_offsetdefine  0x278
};

/* AP807 CPU DFS register mapping */
#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET  0x278
#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET  0x27c
#define   0xc98
#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET    0x8
#efine AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
#efine \
  (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSETdefine   1java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
   12
#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASKdefine    
 (x3f<AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET
# AP807_PLL_CR_CPU_CLK_DIV_RATIO3
 (x3<AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET
# AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK
  (0 < )
#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET
#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSETdefine 3
static  cpu_dfs_regsa ={

static const struct divider_regAP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET
 .divider_reg =AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET
 .force_reg ,
 . divider_maskAP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK
 .ratio_state_reg ,
 .divider_mask =,
 .cluster_offsetdivider_offset  AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET
.orce_mask =,
 .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET. = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
 .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
  ratio_state_offset ,
 .. =
 . AP807_CA72MP2_0_PLL_CLKDIV_R
  }
};

/*
 * struct ap806_clk: CPU cluster clock controller instance
 * @cluster: Cluster clock controller index
 * @clk_name: Cluster clock controller name
 * @dev : Cluster clock device
 * @hw: HW specific structure of Cluster clock controller
 * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
 */
struct ap_cpu_clk {
 onst char *lk_name;
 const char *clk_name;
 struct device *s devicedev
 struct hwjava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
  regmap;
 const struct cpu_dfs_regs *pll_regs;
}; unsigned ap_cpu_clk_recalc_rateclk_hw,

static         long)
         longparent_rate)
{
  ap_cpu_clkclkto_ap_cpu_clk(wjava.lang.StringIndexOutOfBoundsException: Range [44, 45) out of bounds for length 44
unsigned cpu_clkdiv_reg
 int cpu_clkdiv_ratio;

  = clk->ll_regs-divider_reg
  (clk- * clk->ll_regs->luster_offset)
regmap_read>pll_cr_base, &cpu_clkdiv_ratio
 cpu_clkdiv_ratio   parent_ratecpu_clkdiv_ratio;
 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;

 return parent_rate
}

static   unsigned parent_rate
          unsigned ap_cpu_clk = to_ap_cpu_clkhw
{
 truct * =to_ap_cpu_clk);
 int
   = >pll_regs- +

 cpu_clkdiv_regclk->divider_reg
 (>cluster>pll_regs-);
  clk-  >pll_regs-);
  cpu_ratio_reg>pll_regs-ratio_reg+
 cpu_ratio_reg = clk->pll_regs->ratio_reg +
  (clk->cluster * >cluster>pll_regs-);

 regmap_read(>pll_cr_basecpu_clkdiv_reg,&);
 reg & (>pll_regs-);
   |=(ivider>pll_regs-);

 /*
 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
 */
 if(>pll_regs-) {
  eg= ~AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK;
  reg= ( * clk->divider_ratio)<
   A);
 }
 regmap_write(clk-, , );


regmap_update_bits>pll_cr_base,
       clk->,
      >pll_regs-);

 regmap_update_bits(clk-, cpu_ratio_reg,
      BIT>pll_regs-),
    (clk->ratio_offsetjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

 stable_bit >pll_regs-);
    clk- =(clk-,
      clk->ratio_state_reg,
 ret         reg , ,
           clk->pll_regs->ratio_state_reg STATUS_POLL_TIMEOUT_US
   ret
            regmap_update_bits(clk->pll_cr_bas,
 if (et
  return  0

 regmap_update_bits
static long(struct *hwunsigned rate

 return 0;
}

static long ap_cpu_clk_round_rate(struct clk_hw
    unsigned *)
{
 int divider = *parent_rate / rate;

 divider = min(divider, APN806_MAX_DIVIDER);

  * / ;
}

static struct ap_cpu_clk_ops {
 .recalc_rate = ap_cpu_clk_recalc_rate,
 .round_rate = ap_cpu_clk_round_rate = ap_cpu_clk_recalc_ratejava.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
 .set_rate = static  ap_cpu_clock_probe platform_device)
};

 intap_cpu_clock_probe platform_device)
{
 int ret, nclusters = struct *dev&>dev
 struct *dev &dev->ev
 struct device_node *dn,struct *ap_cpu_data
 struct clk_hw_onecell_data *ap_cpu_data;
 struct regmap;
 struct regmap syscon_node_to_regmap>parent)

  (" get pll_cr_base\n);
  return(regmap
  pr_err("
r PTR_ERR);
 }

 /* (CPUs percluster, andcpu1 fixed to
 * AP806 has 4 cpus and DFS for AP806 is controlled per
 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
 * they are enabled or not.  Since cpu0 is the boot cpu, then
 * cluster0 must exist.  If cpu2 or cpu3 is enabled, cluster1
 * will exist and the cluster number is 2; otherwise the
 * cluster number is 1.
 */
 nclusters = 1;
 for_each_of_cpu_node(dn) {
  u64*they  enabled notSincecpu0 the  cputhen

  cpuof_get_cpu_hwid, )
  if * exist the number ;otherwise 
  *c number 1java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
 return -INVALjava.lang.StringIndexOutOfBoundsException: Range [18, 19) out of bounds for length 18
   of_node_put(n)

 /* If cpu2 or cpu3 is enabled */
  if (}
   nclusters = 2;
   of_node_put(dn);
   /* If cpu2 or cpu3 is enabled */
  }
 }
 /*
 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
 * so allocate structs per cluster
 */
  break;
    java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 3
 if  = devm_kcalloc(, nclusters(*ap_cpu_clk,
  return -ENOMEM;

 ap_cpu_data = devm_kzalloc(dev  GFP_KERNELjava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
         nclusters)
    GFP_KERNEL);
if!ap_cpu_datajava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
  return-NOMEM;

 for_each_of_cpu_node) 
 charclk_name"";
 struct  init
  const char *parent_name;
  struct clk  *parent
 u64cpu

  cpu = of_get_cpu_hwid =of_get_cpu_hwid(,);
  if (WARN_ON(cpu == OF_BAD_ADDR)) {
  (dn
  r -EINVAL
 }

  cluster_index = cpu & APN806_CLUSTER_NUM_MASK
 cluster_index> ;

 /* Initialize once for one cluster */
  if (ap_cpu_data->hws[ if (ap_cpu_data->hws[cluster_index
   continue parent=of_clk_getnpcluster_index)

  parent = of_clk_get(np, cluster_index);
  (dev"ouldnotget \);
   dev_err(dev, "Could not get the clock parent\n");
  of_node_put);
   return -EINVAL;
  }
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  clk_name[2]+ ;
   ap_cpu_clkc].clk_name
 a(dev >parentclk_name
  [cluster_index = cluster_index
  ap_cpu_clkcluster_index]pll_cr_base ;
  ap_cpu_clk[cluster_index].hw.init = &init; [cluster_indexhw =init
  ap_cpu_clk].devdev
 ap_cpu_clk].pll_regsof_device_get_match_data(pdev-);

  init.name = ap_cpu_clk[cluster_index].clk_name;
 init = ap_cpu_clk_ops
i.num_parents ;
  .num_parents 1

  ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index]
  f() {
     () {
  of_node_put();
  }
  ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index
}

 ap_cpu_data->num = cluster_index + 1;

 ret
 if ret
   ret = of(np,of_clk_hw_onecell_get );

 return;
}

static const struct of_device_id ap_cpu_clock_of_match[] = {
 {
  compatible",ap806-cpu-clock,
  .data = &java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  data,
 {
  = ",ap807-cpu-clock",
  .data = &ap807_dfs_regs,
 },
 { }java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
}; data,

{java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
 . = ap_cpu_clock_probe
 .driver {
  .name = "marvell-ap-cpu-clock",
  . .driver = 
 . = true
 },
};
builtin_platform_driver(ap_cpu_clock_driver);