// SPDX-License-Identifier: GPL-2.0 /* * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a77990-cpg-mssr.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2015 Renesas Electronics Corp. #include <linux/device.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/soc/renesas/rcar-rst.h>#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>#include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" enum clk_ids {/* Core Clock Outputs exported to DT */ /* External Input Clocks */ /* Internal Core Clocks */ /* Module Clocks */ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {/* External Clock Inputs */ "extal" , CLK_EXTAL),/* Internal Core Clocks */ ".main" , CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),".pll1" , CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),".pll3" , CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),".pll0" , CLK_PLL0, CLK_MAIN, 1, 100),".pll0d4" , CLK_PLL0D4, CLK_PLL0, 4, 1),".pll0d6" , CLK_PLL0D6, CLK_PLL0, 6, 1),".pll0d8" , CLK_PLL0D8, CLK_PLL0, 8, 1),".pll0d20" , CLK_PLL0D20, CLK_PLL0, 20, 1),".pll0d24" , CLK_PLL0D24, CLK_PLL0, 24, 1),".pll1d2" , CLK_PLL1D2, CLK_PLL1, 2, 1),".pe" , CLK_PE, CLK_PLL0D20, 1, 1),".s0" , CLK_S0, CLK_PLL1, 2, 1),".s1" , CLK_S1, CLK_PLL1, 3, 1),".s2" , CLK_S2, CLK_PLL1, 4, 1),".s3" , CLK_S3, CLK_PLL1, 6, 1),".sdsrc" , CLK_SDSRC, CLK_PLL1, 2, 1),".rpcsrc" , CLK_RPCSRC, CLK_PLL0, CLK_PLL1),".r" , CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),".oco" , CLK_OCO, 8 * 1000 * 1000),/* Core Clock Outputs */ "za2" , R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),"za8" , R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),"z2" , R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),"ztr" , R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),"zt" , R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),"zx" , R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),"s0d1" , R8A774C0_CLK_S0D1, CLK_S0, 1, 1),"s0d3" , R8A774C0_CLK_S0D3, CLK_S0, 3, 1),"s0d6" , R8A774C0_CLK_S0D6, CLK_S0, 6, 1),"s0d12" , R8A774C0_CLK_S0D12, CLK_S0, 12, 1),"s0d24" , R8A774C0_CLK_S0D24, CLK_S0, 24, 1),"s1d1" , R8A774C0_CLK_S1D1, CLK_S1, 1, 1),"s1d2" , R8A774C0_CLK_S1D2, CLK_S1, 2, 1),"s1d4" , R8A774C0_CLK_S1D4, CLK_S1, 4, 1),"s2d1" , R8A774C0_CLK_S2D1, CLK_S2, 1, 1),"s2d2" , R8A774C0_CLK_S2D2, CLK_S2, 2, 1),"s2d4" , R8A774C0_CLK_S2D4, CLK_S2, 4, 1),"s3d1" , R8A774C0_CLK_S3D1, CLK_S3, 1, 1),"s3d2" , R8A774C0_CLK_S3D2, CLK_S3, 2, 1),"s3d4" , R8A774C0_CLK_S3D4, CLK_S3, 4, 1),"rpc" , R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),"rpcd2" , R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC),"sd0h" , R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),"sd1h" , R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),"sd3h" , R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c),"sd0" , R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074),"sd1" , R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078),"sd3" , R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c),"cl" , R8A774C0_CLK_CL, CLK_PLL1, 48, 1),"cp" , R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),"cpex" , R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1),"osc" , R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),"s0d6c" , R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),"s3d1c" , R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),"s3d2c" , R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),"s3d4c" , R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),"canfd" , R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244),"csi0" , R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c),"mso" , R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014),"r" , R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {"tmu4" , 121, R8A774C0_CLK_S0D6C),"tmu3" , 122, R8A774C0_CLK_S3D2C),"tmu2" , 123, R8A774C0_CLK_S3D2C),"tmu1" , 124, R8A774C0_CLK_S3D2C),"tmu0" , 125, R8A774C0_CLK_CP),"scif5" , 202, R8A774C0_CLK_S3D4C),"scif4" , 203, R8A774C0_CLK_S3D4C),"scif3" , 204, R8A774C0_CLK_S3D4C),"scif1" , 206, R8A774C0_CLK_S3D4C),"scif0" , 207, R8A774C0_CLK_S3D4C),"msiof3" , 208, R8A774C0_CLK_MSO),"msiof2" , 209, R8A774C0_CLK_MSO),"msiof1" , 210, R8A774C0_CLK_MSO),"msiof0" , 211, R8A774C0_CLK_MSO),"sys-dmac2" , 217, R8A774C0_CLK_S3D1),"sys-dmac1" , 218, R8A774C0_CLK_S3D1),"sys-dmac0" , 219, R8A774C0_CLK_S3D1),"cmt3" , 300, R8A774C0_CLK_R),"cmt2" , 301, R8A774C0_CLK_R),"cmt1" , 302, R8A774C0_CLK_R),"cmt0" , 303, R8A774C0_CLK_R),"scif2" , 310, R8A774C0_CLK_S3D4C),"sdif3" , 311, R8A774C0_CLK_SD3),"sdif1" , 313, R8A774C0_CLK_SD1),"sdif0" , 314, R8A774C0_CLK_SD0),"pcie0" , 319, R8A774C0_CLK_S3D1),"usb3-if0" , 328, R8A774C0_CLK_S3D1),"usb-dmac0" , 330, R8A774C0_CLK_S3D1),"usb-dmac1" , 331, R8A774C0_CLK_S3D1),"rwdt" , 402, R8A774C0_CLK_R),"intc-ex" , 407, R8A774C0_CLK_CP),"intc-ap" , 408, R8A774C0_CLK_S0D3),"audmac0" , 502, R8A774C0_CLK_S1D2),"hscif4" , 516, R8A774C0_CLK_S3D1C),"hscif3" , 517, R8A774C0_CLK_S3D1C),"hscif2" , 518, R8A774C0_CLK_S3D1C),"hscif1" , 519, R8A774C0_CLK_S3D1C),"hscif0" , 520, R8A774C0_CLK_S3D1C),"thermal" , 522, R8A774C0_CLK_CP),"pwm" , 523, R8A774C0_CLK_S3D4C),"fcpvd1" , 602, R8A774C0_CLK_S1D2),"fcpvd0" , 603, R8A774C0_CLK_S1D2),"fcpvb0" , 607, R8A774C0_CLK_S0D1),"fcpvi0" , 611, R8A774C0_CLK_S0D1),"fcpf0" , 615, R8A774C0_CLK_S0D1),"fcpcs" , 619, R8A774C0_CLK_S0D1),"vspd1" , 622, R8A774C0_CLK_S1D2),"vspd0" , 623, R8A774C0_CLK_S1D2),"vspb" , 626, R8A774C0_CLK_S0D1),"vspi0" , 631, R8A774C0_CLK_S0D1),"ehci0" , 703, R8A774C0_CLK_S3D2),"hsusb" , 704, R8A774C0_CLK_S3D2),"csi40" , 716, R8A774C0_CLK_CSI0),"du1" , 723, R8A774C0_CLK_S1D1),"du0" , 724, R8A774C0_CLK_S1D1),"lvds" , 727, R8A774C0_CLK_S2D1),"vin5" , 806, R8A774C0_CLK_S1D2),"vin4" , 807, R8A774C0_CLK_S1D2),"etheravb" , 812, R8A774C0_CLK_S3D2),"gpio6" , 906, R8A774C0_CLK_S3D4),"gpio5" , 907, R8A774C0_CLK_S3D4),"gpio4" , 908, R8A774C0_CLK_S3D4),"gpio3" , 909, R8A774C0_CLK_S3D4),"gpio2" , 910, R8A774C0_CLK_S3D4),"gpio1" , 911, R8A774C0_CLK_S3D4),"gpio0" , 912, R8A774C0_CLK_S3D4),"can-fd" , 914, R8A774C0_CLK_S3D2),"can-if1" , 915, R8A774C0_CLK_S3D4),"can-if0" , 916, R8A774C0_CLK_S3D4),"rpc-if" , 917, R8A774C0_CLK_RPCD2),"i2c6" , 918, R8A774C0_CLK_S3D2),"i2c5" , 919, R8A774C0_CLK_S3D2),"adg" , 922, R8A774C0_CLK_ZA2),"iic-pmic" , 926, R8A774C0_CLK_CP),"i2c4" , 927, R8A774C0_CLK_S3D2),"i2c3" , 928, R8A774C0_CLK_S3D2),"i2c2" , 929, R8A774C0_CLK_S3D2),"i2c1" , 930, R8A774C0_CLK_S3D2),"i2c0" , 931, R8A774C0_CLK_S3D2),"i2c7" , 1003, R8A774C0_CLK_S3D2),"ssi-all" , 1005, R8A774C0_CLK_S3D4),"ssi9" , 1006, MOD_CLK_ID(1005)),"ssi8" , 1007, MOD_CLK_ID(1005)),"ssi7" , 1008, MOD_CLK_ID(1005)),"ssi6" , 1009, MOD_CLK_ID(1005)),"ssi5" , 1010, MOD_CLK_ID(1005)),"ssi4" , 1011, MOD_CLK_ID(1005)),"ssi3" , 1012, MOD_CLK_ID(1005)),"ssi2" , 1013, MOD_CLK_ID(1005)),"ssi1" , 1014, MOD_CLK_ID(1005)),"ssi0" , 1015, MOD_CLK_ID(1005)),"scu-all" , 1017, R8A774C0_CLK_S3D4),"scu-dvc1" , 1018, MOD_CLK_ID(1017)),"scu-dvc0" , 1019, MOD_CLK_ID(1017)),"scu-ctu1-mix1" , 1020, MOD_CLK_ID(1017)),"scu-ctu0-mix0" , 1021, MOD_CLK_ID(1017)),"scu-src9" , 1022, MOD_CLK_ID(1017)),"scu-src8" , 1023, MOD_CLK_ID(1017)),"scu-src7" , 1024, MOD_CLK_ID(1017)),"scu-src6" , 1025, MOD_CLK_ID(1017)),"scu-src5" , 1026, MOD_CLK_ID(1017)),"scu-src4" , 1027, MOD_CLK_ID(1017)),"scu-src3" , 1028, MOD_CLK_ID(1017)),"scu-src2" , 1029, MOD_CLK_ID(1017)),"scu-src1" , 1030, MOD_CLK_ID(1017)),"scu-src0" , 1031, MOD_CLK_ID(1017)),static const unsigned int r8a774c0_crit_mod_clks[] __initconst = {/* RWDT */ /* INTC-AP (GIC) */ /* * CPG Clock Data /* * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 *-------------------------------------------------------------------- * 0 48 x 1 x100/1 x100/3 x100/3 * 1 48 x 1 x100/1 x100/3 x58/3 #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {/* EXTAL div PLL1 mult/div PLL3 mult/div */ static int __init r8a774c0_cpg_mssr_init(struct device *dev)const struct rcar_gen3_cpg_pll_config *cpg_pll_config;int error;if (error)return error;return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {/* Core Clocks */ /* Module Clocks */ /* Critical Module Clocks */ /* Callbacks */
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