// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * * Common Clock Framework support for Exynos3250 SoC. #include <linux/clk-provider.h>#include <linux/io.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <dt-bindings/clock/exynos3250.h>#include "clk.h" #include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS 0x4200#define DIV_LEFTBUS 0x4500#define GATE_IP_LEFTBUS 0x4800#define SRC_RIGHTBUS 0x8200#define DIV_RIGHTBUS 0x8500#define GATE_IP_RIGHTBUS 0x8800#define GATE_IP_PERIR 0x8960#define MPLL_LOCK 0xc010#define MPLL_CON0 0xc110#define VPLL_LOCK 0xc020#define VPLL_CON0 0xc120#define UPLL_LOCK 0xc030#define UPLL_CON0 0xc130#define SRC_TOP0 0xc210#define SRC_TOP1 0xc214#define SRC_CAM 0xc220#define SRC_MFC 0xc228#define SRC_G3D 0xc22c#define SRC_LCD 0xc234#define SRC_ISP 0xc238#define SRC_FSYS 0xc240#define SRC_PERIL0 0xc250#define SRC_PERIL1 0xc254#define SRC_MASK_TOP 0xc310#define SRC_MASK_CAM 0xc320#define SRC_MASK_LCD 0xc334#define SRC_MASK_ISP 0xc338#define SRC_MASK_FSYS 0xc340#define SRC_MASK_PERIL0 0xc350#define SRC_MASK_PERIL1 0xc354#define DIV_TOP 0xc510#define DIV_CAM 0xc520#define DIV_MFC 0xc528#define DIV_G3D 0xc52c#define DIV_LCD 0xc534#define DIV_ISP 0xc538#define DIV_FSYS0 0xc540#define DIV_FSYS1 0xc544#define DIV_FSYS2 0xc548#define DIV_PERIL0 0xc550#define DIV_PERIL1 0xc554#define DIV_PERIL3 0xc55c#define DIV_PERIL4 0xc560#define DIV_PERIL5 0xc564#define DIV_CAM1 0xc568#define CLKDIV2_RATIO 0xc580#define GATE_SCLK_CAM 0xc820#define GATE_SCLK_MFC 0xc828#define GATE_SCLK_G3D 0xc82c#define GATE_SCLK_LCD 0xc834#define GATE_SCLK_ISP_TOP 0xc838#define GATE_SCLK_FSYS 0xc840#define GATE_SCLK_PERIL 0xc850#define GATE_IP_CAM 0xc920#define GATE_IP_MFC 0xc928#define GATE_IP_G3D 0xc92c#define GATE_IP_LCD 0xc934#define GATE_IP_ISP 0xc938#define GATE_IP_FSYS 0xc940#define GATE_IP_PERIL 0xc950#define GATE_BLOCK 0xc970#define APLL_LOCK 0x14000#define APLL_CON0 0x14100#define SRC_CPU 0x14200#define DIV_CPU0 0x14500#define DIV_CPU1 0x14504#define PWR_CTRL1 0x15020#define PWR_CTRL2 0x15024/* Below definitions are used for PWR_CTRL settings */ #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)/* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1)#define CLKS_NR_DMC (CLK_DIV_DMCD + 1)#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1)static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {/* list of all parent clock list */ "fin_pll" , };"fin_pll" , "fout_apll" , };"fin_pll" , "fout_mpll" , };"fin_pll" , "fout_vpll" , };"fin_pll" , "fout_upll" , };"fin_pll" , "div_mpll_pre" , };"fin_pll" , "mout_epll" , };"mout_apll" , "mout_mpll_user_c" , };"mout_apll" , "mout_mpll_user_c" , };"div_aclk_200" , "div_aclk_160" , };"mout_ebi" , "mout_vpll" , };"mout_mpll_user_l" , };"mout_mpll_user_r" , };"fin_pll" , "div_aclk_400_mcuisp" , };"div_mpll_pre" , "mout_vpll" , };"mout_epll_user" , };"mout_aclk_266_0" , "mout_aclk_266_1" , };"fin_pll" , "div_aclk_266" , };"div_mpll_pre" , };"mout_epll_user" , "mout_vpll" };"xxti" , "xusbxti" ,"none" , "none" ,"none" , "none" , "div_mpll_pre" ,"mout_epll_user" , "mout_vpll" , };"audiocdclk" , "none" ,"none" , "none" ,"xxti" , "xusbxti" ,"div_mpll_pre" , "mout_epll_user" ,"mout_vpll" , };"xxti" , "xusbxti" ,"none" , "none" , "none" ,"none" , "div_mpll_pre" ,"mout_epll_user" , "mout_vpll" ,"none" , "none" , "none" ,"div_cam_blk_320" , };"xxti" , "xusbxti" ,"m_bitclkhsdiv4_2l" , "none" ,"none" , "none" , "div_mpll_pre" ,"mout_epll_user" , "mout_vpll" ,"none" , "none" , "none" ,"div_lcd_blk_145" , };"mout_mfc_0" , "mout_mfc_1" };"mout_g3d_0" , "mout_g3d_1" };static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {"sclk_mpll_1600" , "mout_mpll" , 1, 1, 0),"sclk_mpll_mif" , "mout_mpll" , 1, 2, 0),"sclk_bpll" , "fout_bpll" , 1, 2, 0),"div_cam_blk_320" , "sclk_mpll_1600" , 1, 5, 0),"div_lcd_blk_145" , "sclk_mpll_1600" , 1, 11, 0),/* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ "fin_pll" , "xusbxti" , 1, 1, 0),static const struct samsung_mux_clock mux_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* SRC_LEFTBUS */ "mout_mpll_user_l" , mout_mpll_user_p,"mout_gdl" , mout_gdl_p, SRC_LEFTBUS, 0, 1),/* SRC_RIGHTBUS */ "mout_mpll_user_r" , mout_mpll_user_p,"mout_gdr" , mout_gdr_p, SRC_RIGHTBUS, 0, 1),/* SRC_TOP0 */ "mout_ebi" , mout_ebi_p, SRC_TOP0, 28, 1),"mout_aclk_200" , group_div_mpll_pre_p, SRC_TOP0, 24, 1),"mout_aclk_160" , group_div_mpll_pre_p, SRC_TOP0, 20, 1),"mout_aclk_100" , group_div_mpll_pre_p, SRC_TOP0, 16, 1),"mout_aclk_266_1" , mout_aclk_266_1_p, SRC_TOP0, 14, 1),"mout_aclk_266_0" , mout_aclk_266_0_p, SRC_TOP0, 13, 1),"mout_aclk_266" , mout_aclk_266_p, SRC_TOP0, 12, 1),"mout_vpll" , mout_vpll_p, SRC_TOP0, 8, 1),"mout_epll_user" , mout_epll_user_p, SRC_TOP0, 4, 1),"mout_ebi_1" , mout_ebi_1_p, SRC_TOP0, 0, 1),/* SRC_TOP1 */ "mout_upll" , mout_upll_p, SRC_TOP1, 28, 1),"mout_aclk_400_mcuisp_sub" , mout_aclk_400_mcuisp_sub_p,"mout_aclk_266_sub" , mout_aclk_266_sub_p, SRC_TOP1, 20, 1),"mout_mpll" , mout_mpll_p, SRC_TOP1, 12, 1),"mout_aclk_400_mcuisp" , group_div_mpll_pre_p, SRC_TOP1, 8, 1),"mout_vpllsrc" , mout_vpllsrc_p, SRC_TOP1, 0, 1),/* SRC_CAM */ "mout_cam1" , group_sclk_p, SRC_CAM, 20, 4),"mout_cam_blk" , group_sclk_cam_blk_p, SRC_CAM, 0, 4),/* SRC_MFC */ "mout_mfc" , mout_mfc_p, SRC_MFC, 8, 1),"mout_mfc_1" , group_epll_vpll_p, SRC_MFC, 4, 1),"mout_mfc_0" , group_div_mpll_pre_p, SRC_MFC, 0, 1),/* SRC_G3D */ "mout_g3d" , mout_g3d_p, SRC_G3D, 8, 1),"mout_g3d_1" , group_epll_vpll_p, SRC_G3D, 4, 1),"mout_g3d_0" , group_div_mpll_pre_p, SRC_G3D, 0, 1),/* SRC_LCD */ "mout_mipi0" , group_sclk_p, SRC_LCD, 12, 4),"mout_fimd0" , group_sclk_fimd0_p, SRC_LCD, 0, 4),/* SRC_ISP */ "mout_uart_isp" , group_sclk_p, SRC_ISP, 12, 4),"mout_spi1_isp" , group_sclk_p, SRC_ISP, 8, 4),"mout_spi0_isp" , group_sclk_p, SRC_ISP, 4, 4),/* SRC_FSYS */ "mout_tsadc" , group_sclk_p, SRC_FSYS, 28, 4),"mout_mmc2" , group_sclk_p, SRC_FSYS, 8, 4),"mout_mmc1" , group_sclk_p, SRC_FSYS, 4, 4),"mout_mmc0" , group_sclk_p, SRC_FSYS, 0, 4),/* SRC_PERIL0 */ "mout_uart2" , group_sclk_p, SRC_PERIL0, 8, 4),"mout_uart1" , group_sclk_p, SRC_PERIL0, 4, 4),"mout_uart0" , group_sclk_p, SRC_PERIL0, 0, 4),/* SRC_PERIL1 */ "mout_spi1" , group_sclk_p, SRC_PERIL1, 20, 4),"mout_spi0" , group_sclk_p, SRC_PERIL1, 16, 4),"mout_audio" , group_sclk_audio_p, SRC_PERIL1, 4, 4),/* SRC_CPU */ "mout_mpll_user_c" , mout_mpll_user_p,"mout_hpm" , mout_hpm_p, SRC_CPU, 20, 1),"mout_core" , mout_core_p, SRC_CPU, 16, 1,"mout_apll" , mout_apll_p, SRC_CPU, 0, 1,static const struct samsung_div_clock div_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* DIV_LEFTBUS */ "div_gpl" , "div_gdl" , DIV_LEFTBUS, 4, 3),"div_gdl" , "mout_gdl" , DIV_LEFTBUS, 0, 4),/* DIV_RIGHTBUS */ "div_gpr" , "div_gdr" , DIV_RIGHTBUS, 4, 3),"div_gdr" , "mout_gdr" , DIV_RIGHTBUS, 0, 4),/* DIV_TOP */ "div_mpll_pre" , "sclk_mpll_mif" , DIV_TOP, 28, 2),"div_aclk_400_mcuisp" ,"mout_aclk_400_mcuisp" , DIV_TOP, 24, 3),"div_ebi" , "mout_ebi_1" , DIV_TOP, 16, 3),"div_aclk_200" , "mout_aclk_200" , DIV_TOP, 12, 3),"div_aclk_160" , "mout_aclk_160" , DIV_TOP, 8, 3),"div_aclk_100" , "mout_aclk_100" , DIV_TOP, 4, 4),"div_aclk_266" , "mout_aclk_266" , DIV_TOP, 0, 3),/* DIV_CAM */ "div_cam1" , "mout_cam1" , DIV_CAM, 20, 4),"div_cam_blk" , "mout_cam_blk" , DIV_CAM, 0, 4),/* DIV_MFC */ "div_mfc" , "mout_mfc" , DIV_MFC, 0, 4),/* DIV_G3D */ "div_g3d" , "mout_g3d" , DIV_G3D, 0, 4),/* DIV_LCD */ "div_mipi0_pre" , "div_mipi0" , DIV_LCD, 20, 4,"div_mipi0" , "mout_mipi0" , DIV_LCD, 16, 4),"div_fimd0" , "mout_fimd0" , DIV_LCD, 0, 4),/* DIV_ISP */ "div_uart_isp" , "mout_uart_isp" , DIV_ISP, 28, 4),"div_spi1_isp_pre" , "div_spi1_isp" ,"div_spi1_isp" , "mout_spi1_isp" , DIV_ISP, 16, 4),"div_spi0_isp_pre" , "div_spi0_isp" ,"div_spi0_isp" , "mout_spi0_isp" , DIV_ISP, 4, 4),/* DIV_FSYS0 */ "div_tsadc_pre" , "div_tsadc" , DIV_FSYS0, 8, 8,"div_tsadc" , "mout_tsadc" , DIV_FSYS0, 0, 4),/* DIV_FSYS1 */ "div_mmc1_pre" , "div_mmc1" , DIV_FSYS1, 24, 8,"div_mmc1" , "mout_mmc1" , DIV_FSYS1, 16, 4),"div_mmc0_pre" , "div_mmc0" , DIV_FSYS1, 8, 8,"div_mmc0" , "mout_mmc0" , DIV_FSYS1, 0, 4),/* DIV_FSYS2 */ "div_mmc2_pre" , "div_mmc2" , DIV_FSYS2, 8, 8,"div_mmc2" , "mout_mmc2" , DIV_FSYS2, 0, 4),/* DIV_PERIL0 */ "div_uart2" , "mout_uart2" , DIV_PERIL0, 8, 4),"div_uart1" , "mout_uart1" , DIV_PERIL0, 4, 4),"div_uart0" , "mout_uart0" , DIV_PERIL0, 0, 4),/* DIV_PERIL1 */ "div_spi1_pre" , "div_spi1" , DIV_PERIL1, 24, 8,"div_spi1" , "mout_spi1" , DIV_PERIL1, 16, 4),"div_spi0_pre" , "div_spi0" , DIV_PERIL1, 8, 8,"div_spi0" , "mout_spi0" , DIV_PERIL1, 0, 4),/* DIV_PERIL4 */ "div_pcm" , "div_audio" , DIV_PERIL4, 20, 8),"div_audio" , "mout_audio" , DIV_PERIL4, 16, 4),/* DIV_PERIL5 */ "div_i2s" , "div_audio" , DIV_PERIL5, 8, 6),/* DIV_CPU0 */ "div_core2" , "div_core" , DIV_CPU0, 28, 3),"div_apll" , "mout_apll" , DIV_CPU0, 24, 3),"div_pclk_dbg" , "div_core2" , DIV_CPU0, 20, 3),"div_atb" , "div_core2" , DIV_CPU0, 16, 3),"div_corem" , "div_core2" , DIV_CPU0, 4, 3),"div_core" , "mout_core" , DIV_CPU0, 0, 3),/* DIV_CPU1 */ "div_hpm" , "div_copy" , DIV_CPU1, 4, 3),"div_copy" , "mout_hpm" , DIV_CPU1, 0, 3),static const struct samsung_gate_clock gate_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* GATE_IP_LEFTBUS */ "async_g3d" , "div_aclk_100" , GATE_IP_LEFTBUS, 6,"async_mfcl" , "div_aclk_100" , GATE_IP_LEFTBUS, 4,"ppmuleft" , "div_aclk_100" , GATE_IP_LEFTBUS, 1,"gpio_left" , "div_aclk_100" , GATE_IP_LEFTBUS, 0,/* GATE_IP_RIGHTBUS */ "async_ispmx" , "div_aclk_100" ,"async_fsysd" , "div_aclk_100" ,"async_lcd0x" , "div_aclk_100" ,"async_camx" , "div_aclk_100" , GATE_IP_RIGHTBUS, 2,"ppmuright" , "div_aclk_100" , GATE_IP_RIGHTBUS, 1,"gpio_right" , "div_aclk_100" , GATE_IP_RIGHTBUS, 0,/* GATE_IP_PERIR */ "monocnt" , "div_aclk_100" , GATE_IP_PERIR, 22,"tzpc6" , "div_aclk_100" , GATE_IP_PERIR, 21,"provisionkey1" , "div_aclk_100" ,"provisionkey0" , "div_aclk_100" ,"cmu_isppart" , "div_aclk_100" , GATE_IP_PERIR, 18,"tmu_apbif" , "div_aclk_100" ,"keyif" , "div_aclk_100" , GATE_IP_PERIR, 16, 0, 0),"rtc" , "div_aclk_100" , GATE_IP_PERIR, 15, 0, 0),"wdt" , "div_aclk_100" , GATE_IP_PERIR, 14, 0, 0),"mct" , "div_aclk_100" , GATE_IP_PERIR, 13, 0, 0),"seckey" , "div_aclk_100" , GATE_IP_PERIR, 12,"tzpc5" , "div_aclk_100" , GATE_IP_PERIR, 10,"tzpc4" , "div_aclk_100" , GATE_IP_PERIR, 9,"tzpc3" , "div_aclk_100" , GATE_IP_PERIR, 8,"tzpc2" , "div_aclk_100" , GATE_IP_PERIR, 7,"tzpc1" , "div_aclk_100" , GATE_IP_PERIR, 6,"tzpc0" , "div_aclk_100" , GATE_IP_PERIR, 5,"cmu_corepart" , "div_aclk_100" , GATE_IP_PERIR, 4,"cmu_toppart" , "div_aclk_100" , GATE_IP_PERIR, 3,"pmu_apbif" , "div_aclk_100" , GATE_IP_PERIR, 2,"sysreg" , "div_aclk_100" , GATE_IP_PERIR, 1,"chip_id" , "div_aclk_100" , GATE_IP_PERIR, 0,/* GATE_SCLK_CAM */ "sclk_jpeg" , "div_cam_blk" ,"sclk_m2mscaler" , "div_cam_blk" ,"sclk_gscaler1" , "div_cam_blk" ,"sclk_gscaler0" , "div_cam_blk" ,/* GATE_SCLK_MFC */ "sclk_mfc" , "div_mfc" ,/* GATE_SCLK_G3D */ "sclk_g3d" , "div_g3d" ,/* GATE_SCLK_LCD */ "sclk_mipidphy2l" , "div_mipi0" ,"sclk_mipi0" , "div_mipi0_pre" ,"sclk_fimd0" , "div_fimd0" ,/* GATE_SCLK_ISP_TOP */ "sclk_cam1" , "div_cam1" ,"sclk_uart_isp" , "div_uart_isp" ,"sclk_spi1_isp" , "div_spi1_isp" ,"sclk_spi0_isp" , "div_spi0_isp" ,/* GATE_SCLK_FSYS */ "sclk_upll" , "mout_upll" , GATE_SCLK_FSYS, 10, 0, 0),"sclk_tsadc" , "div_tsadc_pre" ,"sclk_ebi" , "div_ebi" ,"sclk_mmc2" , "div_mmc2_pre" ,"sclk_mmc1" , "div_mmc1_pre" ,"sclk_mmc0" , "div_mmc0_pre" ,/* GATE_SCLK_PERIL */ "sclk_i2s" , "div_i2s" ,"sclk_pcm" , "div_pcm" ,"sclk_spi1" , "div_spi1_pre" ,"sclk_spi0" , "div_spi0_pre" ,"sclk_uart2" , "div_uart2" ,"sclk_uart1" , "div_uart1" ,"sclk_uart0" , "div_uart0" ,/* GATE_IP_CAM */ "qejpeg" , "div_cam_blk_320" , GATE_IP_CAM, 19,"pixelasyncm1" , "div_cam_blk_320" ,"pixelasyncm0" , "div_cam_blk_320" ,"ppmucamif" , "div_cam_blk_320" ,"qem2mscaler" , "div_cam_blk_320" ,"qegscaler1" , "div_cam_blk_320" ,"qegscaler0" , "div_cam_blk_320" ,"smmujpeg" , "div_cam_blk_320" ,"smmum2m2scaler" , "div_cam_blk_320" ,"smmugscaler1" , "div_cam_blk_320" ,"smmugscaler0" , "div_cam_blk_320" ,"jpeg" , "div_cam_blk_320" , GATE_IP_CAM, 6, 0, 0),"m2mscaler" , "div_cam_blk_320" ,"gscaler1" , "div_cam_blk_320" , GATE_IP_CAM, 1, 0, 0),"gscaler0" , "div_cam_blk_320" , GATE_IP_CAM, 0, 0, 0),/* GATE_IP_MFC */ "qemfc" , "div_aclk_200" , GATE_IP_MFC, 5,"ppmumfc_l" , "div_aclk_200" , GATE_IP_MFC, 3,"smmumfc_l" , "div_aclk_200" , GATE_IP_MFC, 1, 0, 0),"mfc" , "div_aclk_200" , GATE_IP_MFC, 0, 0, 0),/* GATE_IP_G3D */ "smmug3d" , "div_aclk_200" , GATE_IP_G3D, 3, 0, 0),"qeg3d" , "div_aclk_200" , GATE_IP_G3D, 2,"ppmug3d" , "div_aclk_200" , GATE_IP_G3D, 1,"g3d" , "div_aclk_200" , GATE_IP_G3D, 0, 0, 0),/* GATE_IP_LCD */ "qe_ch1_lcd" , "div_aclk_160" , GATE_IP_LCD, 7,"qe_ch0_lcd" , "div_aclk_160" , GATE_IP_LCD, 6,"ppmulcd0" , "div_aclk_160" , GATE_IP_LCD, 5,"smmufimd0" , "div_aclk_160" , GATE_IP_LCD, 4, 0, 0),"dsim0" , "div_aclk_160" , GATE_IP_LCD, 3, 0, 0),"smies" , "div_aclk_160" , GATE_IP_LCD, 2, 0, 0),"fimd0" , "div_aclk_160" , GATE_IP_LCD, 0, 0, 0),/* GATE_IP_ISP */ "cam1" , "mout_aclk_266_sub" , GATE_IP_ISP, 5, 0, 0),"uart_isp_top" , "mout_aclk_266_sub" ,"spi1_isp_top" , "mout_aclk_266_sub" ,"spi0_isp_top" , "mout_aclk_266_sub" ,/* GATE_IP_FSYS */ "tsadc" , "div_aclk_200" , GATE_IP_FSYS, 20, 0, 0),"ppmufile" , "div_aclk_200" , GATE_IP_FSYS, 17,"usbotg" , "div_aclk_200" , GATE_IP_FSYS, 13, 0, 0),"usbhost" , "div_aclk_200" , GATE_IP_FSYS, 12, 0, 0),"sromc" , "div_aclk_200" , GATE_IP_FSYS, 11, 0, 0),"sdmmc2" , "div_aclk_200" , GATE_IP_FSYS, 7, 0, 0),"sdmmc1" , "div_aclk_200" , GATE_IP_FSYS, 6, 0, 0),"sdmmc0" , "div_aclk_200" , GATE_IP_FSYS, 5, 0, 0),"pdma1" , "div_aclk_200" , GATE_IP_FSYS, 1, 0, 0),"pdma0" , "div_aclk_200" , GATE_IP_FSYS, 0, 0, 0),/* GATE_IP_PERIL */ "pwm" , "div_aclk_100" , GATE_IP_PERIL, 24, 0, 0),"pcm" , "div_aclk_100" , GATE_IP_PERIL, 23, 0, 0),"i2s" , "div_aclk_100" , GATE_IP_PERIL, 21, 0, 0),"spi1" , "div_aclk_100" , GATE_IP_PERIL, 17, 0, 0),"spi0" , "div_aclk_100" , GATE_IP_PERIL, 16, 0, 0),"i2c7" , "div_aclk_100" , GATE_IP_PERIL, 13, 0, 0),"i2c6" , "div_aclk_100" , GATE_IP_PERIL, 12, 0, 0),"i2c5" , "div_aclk_100" , GATE_IP_PERIL, 11, 0, 0),"i2c4" , "div_aclk_100" , GATE_IP_PERIL, 10, 0, 0),"i2c3" , "div_aclk_100" , GATE_IP_PERIL, 9, 0, 0),"i2c2" , "div_aclk_100" , GATE_IP_PERIL, 8, 0, 0),"i2c1" , "div_aclk_100" , GATE_IP_PERIL, 7, 0, 0),"i2c0" , "div_aclk_100" , GATE_IP_PERIL, 6, 0, 0),"uart2" , "div_aclk_100" , GATE_IP_PERIL, 2, 0, 0),"uart1" , "div_aclk_100" , GATE_IP_PERIL, 1, 0, 0),"uart0" , "div_aclk_100" , GATE_IP_PERIL, 0, 0, 0),/* APLL & MPLL & BPLL & UPLL */ static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {/* sentinel */ } /* EPLL */ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {/* sentinel */ } /* VPLL */ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {/* sentinel */ } static const struct samsung_pll_clock exynos3250_plls[] __initconst = {"fout_apll" , "fin_pll" ,"fout_mpll" , "fin_pll" ,"fout_vpll" , "fin_pll" ,"fout_upll" , "fin_pll" ,#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \#define E3250_CPU_DIV1(hpm, copy) \static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {"armclk" , CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,static void __init exynos3_core_down_clock(void __iomem *reg_base)unsigned int tmp;/* * Enable arm clock down (in idle) and set arm divider * ratios in WFI/WFE state. /* * Disable the clock up feature on Exynos4x12, in case it was * enabled by bootloader. static const struct samsung_cmu_info cmu_info __initconst = {static void __init exynos3250_cmu_init(struct device_node *np)struct samsung_clk_provider *ctx;if (!ctx)return ;"samsung,exynos3250-cmu" , exynos3250_cmu_init);/* * CMU DMC #define BPLL_LOCK 0x0118#define BPLL_CON0 0x0218#define BPLL_CON1 0x021c#define BPLL_CON2 0x0220#define SRC_DMC 0x0300#define DIV_DMC1 0x0504#define GATE_BUS_DMC0 0x0700#define GATE_BUS_DMC1 0x0704#define GATE_BUS_DMC2 0x0708#define GATE_BUS_DMC3 0x070c#define GATE_SCLK_DMC 0x0800#define GATE_IP_DMC0 0x0900#define GATE_IP_DMC1 0x0904#define EPLL_LOCK 0x1110#define EPLL_CON0 0x1114#define EPLL_CON1 0x1118#define EPLL_CON2 0x111c#define SRC_EPLL 0x1120static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {"fin_pll" , "fout_epll" , };"fin_pll" , "fout_bpll" , };"fin_pll" , "sclk_mpll_mif" , };"mout_mpll_mif" , "mout_bpll" , };static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* SRC_DMC */ "mout_mpll_mif" , mout_mpll_mif_p, SRC_DMC, 12, 1),"mout_bpll" , mout_bpll_p, SRC_DMC, 10, 1),"mout_dphy" , mout_dphy_p, SRC_DMC, 8, 1),"mout_dmc_bus" , mout_dphy_p, SRC_DMC, 4, 1),/* SRC_EPLL */ "mout_epll" , mout_epll_p, SRC_EPLL, 4, 1),static const struct samsung_div_clock dmc_div_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* DIV_DMC1 */ "div_dmc" , "div_dmc_pre" , DIV_DMC1, 27, 3),"div_dphy" , "mout_dphy" , DIV_DMC1, 23, 3),"div_dmc_pre" , "mout_dmc_bus" , DIV_DMC1, 19, 2),"div_dmcp" , "div_dmcd" , DIV_DMC1, 15, 3),"div_dmcd" , "div_dmc" , DIV_DMC1, 11, 3),static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {"fout_bpll" , "fin_pll" ,"fout_epll" , "fin_pll" ,static const struct samsung_cmu_info dmc_cmu_info __initconst = {static void __init exynos3250_cmu_dmc_init(struct device_node *np)"samsung,exynos3250-cmu-dmc" ,/* * CMU ISP #define DIV_ISP0 0x300#define DIV_ISP1 0x304#define GATE_IP_ISP0 0x800#define GATE_IP_ISP1 0x804#define GATE_SCLK_ISP 0x900static const struct samsung_div_clock isp_div_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* DIV_ISP0 */ "div_isp1" , "mout_aclk_266_sub" , DIV_ISP0, 4, 3),"div_isp0" , "mout_aclk_266_sub" , DIV_ISP0, 0, 3),/* DIV_ISP1 */ "div_mcuisp1" , "mout_aclk_400_mcuisp_sub" ,"div_mcuisp0" , "mout_aclk_400_mcuisp_sub" ,"div_mpwm" , "div_isp1" , DIV_ISP1, 0, 3),static const struct samsung_gate_clock isp_gate_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* GATE_IP_ISP0 */ "uart_isp" , "uart_isp_top" ,"wdt_isp" , "mout_aclk_266_sub" ,"pwm_isp" , "mout_aclk_266_sub" ,"i2c1_isp" , "mout_aclk_266_sub" ,"i2c0_isp" , "mout_aclk_266_sub" ,"mpwm_isp" , "mout_aclk_266_sub" ,"mcuctl_isp" , "mout_aclk_266_sub" ,"ppmuispx" , "mout_aclk_266_sub" ,"ppmuispmx" , "mout_aclk_266_sub" ,"qe_lite1" , "mout_aclk_266_sub" ,"qe_lite0" , "mout_aclk_266_sub" ,"qe_fd" , "mout_aclk_266_sub" ,"qe_drc" , "mout_aclk_266_sub" ,"qe_isp" , "mout_aclk_266_sub" ,"csis1" , "mout_aclk_266_sub" ,"smmu_lite1" , "mout_aclk_266_sub" ,"smmu_lite0" , "mout_aclk_266_sub" ,"smmu_fd" , "mout_aclk_266_sub" ,"smmu_drc" , "mout_aclk_266_sub" ,"smmu_isp" , "mout_aclk_266_sub" ,"gicisp" , "mout_aclk_266_sub" ,"csis0" , "mout_aclk_266_sub" ,"mcuisp" , "mout_aclk_266_sub" ,"lite1" , "mout_aclk_266_sub" ,"lite0" , "mout_aclk_266_sub" ,"fd" , "mout_aclk_266_sub" ,"drc" , "mout_aclk_266_sub" ,"isp" , "mout_aclk_266_sub" ,/* GATE_IP_ISP1 */ "qe_ispcx" , "uart_isp_top" ,"qe_scalerp" , "uart_isp_top" ,"qe_scalerc" , "uart_isp_top" ,"smmu_scalerp" , "uart_isp_top" ,"smmu_scalerc" , "uart_isp_top" ,"scalerp" , "uart_isp_top" ,"scalerc" , "uart_isp_top" ,"spi1_isp" , "uart_isp_top" ,"spi0_isp" , "uart_isp_top" ,"smmu_ispcx" , "uart_isp_top" ,"asyncaxim" , "uart_isp_top" ,/* GATE_SCLK_ISP */ "sclk_mpwm_isp" , "div_mpwm" ,static const struct samsung_cmu_info isp_cmu_info __initconst = {static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;return 0;static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {"samsung,exynos3250-cmu-isp" , },/* sentinel */ } static struct platform_driver exynos3250_cmu_isp_driver __initdata = {"exynos3250-cmu-isp" ,true ,static int __init exynos3250_cmu_platform_init(void )return platform_driver_probe(&exynos3250_cmu_isp_driver,
Messung V0.5 C=96 H=98 G=96
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