// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Authors: Thomas Abraham <thomas.ab@samsung.com> * Chander Kashyap <k.chander@samsung.com> * * Common Clock Framework support for Exynos5420 SoC. #include <dt-bindings/clock/exynos5420.h>#include <linux/slab.h>#include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/clk.h>#include "clk.h" #include "clk-cpu.h" #include "clk-exynos5-subcmu.h" #define APLL_LOCK 0x0#define APLL_CON0 0x100#define SRC_CPU 0x200#define DIV_CPU0 0x500#define DIV_CPU1 0x504#define GATE_BUS_CPU 0x700#define GATE_SCLK_CPU 0x800#define CLKOUT_CMU_CPU 0xa00#define SRC_MASK_CPERI 0x4300#define GATE_IP_G2D 0x8800#define CPLL_LOCK 0x10020#define DPLL_LOCK 0x10030#define EPLL_LOCK 0x10040#define RPLL_LOCK 0x10050#define IPLL_LOCK 0x10060#define SPLL_LOCK 0x10070#define VPLL_LOCK 0x10080#define MPLL_LOCK 0x10090#define CPLL_CON0 0x10120#define DPLL_CON0 0x10128#define EPLL_CON0 0x10130#define EPLL_CON1 0x10134#define EPLL_CON2 0x10138#define RPLL_CON0 0x10140#define RPLL_CON1 0x10144#define RPLL_CON2 0x10148#define IPLL_CON0 0x10150#define SPLL_CON0 0x10160#define VPLL_CON0 0x10170#define MPLL_CON0 0x10180#define SRC_TOP0 0x10200#define SRC_TOP1 0x10204#define SRC_TOP2 0x10208#define SRC_TOP3 0x1020c#define SRC_TOP4 0x10210#define SRC_TOP5 0x10214#define SRC_TOP6 0x10218#define SRC_TOP7 0x1021c#define SRC_TOP8 0x10220 /* 5800 specific */ #define SRC_TOP9 0x10224 /* 5800 specific */ #define SRC_DISP10 0x1022c#define SRC_MAU 0x10240#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254#define SRC_ISP 0x10270#define SRC_CAM 0x10274 /* 5800 specific */ #define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288#define SRC_TOP13 0x1028c /* 5800 specific */ #define SRC_MASK_TOP0 0x10300#define SRC_MASK_TOP1 0x10304#define SRC_MASK_TOP2 0x10308#define SRC_MASK_TOP7 0x1031c#define SRC_MASK_DISP10 0x1032c#define SRC_MASK_MAU 0x10334#define SRC_MASK_FSYS 0x10340#define SRC_MASK_PERIC0 0x10350#define SRC_MASK_PERIC1 0x10354#define SRC_MASK_ISP 0x10370#define DIV_TOP0 0x10500#define DIV_TOP1 0x10504#define DIV_TOP2 0x10508#define DIV_TOP8 0x10520 /* 5800 specific */ #define DIV_TOP9 0x10524 /* 5800 specific */ #define DIV_DISP10 0x1052c#define DIV_MAU 0x10544#define DIV_FSYS0 0x10548#define DIV_FSYS1 0x1054c#define DIV_FSYS2 0x10550#define DIV_PERIC0 0x10558#define DIV_PERIC1 0x1055c#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568#define DIV_CAM 0x10574 /* 5800 specific */ #define SCLK_DIV_ISP0 0x10580#define SCLK_DIV_ISP1 0x10584#define DIV2_RATIO0 0x10590#define DIV4_RATIO 0x105a0#define GATE_BUS_TOP 0x10700#define GATE_BUS_DISP1 0x10728#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_FSYS2 0x10748#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764#define GATE_BUS_NOC 0x10770#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_CAM 0x10924 /* 5800 specific */ #define GATE_IP_MFC 0x1092c#define GATE_IP_DISP1 0x10928#define GATE_IP_G3D 0x10930#define GATE_IP_GEN 0x10934#define GATE_IP_FSYS 0x10944#define GATE_IP_PERIC 0x10950#define GATE_IP_PERIS 0x10960#define GATE_IP_MSCL 0x10970#define GATE_TOP_SCLK_GSCL 0x10820#define GATE_TOP_SCLK_DISP1 0x10828#define GATE_TOP_SCLK_MAU 0x1083c#define GATE_TOP_SCLK_FSYS 0x10840#define GATE_TOP_SCLK_PERIC 0x10850#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110#define SRC_CDREX 0x20200#define DIV_CDREX0 0x20500#define DIV_CDREX1 0x20504#define GATE_BUS_CDREX0 0x20700#define GATE_BUS_CDREX1 0x20704#define KPLL_LOCK 0x28000#define KPLL_CON0 0x28100#define SRC_KFC 0x28200#define DIV_KFC0 0x28500/* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1)/* Exynos5x SoC type */ enum exynos5x_soc {/* list of PLLs */ enum exynos5x_plls {/* number of PLLs */ static void __iomem *reg_base;static enum exynos5x_soc exynos5x_soc;/* * list of controller registers to be saved and restored during a * suspend/resume cycle. static const unsigned long exynos5x_clk_regs[] __initconst = {static const unsigned long exynos5800_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {/* list of all parent clocks */ "mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" };"mout_apll" , "mout_mspll_cpu" };"mout_kpll" , "mout_mspll_kfc" };"fin_pll" , "fout_apll" };"fin_pll" , "fout_bpll" };"fin_pll" , "fout_cpll" };"fin_pll" , "fout_dpll" };"fin_pll" , "fout_epll" };"fin_pll" , "fout_ipll" };"fin_pll" , "fout_kpll" };"fin_pll" , "fout_mpll" };"fin_pll" , "fout_rpll" };"fin_pll" , "fout_spll" };"fin_pll" , "fout_vpll" };"mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" };"fin_pll" , "mout_sclk_cpll" ,"mout_sclk_dpll" , "mout_sclk_mpll" , "mout_sclk_spll" ,"mout_sclk_ipll" , "mout_sclk_epll" , "mout_sclk_rpll" };"mout_sclk_rpll" , "mout_sclk_spll" };"mout_sclk_ipll" , "mout_sclk_dpll" , "mout_sclk_mpll" };"mout_sclk_vpll" , "mout_sclk_dpll" };"mout_fimd1" , "mout_fimd1_opt" };"dout_aclk66" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk66" };"mout_sw_aclk66" , "ff_sw_aclk66" };"dout_aclk200_fsys" , "mout_sclk_spll" };"dout_pclk200_fsys" , "mout_sclk_spll" };"fin_pll" , "mout_sw_pclk200_fsys" };"fin_pll" , "mout_sw_aclk200_fsys" };"dout_aclk200_fsys2" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk200_fsys2" };"dout_aclk100_noc" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk100_noc" };"dout_aclk400_wcore" , "mout_sclk_spll" };"mout_aclk400_wcore" , "sclk_bpll" };"fin_pll" , "mout_sw_aclk400_wcore" };"dout_aclk400_isp" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk400_isp" };"dout_aclk333_432_isp0" ,"mout_sclk_spll" };"fin_pll" , "mout_sw_aclk333_432_isp0" };"dout_aclk333_432_isp" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk333_432_isp" };"dout_aclk200" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk200" };"dout_aclk400_mscl" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk400_mscl" };"dout_aclk333" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk333" };"dout_aclk166" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk166" };"dout_aclk266" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk266" };"fin_pll" , "mout_sw_aclk266" };"dout_aclk333_432_gscl" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk333_432_gscl" };"dout_aclk300_gscl" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk300_gscl" };"dout_aclk300_disp1" , "mout_sclk_spll" };"dout_aclk400_disp1" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk300_disp1" };"fin_pll" , "mout_sw_aclk400_disp1" };"dout_aclk300_jpeg" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk300_jpeg" };"dout_aclk_g3d" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk_g3d" };"dout_aclk266_g2d" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk266_g2d" };"dout_aclk333_g2d" , "mout_sclk_spll" };"fin_pll" , "mout_sw_aclk333_g2d" };"fin_pll" , "cdclk0" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" , "mout_sclk_ipll" ,"mout_sclk_epll" , "mout_sclk_rpll" };"fin_pll" , "cdclk1" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" , "mout_sclk_ipll" ,"mout_sclk_epll" , "mout_sclk_rpll" };"fin_pll" , "cdclk2" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" , "mout_sclk_ipll" ,"mout_sclk_epll" , "mout_sclk_rpll" };"fin_pll" , "dout_audio0" , "dout_audio1" ,"dout_audio2" , "spdif_extclk" , "mout_sclk_ipll" ,"mout_sclk_epll" , "mout_sclk_rpll" };"dout_hdmi_pixel" , "sclk_hdmiphy" };"fin_pll" , "maudio_clk" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" , "mout_sclk_ipll" ,"mout_sclk_epll" , "mout_sclk_rpll" };"mout_sclk_epll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" };"mout_bpll" , "mout_mx_mspll_ccore" };/* List of parents specific to exynos5800 */ "mout_sclk_epll" , "ff_dout_epll2" };"mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "ff_dout_spll2" };"mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "ff_dout_spll2" ,"mout_epll2" , "mout_sclk_ipll" };"mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "ff_dout_spll2" ,"mout_epll2" };"mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" };"mout_sclk_ipll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "ff_dout_spll2" };"mout_sclk_cpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "mout_sclk_spll" ,"mout_epll2" , "mout_sclk_ipll" };"sclk_bpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "ff_dout_spll2" ,"mout_sclk_spll" , "mout_sclk_epll" };"mout_sclk_epll" , "mout_sclk_dpll" ,"mout_sclk_mpll" ,"ff_dout_spll2" };"dout_aclk432_scaler" , "dout_sclk_sw" };"dout_osc_div" , "mout_sw_aclk432_scaler" };"dout_aclk432_cam" , "dout_sclk_sw" };"dout_osc_div" , "mout_sw_aclk432_cam" };"dout_aclkfl1_550_cam" , "dout_sclk_sw" };"dout_osc_div" , "mout_sw_aclkfl1_550_cam" };"dout_aclk550_cam" , "dout_sclk_sw" };"dout_osc_div" , "mout_sw_aclk550_cam" };"dout_osc_div" , "mout_mau_epll_clk" };"sclk_bpll" , "mout_sclk_dpll" ,"mout_sclk_mpll" , "ff_dout_spll2" ,"mout_sclk_spll" , "mout_sclk_epll" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock"fin_pll" , NULL, 0, 0),/* fixed rate clocks generated inside the soc */ static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {"sclk_hdmiphy" , NULL, 0, 24000000),"sclk_pwi" , NULL, 0, 24000000),"sclk_usbh20" , NULL, 0, 48000000),"mphy_refclk_ixtal24" , NULL, 0, 48000000),"sclk_usbh20_scan_clk" , NULL, 0, 480000000),static const struct samsung_fixed_factor_clock"ff_hsic_12m" , "fin_pll" , 1, 2, 0),"ff_sw_aclk66" , "mout_sw_aclk66" , 1, 2, 0),static const struct samsung_fixed_factor_clock"ff_dout_epll2" , "mout_sclk_epll" , 1, 2, 0),"ff_dout_spll2" , "mout_sclk_spll" , 1, 2, 0),static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {"mout_aclk400_isp" , mout_group3_5800_p, SRC_TOP0, 0, 3),"mout_aclk400_mscl" , mout_group3_5800_p, SRC_TOP0, 4, 3),"mout_aclk400_wcore" , mout_group2_5800_p, SRC_TOP0, 16, 3),"mout_aclk100_noc" , mout_group1_5800_p, SRC_TOP0, 20, 2),"mout_aclk333_432_gscl" , mout_group6_5800_p, SRC_TOP1, 0, 2),"mout_aclk333_432_isp" , mout_group6_5800_p, SRC_TOP1, 4, 2),"mout_aclk333_432_isp0" , mout_group6_5800_p, SRC_TOP1, 12, 2),"mout_aclk266" , mout_group5_5800_p, SRC_TOP1, 20, 2),"mout_aclk333" , mout_group1_5800_p, SRC_TOP1, 28, 2),"mout_aclk400_disp1" , mout_group7_5800_p, SRC_TOP2, 4, 3),"mout_aclk333_g2d" , mout_group5_5800_p, SRC_TOP2, 8, 2),"mout_aclk266_g2d" , mout_group5_5800_p, SRC_TOP2, 12, 2),"mout_aclk300_jpeg" , mout_group5_5800_p, SRC_TOP2, 20, 2),"mout_aclk300_disp1" , mout_group5_5800_p, SRC_TOP2, 24, 2),"mout_aclk300_gscl" , mout_group5_5800_p, SRC_TOP2, 28, 2),"mout_mx_mspll_ccore_phy" ,"mout_mx_mspll_ccore" ,"mout_mau_epll_clk" , mout_mau_epll_clk_5800_p,"sclk_bpll" , mout_bpll_p, SRC_TOP7, 24, 1),"mout_epll2" , mout_epll2_5800_p, SRC_TOP7, 28, 1),"mout_aclk550_cam" , mout_group3_5800_p, SRC_TOP8, 16, 3),"mout_aclkfl1_550_cam" , mout_group3_5800_p, SRC_TOP8, 20, 3),"mout_aclk432_cam" , mout_group6_5800_p, SRC_TOP8, 24, 2),"mout_aclk432_scaler" , mout_group6_5800_p, SRC_TOP8, 28, 2),"mout_user_mau_epll" , mout_group16_5800_p,"mout_user_aclk550_cam" , mout_group15_5800_p,"mout_user_aclkfl1_550_cam" , mout_group13_5800_p,"mout_user_aclk432_cam" , mout_group11_5800_p,"mout_user_aclk432_scaler" , mout_group9_5800_p,"mout_sw_aclk550_cam" , mout_group14_5800_p, SRC_TOP13, 16, 1),"mout_sw_aclkfl1_550_cam" , mout_group12_5800_p,"mout_sw_aclk432_cam" , mout_group10_5800_p,"mout_sw_aclk432_scaler" , mout_group8_5800_p,"mout_fimd1" , mout_group2_p, SRC_DISP10, 4, 3),static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {"dout_aclk400_wcore" ,"mout_aclk400_wcore" , DIV_TOP0, 16, 3),"dout_aclk550_cam" , "mout_aclk550_cam" ,"dout_aclkfl1_550_cam" , "mout_aclkfl1_550_cam" ,"dout_aclk432_cam" , "mout_aclk432_cam" ,"dout_aclk432_scaler" , "mout_aclk432_scaler" ,"dout_osc_div" , "fin_pll" , DIV_TOP9, 20, 3),"dout_sclk_sw" , "sclk_spll" , DIV_TOP9, 24, 6),static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {"aclk550_cam" , "mout_user_aclk550_cam" ,"aclk432_scaler" , "mout_user_aclk432_scaler" ,static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {"sclk_bpll" , mout_bpll_p, TOP_SPARE2, 0, 1),"mout_aclk400_wcore_bpll" , mout_aclk400_wcore_bpll_p,"mout_aclk400_isp" , mout_group1_p, SRC_TOP0, 0, 2),"mout_aclk400_mscl" , mout_group1_p, SRC_TOP0, 4, 2),"mout_aclk400_wcore" , mout_group1_p, SRC_TOP0, 16, 2),"mout_aclk100_noc" , mout_group1_p, SRC_TOP0, 20, 2),"mout_aclk333_432_gscl" , mout_group4_p, SRC_TOP1, 0, 2),"mout_aclk333_432_isp" , mout_group4_p,"mout_aclk333_432_isp0" , mout_group4_p, SRC_TOP1, 12, 2),"mout_aclk266" , mout_group1_p, SRC_TOP1, 20, 2),"mout_aclk333" , mout_group1_p, SRC_TOP1, 28, 2),"mout_aclk400_disp1" , mout_group1_p, SRC_TOP2, 4, 2),"mout_aclk333_g2d" , mout_group1_p, SRC_TOP2, 8, 2),"mout_aclk266_g2d" , mout_group1_p, SRC_TOP2, 12, 2),"mout_aclk300_jpeg" , mout_group1_p, SRC_TOP2, 20, 2),"mout_aclk300_disp1" , mout_group1_p, SRC_TOP2, 24, 2),"mout_aclk300_gscl" , mout_group1_p, SRC_TOP2, 28, 2),"mout_mx_mspll_ccore" ,"mout_mau_epll_clk" , mout_mau_epll_clk_p, SRC_TOP7, 20, 2,"mout_fimd1" , mout_group3_p, SRC_DISP10, 4, 1),static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {"dout_aclk400_wcore" ,"mout_aclk400_wcore_bpll" , DIV_TOP0, 16, 3),static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {"seckey" , "aclk66_psgen" , GATE_BUS_PERIS1, 1, 0, 0),/* Maudio Block */ "mau_epll" , "mout_mau_epll_clk" ,"sclk_maudio0" , "dout_maudio0" ,"sclk_maupcm0" , "dout_maupcm0" ,static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {"mout_user_pclk66_gpio" , mout_user_pclk66_gpio_p,"mout_mspll_kfc" , mout_mspll_cpu_p,"mout_mspll_cpu" , mout_mspll_cpu_p,"mout_apll" , mout_apll_p, SRC_CPU, 0, 1,"mout_cpu" , mout_cpu_p, SRC_CPU, 16, 1),"mout_kpll" , mout_kpll_p, SRC_KFC, 0, 1,"mout_kfc" , mout_kfc_p, SRC_KFC, 16, 1),"mout_aclk200" , mout_group1_p, SRC_TOP0, 8, 2),"mout_aclk200_fsys2" , mout_group1_p, SRC_TOP0, 12, 2),"mout_pclk200_fsys" , mout_group1_p, SRC_TOP0, 24, 2),"mout_aclk200_fsys" , mout_group1_p, SRC_TOP0, 28, 2),"mout_aclk66" , mout_group1_p, SRC_TOP1, 8, 2),"mout_aclk166" , mout_group1_p, SRC_TOP1, 24, 2),"mout_aclk_g3d" , mout_group5_p, SRC_TOP2, 16, 1,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p,"mout_user_aclk400_mscl" , mout_user_aclk400_mscl_p,"mout_user_aclk200_disp1" ,"mout_user_aclk200_fsys2" , mout_user_aclk200_fsys2_p,"mout_user_aclk400_wcore" , mout_user_aclk400_wcore_p,"mout_user_aclk100_noc" , mout_user_aclk100_noc_p,"mout_user_pclk200_fsys" , mout_user_pclk200_fsys_p,"mout_user_aclk200_fsys" , mout_user_aclk200_fsys_p,"mout_user_aclk333_432_gscl" , mout_user_aclk333_432_gscl_p,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p,"mout_user_aclk66_peric" , mout_user_aclk66_peric_p,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p,"mout_user_aclk266" , mout_user_aclk266_p, SRC_TOP4, 20, 1),"mout_user_aclk166" , mout_user_aclk166_p, SRC_TOP4, 24, 1),"mout_user_aclk333" , mout_user_aclk333_p,"mout_user_aclk400_disp1" ,"mout_user_aclk66_psgen" , mout_user_aclk66_peric_p,"mout_user_aclk333_g2d" , mout_user_aclk333_g2d_p,"mout_user_aclk266_g2d" , mout_user_aclk266_g2d_p,"mout_user_aclk_g3d" , mout_user_aclk_g3d_p,"mout_user_aclk300_jpeg" , mout_user_aclk300_jpeg_p,"mout_user_aclk300_disp1" ,"mout_user_aclk300_gscl" ,"mout_sclk_mpll" , mout_mpll_p, SRC_TOP6, 0, 1),"mout_sclk_vpll" , mout_vpll_p, SRC_TOP6, 4, 1,"mout_sclk_spll" , mout_spll_p, SRC_TOP6, 8, 1),"mout_sclk_ipll" , mout_ipll_p, SRC_TOP6, 12, 1),"mout_sclk_rpll" , mout_rpll_p, SRC_TOP6, 16, 1),"mout_sclk_epll" , mout_epll_p, SRC_TOP6, 20, 1,"mout_sclk_dpll" , mout_dpll_p, SRC_TOP6, 24, 1),"mout_sclk_cpll" , mout_cpll_p, SRC_TOP6, 28, 1),"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p,"mout_sw_aclk400_mscl" , mout_sw_aclk400_mscl_p,"mout_sw_aclk200" , mout_sw_aclk200_p,"mout_sw_aclk200_fsys2" , mout_sw_aclk200_fsys2_p,"mout_sw_aclk400_wcore" , mout_sw_aclk400_wcore_p,"mout_sw_aclk100_noc" , mout_sw_aclk100_noc_p,"mout_sw_pclk200_fsys" , mout_sw_pclk200_fsys_p,"mout_sw_aclk200_fsys" , mout_sw_aclk200_fsys_p,"mout_sw_aclk333_432_gscl" , mout_sw_aclk333_432_gscl_p,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p,"mout_sw_aclk66" , mout_sw_aclk66_p, SRC_TOP11, 8, 1),"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p,"mout_sw_aclk266" , mout_sw_aclk266_p, SRC_TOP11, 20, 1),"mout_sw_aclk166" , mout_sw_aclk166_p, SRC_TOP11, 24, 1),"mout_sw_aclk333" , mout_sw_aclk333_p,"mout_sw_aclk400_disp1" ,"mout_sw_aclk333_g2d" , mout_sw_aclk333_g2d_p,"mout_sw_aclk266_g2d" , mout_sw_aclk266_g2d_p,"mout_sw_aclk_g3d" , mout_sw_aclk_g3d_p,"mout_sw_aclk300_jpeg" , mout_sw_aclk300_jpeg_p,"mout_sw_aclk300_disp1" ,"mout_sw_aclk300_gscl" ,/* DISP1 Block */ "mout_mipi1" , mout_group2_p, SRC_DISP10, 16, 3),"mout_dp1" , mout_group2_p, SRC_DISP10, 20, 3),"mout_pixel" , mout_group2_p, SRC_DISP10, 24, 3),"mout_hdmi" , mout_hdmi_p, SRC_DISP10, 28, 1),"mout_fimd1_opt" , mout_group2_p, SRC_DISP10, 8, 3),"mout_fimd1_final" , mout_fimd1_final_p, TOP_SPARE2, 8, 1),/* CDREX block */ "mout_mclk_cdrex" , mout_mclk_cdrex_p,"mout_bpll" , mout_bpll_p, SRC_CDREX, 0, 1,/* MAU Block */ "mout_maudio0" , mout_maudio0_p, SRC_MAU, 28, 3),/* FSYS Block */ "mout_usbd301" , mout_group2_p, SRC_FSYS, 4, 3),"mout_mmc0" , mout_group2_p, SRC_FSYS, 8, 3),"mout_mmc1" , mout_group2_p, SRC_FSYS, 12, 3),"mout_mmc2" , mout_group2_p, SRC_FSYS, 16, 3),"mout_usbd300" , mout_group2_p, SRC_FSYS, 20, 3),"mout_unipro" , mout_group2_p, SRC_FSYS, 24, 3),"mout_mphy_refclk" , mout_group2_p, SRC_FSYS, 28, 3),/* PERIC Block */ "mout_uart0" , mout_group2_p, SRC_PERIC0, 4, 3),"mout_uart1" , mout_group2_p, SRC_PERIC0, 8, 3),"mout_uart2" , mout_group2_p, SRC_PERIC0, 12, 3),"mout_uart3" , mout_group2_p, SRC_PERIC0, 16, 3),"mout_pwm" , mout_group2_p, SRC_PERIC0, 24, 3),"mout_spdif" , mout_spdif_p, SRC_PERIC0, 28, 3),"mout_audio0" , mout_audio0_p, SRC_PERIC1, 8, 3),"mout_audio1" , mout_audio1_p, SRC_PERIC1, 12, 3),"mout_audio2" , mout_audio2_p, SRC_PERIC1, 16, 3),"mout_spi0" , mout_group2_p, SRC_PERIC1, 20, 3),"mout_spi1" , mout_group2_p, SRC_PERIC1, 24, 3),"mout_spi2" , mout_group2_p, SRC_PERIC1, 28, 3),/* ISP Block */ "mout_pwm_isp" , mout_group2_p, SRC_ISP, 24, 3),"mout_uart_isp" , mout_group2_p, SRC_ISP, 20, 3),"mout_spi0_isp" , mout_group2_p, SRC_ISP, 12, 3),"mout_spi1_isp" , mout_group2_p, SRC_ISP, 16, 3),"mout_isp_sensor" , mout_group2_p, SRC_ISP, 28, 3),static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {"div_arm" , "mout_cpu" , DIV_CPU0, 0, 3),"sclk_apll" , "mout_apll" , DIV_CPU0, 24, 3),"armclk2" , "div_arm" , DIV_CPU0, 28, 3),"div_kfc" , "mout_kfc" , DIV_KFC0, 0, 3),"sclk_kpll" , "mout_kpll" , DIV_KFC0, 24, 3),"dout_aclk400_isp" , "mout_aclk400_isp" ,"dout_aclk400_mscl" , "mout_aclk400_mscl" ,"dout_aclk200" , "mout_aclk200" ,"dout_aclk200_fsys2" , "mout_aclk200_fsys2" ,"dout_aclk100_noc" , "mout_aclk100_noc" ,"dout_pclk200_fsys" , "mout_pclk200_fsys" ,"dout_aclk200_fsys" , "mout_aclk200_fsys" ,"dout_aclk333_432_gscl" ,"mout_aclk333_432_gscl" , DIV_TOP1, 0, 3),"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , DIV_TOP1, 4, 3),"dout_aclk66" , "mout_aclk66" ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , DIV_TOP1, 16, 3),"dout_aclk266" , "mout_aclk266" ,"dout_aclk166" , "mout_aclk166" ,"dout_aclk333" , "mout_aclk333" ,"dout_aclk333_g2d" , "mout_aclk333_g2d" ,"dout_aclk266_g2d" , "mout_aclk266_g2d" ,"dout_aclk_g3d" , "mout_aclk_g3d" , DIV_TOP2,"dout_aclk300_jpeg" , "mout_aclk300_jpeg" ,"dout_aclk300_disp1" ,"mout_aclk300_disp1" , DIV_TOP2, 24, 3),"dout_aclk300_gscl" , "mout_aclk300_gscl" ,/* DISP1 Block */ "dout_fimd1" , "mout_fimd1_final" , DIV_DISP10, 0, 4),"dout_mipi1" , "mout_mipi1" , DIV_DISP10, 16, 8),"dout_dp1" , "mout_dp1" , DIV_DISP10, 24, 4),"dout_hdmi_pixel" , "mout_pixel" , DIV_DISP10, 28, 4),"dout_aclk400_disp1" ,"mout_aclk400_disp1" , DIV_TOP2, 4, 3),/* CDREX Block */ /* * The three clocks below are controlled using the same register and * bits. They are put into one because there is a need of * synchronization between the BUS and DREXs (two external memory * interfaces). * They are put here to show this HW assumption and for clock * information summary completeness. "dout_pclk_cdrex" , "dout_aclk_cdrex1" ,"dout_pclk_drex0" , "dout_cclk_drex0" ,"dout_pclk_drex1" , "dout_cclk_drex0" ,"dout_sclk_cdrex" , "mout_mclk_cdrex" ,"dout_aclk_cdrex1" , "dout_clk2x_phy0" ,"dout_cclk_drex0" , "dout_clk2x_phy0" ,"dout_clk2x_phy0" , "dout_sclk_cdrex" ,"dout_pclk_core_mem" , "mout_mclk_cdrex" ,/* Audio Block */ "dout_maudio0" , "mout_maudio0" , DIV_MAU, 20, 4),"dout_maupcm0" , "dout_maudio0" , DIV_MAU, 24, 8),/* USB3.0 */ "dout_usbphy301" , "mout_usbd301" , DIV_FSYS0, 12, 4),"dout_usbphy300" , "mout_usbd300" , DIV_FSYS0, 16, 4),"dout_usbd301" , "mout_usbd301" , DIV_FSYS0, 20, 4),"dout_usbd300" , "mout_usbd300" , DIV_FSYS0, 24, 4),/* MMC */ "dout_mmc0" , "mout_mmc0" , DIV_FSYS1, 0, 10),"dout_mmc1" , "mout_mmc1" , DIV_FSYS1, 10, 10),"dout_mmc2" , "mout_mmc2" , DIV_FSYS1, 20, 10),"dout_unipro" , "mout_unipro" , DIV_FSYS2, 24, 8),"dout_mphy_refclk" , "mout_mphy_refclk" , DIV_FSYS2, 16, 8),/* UART and PWM */ "dout_uart0" , "mout_uart0" , DIV_PERIC0, 8, 4),"dout_uart1" , "mout_uart1" , DIV_PERIC0, 12, 4),"dout_uart2" , "mout_uart2" , DIV_PERIC0, 16, 4),"dout_uart3" , "mout_uart3" , DIV_PERIC0, 20, 4),"dout_pwm" , "mout_pwm" , DIV_PERIC0, 28, 4),/* SPI */ "dout_spi0" , "mout_spi0" , DIV_PERIC1, 20, 4),"dout_spi1" , "mout_spi1" , DIV_PERIC1, 24, 4),"dout_spi2" , "mout_spi2" , DIV_PERIC1, 28, 4),/* PCM */ "dout_pcm1" , "dout_audio1" , DIV_PERIC2, 16, 8),"dout_pcm2" , "dout_audio2" , DIV_PERIC2, 24, 8),/* Audio - I2S */ "dout_i2s1" , "dout_audio1" , DIV_PERIC3, 6, 6),"dout_i2s2" , "dout_audio2" , DIV_PERIC3, 12, 6),"dout_audio0" , "mout_audio0" , DIV_PERIC3, 20, 4),"dout_audio1" , "mout_audio1" , DIV_PERIC3, 24, 4),"dout_audio2" , "mout_audio2" , DIV_PERIC3, 28, 4),/* SPI Pre-Ratio */ "dout_spi0_pre" , "dout_spi0" , DIV_PERIC4, 8, 8),"dout_spi1_pre" , "dout_spi1" , DIV_PERIC4, 16, 8),"dout_spi2_pre" , "dout_spi2" , DIV_PERIC4, 24, 8),/* GSCL Block */ "dout_gscl_blk_333" , "aclk333_432_gscl" , DIV2_RATIO0, 6, 2),/* PSGEN */ "dout_gen_blk" , "mout_user_aclk266" , DIV2_RATIO0, 8, 1),"dout_jpg_blk" , "aclk166" , DIV2_RATIO0, 20, 1),/* ISP Block */ "dout_isp_sensor0" , "mout_isp_sensor" , SCLK_DIV_ISP0, 8, 8),"dout_isp_sensor1" , "mout_isp_sensor" , SCLK_DIV_ISP0, 16, 8),"dout_isp_sensor2" , "mout_isp_sensor" , SCLK_DIV_ISP0, 24, 8),"dout_pwm_isp" , "mout_pwm_isp" , SCLK_DIV_ISP1, 28, 4),"dout_uart_isp" , "mout_uart_isp" , SCLK_DIV_ISP1, 24, 4),"dout_spi0_isp" , "mout_spi0_isp" , SCLK_DIV_ISP1, 16, 4),"dout_spi1_isp" , "mout_spi1_isp" , SCLK_DIV_ISP1, 20, 4),"dout_spi0_isp_pre" , "dout_spi0_isp" , SCLK_DIV_ISP1, 0, 8,"dout_spi1_isp_pre" , "dout_spi1_isp" , SCLK_DIV_ISP1, 8, 8,static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {/* G2D */ "mdma0" , "aclk266_g2d" , GATE_IP_G2D, 1, 0, 0),"sss" , "aclk266_g2d" , GATE_IP_G2D, 2, 0, 0),"g2d" , "aclk333_g2d" , GATE_IP_G2D, 3, 0, 0),"smmu_mdma0" , "aclk266_g2d" , GATE_IP_G2D, 5, 0, 0),"smmu_g2d" , "aclk333_g2d" , GATE_IP_G2D, 7, 0, 0),"aclk200_fsys" , "mout_user_aclk200_fsys" ,"aclk200_fsys2" , "mout_user_aclk200_fsys2" ,"aclk333_g2d" , "mout_user_aclk333_g2d" ,"aclk266_g2d" , "mout_user_aclk266_g2d" ,"aclk300_jpeg" , "mout_user_aclk300_jpeg" ,"aclk333_432_isp0" , "mout_user_aclk333_432_isp0" ,"aclk300_gscl" , "mout_user_aclk300_gscl" ,"aclk333_432_gscl" , "mout_user_aclk333_432_gscl" ,"aclk333_432_isp" , "mout_user_aclk333_432_isp" ,"pclk66_gpio" , "mout_user_pclk66_gpio" ,"aclk66_psgen" , "mout_user_aclk66_psgen" ,"aclk266_isp" , "mout_user_aclk266_isp" ,"aclk166" , "mout_user_aclk166" ,"aclk333" , "mout_user_aclk333" ,"aclk400_isp" , "mout_user_aclk400_isp" ,"aclk400_mscl" , "mout_user_aclk400_mscl" ,"aclk200_disp1" , "mout_user_aclk200_disp1" ,"sclk_mphy_ixtal24" , "mphy_refclk_ixtal24" ,"sclk_hsic_12m" , "ff_hsic_12m" ,"aclk300_disp1" , "mout_user_aclk300_disp1" ,/* sclk */ "sclk_uart0" , "dout_uart0" ,"sclk_uart1" , "dout_uart1" ,"sclk_uart2" , "dout_uart2" ,"sclk_uart3" , "dout_uart3" ,"sclk_spi0" , "dout_spi0_pre" ,"sclk_spi1" , "dout_spi1_pre" ,"sclk_spi2" , "dout_spi2_pre" ,"sclk_spdif" , "mout_spdif" ,"sclk_pwm" , "dout_pwm" ,"sclk_pcm1" , "dout_pcm1" ,"sclk_pcm2" , "dout_pcm2" ,"sclk_i2s1" , "dout_i2s1" ,"sclk_i2s2" , "dout_i2s2" ,"sclk_mmc0" , "dout_mmc0" ,"sclk_mmc1" , "dout_mmc1" ,"sclk_mmc2" , "dout_mmc2" ,"sclk_usbphy301" , "dout_usbphy301" ,"sclk_usbphy300" , "dout_usbphy300" ,"sclk_usbd300" , "dout_usbd300" ,"sclk_usbd301" , "dout_usbd301" ,/* Display */ "sclk_fimd1" , "dout_fimd1" ,"sclk_mipi1" , "dout_mipi1" ,"sclk_hdmi" , "mout_hdmi" ,"sclk_pixel" , "dout_hdmi_pixel" ,"sclk_dp1" , "dout_dp1" ,/* FSYS Block */ "tsi" , "aclk200_fsys" , GATE_BUS_FSYS0, 0, 0, 0),"pdma0" , "aclk200_fsys" , GATE_BUS_FSYS0, 1, 0, 0),"pdma1" , "aclk200_fsys" , GATE_BUS_FSYS0, 2, 0, 0),"ufs" , "aclk200_fsys2" , GATE_BUS_FSYS0, 3, 0, 0),"rtic" , "aclk200_fsys" , GATE_IP_FSYS, 9, 0, 0),"mmc0" , "aclk200_fsys2" , GATE_IP_FSYS, 12, 0, 0),"mmc1" , "aclk200_fsys2" , GATE_IP_FSYS, 13, 0, 0),"mmc2" , "aclk200_fsys2" , GATE_IP_FSYS, 14, 0, 0),"sromc" , "aclk200_fsys2" ,"usbh20" , "aclk200_fsys" , GATE_IP_FSYS, 18, 0, 0),"usbd300" , "aclk200_fsys" , GATE_IP_FSYS, 19, 0, 0),"usbd301" , "aclk200_fsys" , GATE_IP_FSYS, 20, 0, 0),"sclk_unipro" , "dout_unipro" ,/* PERIC Block */ "uart0" , "mout_user_aclk66_peric" ,"uart1" , "mout_user_aclk66_peric" ,"uart2" , "mout_user_aclk66_peric" ,"uart3" , "mout_user_aclk66_peric" ,"i2c0" , "mout_user_aclk66_peric" ,"i2c1" , "mout_user_aclk66_peric" ,"i2c2" , "mout_user_aclk66_peric" ,"i2c3" , "mout_user_aclk66_peric" ,"usi0" , "mout_user_aclk66_peric" ,"usi1" , "mout_user_aclk66_peric" ,"usi2" , "mout_user_aclk66_peric" ,"usi3" , "mout_user_aclk66_peric" ,"i2c_hdmi" , "mout_user_aclk66_peric" ,"tsadc" , "mout_user_aclk66_peric" ,"spi0" , "mout_user_aclk66_peric" ,"spi1" , "mout_user_aclk66_peric" ,"spi2" , "mout_user_aclk66_peric" ,"i2s1" , "mout_user_aclk66_peric" ,"i2s2" , "mout_user_aclk66_peric" ,"pcm1" , "mout_user_aclk66_peric" ,"pcm2" , "mout_user_aclk66_peric" ,"pwm" , "mout_user_aclk66_peric" ,"spdif" , "mout_user_aclk66_peric" ,"usi4" , "mout_user_aclk66_peric" ,"usi5" , "mout_user_aclk66_peric" ,"usi6" , "mout_user_aclk66_peric" ,"keyif" , "mout_user_aclk66_peric" ,/* PERIS Block */ "chipid" , "aclk66_psgen" ,"sysreg" , "aclk66_psgen" ,"tzpc0" , "aclk66_psgen" , GATE_IP_PERIS, 6, 0, 0),"tzpc1" , "aclk66_psgen" , GATE_IP_PERIS, 7, 0, 0),"tzpc2" , "aclk66_psgen" , GATE_IP_PERIS, 8, 0, 0),"tzpc3" , "aclk66_psgen" , GATE_IP_PERIS, 9, 0, 0),"tzpc4" , "aclk66_psgen" , GATE_IP_PERIS, 10, 0, 0),"tzpc5" , "aclk66_psgen" , GATE_IP_PERIS, 11, 0, 0),"tzpc6" , "aclk66_psgen" , GATE_IP_PERIS, 12, 0, 0),"tzpc7" , "aclk66_psgen" , GATE_IP_PERIS, 13, 0, 0),"tzpc8" , "aclk66_psgen" , GATE_IP_PERIS, 14, 0, 0),"tzpc9" , "aclk66_psgen" , GATE_IP_PERIS, 15, 0, 0),"hdmi_cec" , "aclk66_psgen" , GATE_IP_PERIS, 16, 0, 0),"mct" , "aclk66_psgen" , GATE_IP_PERIS, 18, 0, 0),"wdt" , "aclk66_psgen" , GATE_IP_PERIS, 19, 0, 0),"rtc" , "aclk66_psgen" , GATE_IP_PERIS, 20, 0, 0),"tmu" , "aclk66_psgen" , GATE_IP_PERIS, 21, 0, 0),"tmu_gpu" , "aclk66_psgen" , GATE_IP_PERIS, 22, 0, 0),/* GEN Block */ "rotator" , "mout_user_aclk266" , GATE_IP_GEN, 1, 0, 0),"jpeg" , "aclk300_jpeg" , GATE_IP_GEN, 2, 0, 0),"jpeg2" , "aclk300_jpeg" , GATE_IP_GEN, 3, 0, 0),"mdma1" , "mout_user_aclk266" , GATE_IP_GEN, 4, 0, 0),"top_rtc" , "aclk66_psgen" , GATE_IP_GEN, 5, 0, 0),"smmu_rotator" , "dout_gen_blk" ,"smmu_jpeg" , "dout_jpg_blk" , GATE_IP_GEN, 7, 0, 0),"smmu_mdma1" , "dout_gen_blk" ,/* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ "smmu_jpeg2" , "dout_jpg_blk" ,"mc" , "aclk66_psgen" , GATE_BUS_GEN, 12, 0, 0),/* GSCL Block */ "sclk_gscl_wa" , "mout_user_aclk333_432_gscl" ,"sclk_gscl_wb" , "mout_user_aclk333_432_gscl" ,"fimc_3aa" , "aclk333_432_gscl" ,"fimc_lite0" , "aclk333_432_gscl" ,"fimc_lite1" , "aclk333_432_gscl" ,"smmu_3aa" , "dout_gscl_blk_333" ,"smmu_fimcl0" , "dout_gscl_blk_333" ,"smmu_fimcl1" , "dout_gscl_blk_333" ,"gscl_wa" , "sclk_gscl_wa" , GATE_IP_GSCL1, 12,"gscl_wb" , "sclk_gscl_wb" , GATE_IP_GSCL1, 13,"smmu_fimcl3" , "dout_gscl_blk_333" ,"fimc_lite3" , "aclk333_432_gscl" ,/* ISP */ "sclk_uart_isp" , "dout_uart_isp" ,"sclk_spi0_isp" , "dout_spi0_isp_pre" ,"sclk_spi1_isp" , "dout_spi1_isp_pre" ,"sclk_pwm_isp" , "dout_pwm_isp" ,"sclk_isp_sensor0" , "dout_isp_sensor0" ,"sclk_isp_sensor1" , "dout_isp_sensor1" ,"sclk_isp_sensor2" , "dout_isp_sensor2" ,/* CDREX */ "clkm_phy0" , "dout_sclk_cdrex" ,"clkm_phy1" , "dout_sclk_cdrex" ,"mx_mspll_ccore_phy" , "mout_mx_mspll_ccore_phy" ,"aclk_ppmu_drex1_1" , "dout_aclk_cdrex1" ,"aclk_ppmu_drex1_0" , "dout_aclk_cdrex1" ,"aclk_ppmu_drex0_1" , "dout_aclk_cdrex1" ,"aclk_ppmu_drex0_0" , "dout_aclk_cdrex1" ,"pclk_ppmu_drex1_1" , "dout_pclk_cdrex" ,"pclk_ppmu_drex1_0" , "dout_pclk_cdrex" ,"pclk_ppmu_drex0_1" , "dout_pclk_cdrex" ,"pclk_ppmu_drex0_0" , "dout_pclk_cdrex" ,static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {"dout_disp1_blk" , "aclk200_disp1" , DIV2_RATIO0, 16, 2),static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {"fimd1" , "aclk300_disp1" , GATE_IP_DISP1, 0, 0, 0),"dsim1" , "aclk200_disp1" , GATE_IP_DISP1, 3, 0, 0),"dp1" , "aclk200_disp1" , GATE_IP_DISP1, 4, 0, 0),"mixer" , "aclk200_disp1" , GATE_IP_DISP1, 5, 0, 0),"hdmi" , "aclk200_disp1" , GATE_IP_DISP1, 6, 0, 0),"smmu_fimd1m0" , "dout_disp1_blk" ,"smmu_fimd1m1" , "dout_disp1_blk" ,"smmu_mixer" , "aclk200_disp1" ,static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {/* DISP1 gates */ /* MUX mout_user_aclk400_disp1 */ /* MUX mout_user_aclk300_disp1 */ /* MUX mout_user_aclk200_disp1 */ /* DIV dout_disp1_blk */ static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {"dout_gscl_blk_300" , "mout_user_aclk300_gscl" ,static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {"gscl0" , "aclk300_gscl" , GATE_IP_GSCL0, 0, 0, 0),"gscl1" , "aclk300_gscl" , GATE_IP_GSCL0, 1, 0, 0),"smmu_gscl0" , "dout_gscl_blk_300" ,"smmu_gscl1" , "dout_gscl_blk_300" ,static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {/* GSC gates */ /* GSC gates */ /* MUX mout_user_aclk300_gscl */ /* DIV dout_gscl_blk_300 */ static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {"g3d" , "mout_user_aclk_g3d" , GATE_IP_G3D, 9,static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {/* G3D gates */ /* MUX mout_user_aclk_g3d */ static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {"dout_mfc_blk" , "mout_user_aclk333" , DIV4_RATIO, 0, 2),static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {"mfc" , "aclk333" , GATE_IP_MFC, 0, 0, 0),"smmu_mfcl" , "dout_mfc_blk" , GATE_IP_MFC, 1, 0, 0),"smmu_mfcr" , "dout_mfc_blk" , GATE_IP_MFC, 2, 0, 0),static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {/* MFC gates */ /* MUX mout_user_aclk333 */ /* DIV dout_mfc_blk */ static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {/* MSCL Block */ "mscl0" , "aclk400_mscl" , GATE_IP_MSCL, 0, 0, 0),"mscl1" , "aclk400_mscl" , GATE_IP_MSCL, 1, 0, 0),"mscl2" , "aclk400_mscl" , GATE_IP_MSCL, 2, 0, 0),"smmu_mscl0" , "dout_mscl_blk" ,"smmu_mscl1" , "dout_mscl_blk" ,"smmu_mscl2" , "dout_mscl_blk" ,static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {"dout_mscl_blk" , "aclk400_mscl" , DIV2_RATIO0, 28, 2),static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {/* MSCL gates */ /* MUX mout_user_aclk400_mscl */ /* DIV dout_mscl_blk */ static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {"mau_epll" , "mout_user_mau_epll" ,"sclk_maudio0" , "dout_maudio0" ,"sclk_maupcm0" , "dout_maupcm0" ,static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {/* MUX mout_user_mau_epll */ static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {"DISP" ,static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {"GSC" ,static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {"G3D" ,static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {"MFC" ,static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {"MSC" ,static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {"MAU" ,static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {"fout_apll" , "fin_pll" , APLL_LOCK,"fout_cpll" , "fin_pll" , CPLL_LOCK,"fout_dpll" , "fin_pll" , DPLL_LOCK,"fout_epll" , "fin_pll" , EPLL_LOCK,"fout_rpll" , "fin_pll" , RPLL_LOCK,"fout_ipll" , "fin_pll" , IPLL_LOCK,"fout_spll" , "fin_pll" , SPLL_LOCK,"fout_vpll" , "fin_pll" , VPLL_LOCK,"fout_mpll" , "fin_pll" , MPLL_LOCK,"fout_bpll" , "fin_pll" , BPLL_LOCK,"fout_kpll" , "fin_pll" , KPLL_LOCK,#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {#define E5420_KFC_DIV(kpll, pclk, aclk) \static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {/* for Exynos5800 */ static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {"armclk" , CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,"kfcclk" , CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {"armclk" , CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,"kfcclk" , CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,static const struct of_device_id ext_clk_match[] __initconst = {"samsung,exynos5420-oscclk" , .data = (void *)0, },/* register exynos5420 clocks */ static void __init exynos5x_clk_init(struct device_node *np,enum exynos5x_soc soc)struct samsung_clk_provider *ctx;struct clk_hw **hws;if (np) {if (!reg_base)"%s: failed to map registers\n" , __func__);else {"%s: unable to determine soc\n" , __func__);if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {if (soc == EXYNOS5420)else if (soc == EXYNOS5420) {else {if (soc == EXYNOS5420) {else {if (soc == EXYNOS5800) {
Messung V0.5 C=97 H=95 G=95
¤ Dauer der Verarbeitung: 0.19 Sekunden
(vorverarbeitet)
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