// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Chanwoo Choi <cw00.choi@samsung.com> * * Common Clock Framework support for Exynos5433 SoC. #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/slab.h>#include <dt-bindings/clock/exynos5433.h>#include "clk.h" #include "clk-cpu.h" #include "clk-exynos-arm64.h" #include "clk-pll.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1)#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1)#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1)#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1)#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1)#define CLKS_NR_FSYS (CLK_PCIE + 1)#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1)#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1)#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1)#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1)#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1)#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1)#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1)#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1)#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1)#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1)#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1)#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1)#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1)/* * Register offset definitions for CMU_TOP #define ISP_PLL_LOCK 0x0000#define AUD_PLL_LOCK 0x0004#define ISP_PLL_CON0 0x0100#define ISP_PLL_CON1 0x0104#define ISP_PLL_FREQ_DET 0x0108#define AUD_PLL_CON0 0x0110#define AUD_PLL_CON1 0x0114#define AUD_PLL_CON2 0x0118#define AUD_PLL_FREQ_DET 0x011c#define MUX_SEL_TOP0 0x0200#define MUX_SEL_TOP1 0x0204#define MUX_SEL_TOP2 0x0208#define MUX_SEL_TOP3 0x020c#define MUX_SEL_TOP4 0x0210#define MUX_SEL_TOP_MSCL 0x0220#define MUX_SEL_TOP_CAM1 0x0224#define MUX_SEL_TOP_DISP 0x0228#define MUX_SEL_TOP_FSYS0 0x0230#define MUX_SEL_TOP_FSYS1 0x0234#define MUX_SEL_TOP_PERIC0 0x0238#define MUX_SEL_TOP_PERIC1 0x023c#define MUX_ENABLE_TOP0 0x0300#define MUX_ENABLE_TOP1 0x0304#define MUX_ENABLE_TOP2 0x0308#define MUX_ENABLE_TOP3 0x030c#define MUX_ENABLE_TOP4 0x0310#define MUX_ENABLE_TOP_MSCL 0x0320#define MUX_ENABLE_TOP_CAM1 0x0324#define MUX_ENABLE_TOP_DISP 0x0328#define MUX_ENABLE_TOP_FSYS0 0x0330#define MUX_ENABLE_TOP_FSYS1 0x0334#define MUX_ENABLE_TOP_PERIC0 0x0338#define MUX_ENABLE_TOP_PERIC1 0x033c#define MUX_STAT_TOP0 0x0400#define MUX_STAT_TOP1 0x0404#define MUX_STAT_TOP2 0x0408#define MUX_STAT_TOP3 0x040c#define MUX_STAT_TOP4 0x0410#define MUX_STAT_TOP_MSCL 0x0420#define MUX_STAT_TOP_CAM1 0x0424#define MUX_STAT_TOP_FSYS0 0x0430#define MUX_STAT_TOP_FSYS1 0x0434#define MUX_STAT_TOP_PERIC0 0x0438#define MUX_STAT_TOP_PERIC1 0x043c#define DIV_TOP0 0x0600#define DIV_TOP1 0x0604#define DIV_TOP2 0x0608#define DIV_TOP3 0x060c#define DIV_TOP4 0x0610#define DIV_TOP_MSCL 0x0618#define DIV_TOP_CAM10 0x061c#define DIV_TOP_CAM11 0x0620#define DIV_TOP_FSYS0 0x062c#define DIV_TOP_FSYS1 0x0630#define DIV_TOP_FSYS2 0x0634#define DIV_TOP_PERIC0 0x0638#define DIV_TOP_PERIC1 0x063c#define DIV_TOP_PERIC2 0x0640#define DIV_TOP_PERIC3 0x0644#define DIV_TOP_PERIC4 0x0648#define DIV_TOP_PLL_FREQ_DET 0x064c#define DIV_STAT_TOP0 0x0700#define DIV_STAT_TOP1 0x0704#define DIV_STAT_TOP2 0x0708#define DIV_STAT_TOP3 0x070c#define DIV_STAT_TOP4 0x0710#define DIV_STAT_TOP_MSCL 0x0718#define DIV_STAT_TOP_CAM10 0x071c#define DIV_STAT_TOP_CAM11 0x0720#define DIV_STAT_TOP_FSYS0 0x072c#define DIV_STAT_TOP_FSYS1 0x0730#define DIV_STAT_TOP_FSYS2 0x0734#define DIV_STAT_TOP_PERIC0 0x0738#define DIV_STAT_TOP_PERIC1 0x073c#define DIV_STAT_TOP_PERIC2 0x0740#define DIV_STAT_TOP_PERIC3 0x0744#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c#define ENABLE_ACLK_TOP 0x0800#define ENABLE_SCLK_TOP 0x0a00#define ENABLE_SCLK_TOP_MSCL 0x0a04#define ENABLE_SCLK_TOP_CAM1 0x0a08#define ENABLE_SCLK_TOP_DISP 0x0a0c#define ENABLE_SCLK_TOP_FSYS 0x0a10#define ENABLE_SCLK_TOP_PERIC 0x0a14#define ENABLE_IP_TOP 0x0b00#define ENABLE_CMU_TOP 0x0c00#define ENABLE_CMU_TOP_DIV_STAT 0x0c04static const unsigned long top_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump top_suspend_regs[] = {/* force all aclk clocks enabled */ /* force all sclk_uart clocks enabled */ /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ /* list of all parent clock list */ "oscclk" , "fout_aud_pll" , };"oscclk" , "fout_isp_pll" , };"oscclk" , "mout_aud_pll" , };"oscclk" , "sclk_mphy_pll" , };"oscclk" , "sclk_mfc_pll" , };"oscclk" , "sclk_bus_pll" , };"oscclk" , "mout_bus_pll_user" , };"oscclk" , "mout_mphy_pll_user" , };"mout_bus_pll_user" , "mout_mfc_pll_user" ,};"mout_mfc_pll_user" , "mout_bus_pll_user" ,};"mout_aclk_cam1_552_a" ,"mout_mfc_pll_user" , };"mout_isp_pll" , "mout_bus_pll_user" , };"mout_aclk_mfc_400_b" ,"mout_mphy_pll_user" , };"mout_aclk_mfc_400_a" ,"mout_bus_pll_user" , };"mout_mfc_pll_user" , "mout_isp_pll" , };"mout_bus_pll_user" ,"mout_mphy_pll_user" , };"mout_aclk_mscl_400_a" ,"mout_mphy_pll_user" , };"mout_aclk_g2d_400_a" ,"mout_mphy_pll_user" , };"mout_sclk_jpeg_b" , "mout_mphy_pll_user" ,};"mout_sclk_jpeg_a" , "mout_mfc_pll_user" , };"mout_sclk_mmc2_a" , "mout_mfc_pll_user" ,};"mout_sclk_mmc1_a" , "mout_mfc_pll_user" ,};"mout_sclk_mmc0_c" , "mout_isp_pll" , };"mout_sclk_mmc0_b" , "mout_mphy_pll_user" ,};"mout_sclk_mmc0_a" , "mout_mfc_pll_user" , };"sclk_audio0" , "sclk_audio1" ,"oscclk" , "ioclk_spdif_extclk" , };"ioclk_audiocdclk1" , "oscclk" ,"mout_aud_pll_user_t" ,};"ioclk_audiocdclk0" , "oscclk" ,"mout_aud_pll_user_t" ,};"sclk_audio1" , "ioclk_spdif_extclk" , };static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {"oscclk_efuse_common" , "oscclk" , 1, 1, 0),static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {/* Xi2s{0|1}CDCLK input clock for I2S/PCM */ "ioclk_audiocdclk1" , NULL, 0, 100000000),"ioclk_audiocdclk0" , NULL, 0, 100000000),/* Xi2s1SDI input clock for SPDIF */ "ioclk_spdif_extclk" , NULL, 0, 100000000),/* XspiCLK[4:0] input clock for SPI */ "ioclk_spi4_clk_in" , NULL, 0, 50000000),"ioclk_spi3_clk_in" , NULL, 0, 50000000),"ioclk_spi2_clk_in" , NULL, 0, 50000000),"ioclk_spi1_clk_in" , NULL, 0, 50000000),"ioclk_spi0_clk_in" , NULL, 0, 50000000),/* Xi2s1SCLK input clock for I2S1_BCLK */ "ioclk_i2s1_bclk_in" , NULL, 0, 12288000),static const struct samsung_mux_clock top_mux_clks[] __initconst = {/* MUX_SEL_TOP0 */ "mout_aud_pll" , mout_aud_pll_p, MUX_SEL_TOP0,"mout_isp_pll" , mout_isp_pll_p, MUX_SEL_TOP0,/* MUX_SEL_TOP1 */ "mout_aud_pll_user_t" ,"mout_mphy_pll_user" , mout_mphy_pll_user_p,"mout_mfc_pll_user" , mout_mfc_pll_user_p,"mout_bus_pll_user" , mout_bus_pll_user_p,/* MUX_SEL_TOP2 */ "mout_aclk_hevc_400" ,"mout_aclk_cam1_333" ,"mout_aclk_cam1_552_b" ,"mout_aclk_cam1_552_a" ,"mout_aclk_isp_dis_400" ,"mout_aclk_isp_400" ,/* MUX_SEL_TOP3 */ "mout_aclk_bus0_400" ,"mout_aclk_mscl_400_b" ,"mout_aclk_mscl_400_a" ,"mout_aclk_gscl_333" ,"mout_aclk_g2d_400_b" ,"mout_aclk_g2d_400_a" ,/* MUX_SEL_TOP4 */ "mout_aclk_mfc_400_c" ,"mout_aclk_mfc_400_b" ,"mout_aclk_mfc_400_a" ,/* MUX_SEL_TOP_MSCL */ "mout_sclk_jpeg_c" , mout_sclk_jpeg_c_p,"mout_sclk_jpeg_b" , mout_sclk_jpeg_b_p,"mout_sclk_jpeg_a" , mout_bus_pll_user_t_p,/* MUX_SEL_TOP_CAM1 */ "mout_sclk_isp_sensor2" ,"mout_sclk_isp_sensor1" ,"mout_sclk_isp_sensor0" ,"mout_sclk_isp_uart" ,"mout_sclk_isp_spi1" ,"mout_sclk_isp_spi0" ,/* MUX_SEL_TOP_FSYS0 */ "mout_sclk_mmc2_b" , mout_sclk_mmc2_b_p,"mout_sclk_mmc2_a" , mout_bus_pll_user_t_p,"mout_sclk_mmc1_b" , mout_sclk_mmc1_b_p,"mout_sclk_mmc1_a" , mout_bus_pll_user_t_p,"mout_sclk_mmc0_d" , mout_sclk_mmc0_d_p,"mout_sclk_mmc0_c" , mout_sclk_mmc0_c_p,"mout_sclk_mmc0_b" , mout_sclk_mmc0_b_p,"mout_sclk_mmc0_a" , mout_bus_pll_user_t_p,/* MUX_SEL_TOP_FSYS1 */ "mout_sclk_pcie_100" , mout_bus_pll_user_t_p,"mout_sclk_ufsunipro" ,"mout_sclk_usbhost30" ,"mout_sclk_usbdrd30" ,/* MUX_SEL_TOP_PERIC0 */ "mout_sclk_spi4" , mout_bus_pll_user_t_p,"mout_sclk_spi3" , mout_bus_pll_user_t_p,"mout_sclk_uart2" , mout_bus_pll_user_t_p,"mout_sclk_uart1" , mout_bus_pll_user_t_p,"mout_sclk_uart0" , mout_bus_pll_user_t_p,"mout_sclk_spi2" , mout_bus_pll_user_t_p,"mout_sclk_spi1" , mout_bus_pll_user_t_p,"mout_sclk_spi0" , mout_bus_pll_user_t_p,/* MUX_SEL_TOP_PERIC1 */ "mout_sclk_slimbus" , mout_aud_pll_user_p,"mout_sclk_spdif" , mout_sclk_spdif_p,"mout_sclk_audio1" , mout_sclk_audio1_p,"mout_sclk_audio0" , mout_sclk_audio0_p,/* MUX_SEL_TOP_DISP */ "mout_sclk_hdmi_spdif" ,static const struct samsung_div_clock top_div_clks[] __initconst = {/* DIV_TOP0 */ "div_aclk_cam1_333" , "mout_aclk_cam1_333" ,"div_aclk_cam1_400" , "mout_bus_pll_user" ,"div_aclk_cam1_552" , "mout_aclk_cam1_552_b" ,"div_aclk_cam0_333" , "mout_mfc_pll_user" ,"div_aclk_cam0_400" , "mout_bus_pll_user" ,"div_aclk_cam0_552" , "mout_isp_pll" ,"div_aclk_isp_dis_400" ,"mout_aclk_isp_dis_400" , DIV_TOP0, 4, 4),"div_aclk_isp_400" ,"mout_aclk_isp_400" , DIV_TOP0, 0, 4),/* DIV_TOP1 */ "div_aclk_gscl_111" , "mout_aclk_gscl_333" ,"div_aclk_gscl_333" , "mout_aclk_gscl_333" ,"div_aclk_hevc_400" , "mout_aclk_hevc_400" ,"div_aclk_mfc_400" , "mout_aclk_mfc_400_c" ,"div_aclk_g2d_266" , "mout_bus_pll_user" ,"div_aclk_g2d_400" , "mout_aclk_g2d_400_b" ,/* DIV_TOP2 */ "div_aclk_mscl_400" , "mout_aclk_mscl_400_b" ,"div_aclk_fsys_200" , "mout_bus_pll_user" ,/* DIV_TOP3 */ "div_aclk_imem_sssx_266" ,"mout_bus_pll_user" , DIV_TOP3, 24, 3),"div_aclk_imem_200" ,"mout_bus_pll_user" , DIV_TOP3, 20, 3),"div_aclk_imem_266" ,"mout_bus_pll_user" , DIV_TOP3, 16, 3),"div_aclk_peric_66_b" ,"div_aclk_peric_66_a" , DIV_TOP3, 12, 3),"div_aclk_peric_66_a" ,"mout_bus_pll_user" , DIV_TOP3, 8, 3),"div_aclk_peris_66_b" ,"div_aclk_peris_66_a" , DIV_TOP3, 4, 3),"div_aclk_peris_66_a" ,"mout_bus_pll_user" , DIV_TOP3, 0, 3),/* DIV_TOP4 */ "div_aclk_g3d_400" , "mout_bus_pll_user" ,"div_aclk_bus0_400" , "mout_aclk_bus0_400" ,"div_aclk_bus1_400" , "mout_bus_pll_user" ,/* DIV_TOP_MSCL */ "div_sclk_jpeg" , "mout_sclk_jpeg_c" ,/* DIV_TOP_CAM10 */ "div_sclk_isp_uart" , "mout_sclk_isp_uart" ,"div_sclk_isp_spi1_b" ,"div_sclk_isp_spi1_a" , DIV_TOP_CAM10, 16, 8),"div_sclk_isp_spi1_a" ,"mout_sclk_isp_spi1" , DIV_TOP_CAM10, 12, 4),"div_sclk_isp_spi0_b" ,"div_sclk_isp_spi0_a" , DIV_TOP_CAM10, 4, 8),"div_sclk_isp_spi0_a" ,"mout_sclk_isp_spi0" , DIV_TOP_CAM10, 0, 4),/* DIV_TOP_CAM11 */ "div_sclk_isp_sensor2_b" ,"div_sclk_isp_sensor2_a" , DIV_TOP_CAM11, 20, 4),"div_sclk_isp_sensor2_a" ,"mout_sclk_isp_sensor2" , DIV_TOP_CAM11, 16, 4),"div_sclk_isp_sensor1_b" ,"div_sclk_isp_sensor1_a" , DIV_TOP_CAM11, 12, 4),"div_sclk_isp_sensor1_a" ,"mout_sclk_isp_sensor1" , DIV_TOP_CAM11, 8, 4),"div_sclk_isp_sensor0_b" ,"div_sclk_isp_sensor0_a" , DIV_TOP_CAM11, 4, 4),"div_sclk_isp_sensor0_a" ,"mout_sclk_isp_sensor0" , DIV_TOP_CAM11, 0, 4),/* DIV_TOP_FSYS0 */ "div_sclk_mmc1_b" , "div_sclk_mmc1_a" ,"div_sclk_mmc1_a" , "mout_sclk_mmc1_b" ,"div_sclk_mmc0_b" , "div_sclk_mmc0_a" ,"div_sclk_mmc0_a" , "mout_sclk_mmc0_d" ,/* DIV_TOP_FSYS1 */ "div_sclk_mmc2_b" , "div_sclk_mmc2_a" ,"div_sclk_mmc2_a" , "mout_sclk_mmc2_b" ,/* DIV_TOP_FSYS2 */ "div_sclk_pcie_100" , "mout_sclk_pcie_100" ,"div_sclk_usbhost30" ,"mout_sclk_usbhost30" , DIV_TOP_FSYS2, 8, 4),"div_sclk_ufsunipro" ,"mout_sclk_ufsunipro" , DIV_TOP_FSYS2, 4, 4),"div_sclk_usbdrd30" , "mout_sclk_usbdrd30" ,/* DIV_TOP_PERIC0 */ "div_sclk_spi1_b" , "div_sclk_spi1_a" ,"div_sclk_spi1_a" , "mout_sclk_spi1" ,"div_sclk_spi0_b" , "div_sclk_spi0_a" ,"div_sclk_spi0_a" , "mout_sclk_spi0" ,/* DIV_TOP_PERIC1 */ "div_sclk_spi2_b" , "div_sclk_spi2_a" ,"div_sclk_spi2_a" , "mout_sclk_spi2" ,/* DIV_TOP_PERIC2 */ "div_sclk_uart2" , "mout_sclk_uart2" ,"div_sclk_uart1" , "mout_sclk_uart0" ,"div_sclk_uart0" , "mout_sclk_uart1" ,/* DIV_TOP_PERIC3 */ "div_sclk_i2s1" , "sclk_audio1" ,"div_sclk_pcm1" , "sclk_audio1" ,"div_sclk_audio1" , "mout_sclk_audio1" ,"div_sclk_audio0" , "mout_sclk_audio0" ,/* DIV_TOP_PERIC4 */ "div_sclk_spi4_b" , "div_sclk_spi4_a" ,"div_sclk_spi4_a" , "mout_sclk_spi4" ,"div_sclk_spi3_b" , "div_sclk_spi3_a" ,"div_sclk_spi3_a" , "mout_sclk_spi3" ,static const struct samsung_gate_clock top_gate_clks[] __initconst = {/* ENABLE_ACLK_TOP */ "aclk_g3d_400" , "div_aclk_g3d_400" ,"aclk_imem_sssx_266" ,"div_aclk_imem_sssx_266" , ENABLE_ACLK_TOP,"aclk_bus0_400" , "div_aclk_bus0_400" ,"aclk_bus1_400" , "div_aclk_bus1_400" ,"aclk_imem_200" , "div_aclk_imem_200" ,"aclk_imem_266" , "div_aclk_imem_266" ,"aclk_peric_66" , "div_aclk_peric_66_b" ,"aclk_peris_66" , "div_aclk_peris_66_b" ,"aclk_mscl_400" , "div_aclk_mscl_400" ,"aclk_fsys_200" , "div_aclk_fsys_200" ,"aclk_gscl_111" , "div_aclk_gscl_111" ,"aclk_gscl_333" , "div_aclk_gscl_333" ,"aclk_cam1_333" , "div_aclk_cam1_333" ,"aclk_cam1_400" , "div_aclk_cam1_400" ,"aclk_cam1_552" , "div_aclk_cam1_552" ,"aclk_cam0_333" , "div_aclk_cam0_333" ,"aclk_cam0_400" , "div_aclk_cam0_400" ,"aclk_cam0_552" , "div_aclk_cam0_552" ,"aclk_isp_dis_400" , "div_aclk_isp_dis_400" ,"aclk_isp_400" , "div_aclk_isp_400" ,"aclk_hevc_400" , "div_aclk_hevc_400" ,"aclk_mfc_400" , "div_aclk_mfc_400" ,"aclk_g2d_266" , "div_aclk_g2d_266" ,"aclk_g2d_400" , "div_aclk_g2d_400" ,/* ENABLE_SCLK_TOP_MSCL */ "sclk_jpeg_mscl" , "div_sclk_jpeg" ,/* ENABLE_SCLK_TOP_CAM1 */ "sclk_isp_sensor2" , "div_sclk_isp_sensor2_b" ,"sclk_isp_sensor1" , "div_sclk_isp_sensor1_b" ,"sclk_isp_sensor0" , "div_sclk_isp_sensor0_b" ,"sclk_isp_mctadc_cam1" , "oscclk" ,"sclk_isp_uart_cam1" , "div_sclk_isp_uart" ,"sclk_isp_spi1_cam1" , "div_sclk_isp_spi1_b" ,"sclk_isp_spi0_cam1" , "div_sclk_isp_spi0_b" ,/* ENABLE_SCLK_TOP_DISP */ "sclk_hdmi_spdif_disp" ,"mout_sclk_hdmi_spdif" , ENABLE_SCLK_TOP_DISP, 0,/* ENABLE_SCLK_TOP_FSYS */ "sclk_pcie_100_fsys" , "div_sclk_pcie_100" ,"sclk_mmc2_fsys" , "div_sclk_mmc2_b" ,"sclk_mmc1_fsys" , "div_sclk_mmc1_b" ,"sclk_mmc0_fsys" , "div_sclk_mmc0_b" ,"sclk_ufsunipro_fsys" ,"div_sclk_ufsunipro" , ENABLE_SCLK_TOP_FSYS,"sclk_usbhost30_fsys" ,"div_sclk_usbhost30" , ENABLE_SCLK_TOP_FSYS,"sclk_usbdrd30_fsys" ,"div_sclk_usbdrd30" , ENABLE_SCLK_TOP_FSYS,/* ENABLE_SCLK_TOP_PERIC */ "sclk_spi4_peric" , "div_sclk_spi4_b" ,"sclk_spi3_peric" , "div_sclk_spi3_b" ,"sclk_spdif_peric" , "mout_sclk_spdif" ,"sclk_i2s1_peric" , "div_sclk_i2s1" ,"sclk_pcm1_peric" , "div_sclk_pcm1" ,"sclk_uart2_peric" , "div_sclk_uart2" ,"sclk_uart1_peric" , "div_sclk_uart1" ,"sclk_uart0_peric" , "div_sclk_uart0" ,"sclk_spi2_peric" , "div_sclk_spi2_b" ,"sclk_spi1_peric" , "div_sclk_spi1_b" ,"sclk_spi0_peric" , "div_sclk_spi0_b" ,/* MUX_ENABLE_TOP_PERIC1 */ "sclk_slimbus" , "mout_sclk_slimbus" ,"sclk_audio1" , "div_sclk_audio1" ,"sclk_audio0" , "div_sclk_audio0" ,/* * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {/* sentinel */ } /* AUD_PLL */ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {/* sentinel */ } static const struct samsung_pll_clock top_pll_clks[] __initconst = {"fout_isp_pll" , "oscclk" ,"fout_aud_pll" , "oscclk" ,static const struct samsung_cmu_info top_cmu_info __initconst = {static void __init exynos5433_cmu_top_init(struct device_node *np)"samsung,exynos5433-cmu-top" ,/* * Register offset definitions for CMU_CPIF #define MPHY_PLL_LOCK 0x0000#define MPHY_PLL_CON0 0x0100#define MPHY_PLL_CON1 0x0104#define MPHY_PLL_FREQ_DET 0x010c#define MUX_SEL_CPIF0 0x0200#define DIV_CPIF 0x0600#define ENABLE_SCLK_CPIF 0x0a00static const unsigned long cpif_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {/* force all sclk clocks enabled */ /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ /* list of all parent clock list */ "oscclk" , "fout_mphy_pll" , };static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {"fout_mphy_pll" , "oscclk" ,static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {/* MUX_SEL_CPIF0 */ "mout_mphy_pll" , mout_mphy_pll_p, MUX_SEL_CPIF0,static const struct samsung_div_clock cpif_div_clks[] __initconst = {/* DIV_CPIF */ "div_sclk_mphy" , "mout_mphy_pll" , DIV_CPIF,static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {/* ENABLE_SCLK_CPIF */ "sclk_mphy_pll" , "mout_mphy_pll" ,"sclk_ufs_mphy" , "div_sclk_mphy" ,static const struct samsung_cmu_info cpif_cmu_info __initconst = {static void __init exynos5433_cmu_cpif_init(struct device_node *np)"samsung,exynos5433-cmu-cpif" ,/* * Register offset definitions for CMU_MIF #define MEM0_PLL_LOCK 0x0000#define MEM1_PLL_LOCK 0x0004#define BUS_PLL_LOCK 0x0008#define MFC_PLL_LOCK 0x000c#define MEM0_PLL_CON0 0x0100#define MEM0_PLL_CON1 0x0104#define MEM0_PLL_FREQ_DET 0x010c#define MEM1_PLL_CON0 0x0110#define MEM1_PLL_CON1 0x0114#define MEM1_PLL_FREQ_DET 0x011c#define BUS_PLL_CON0 0x0120#define BUS_PLL_CON1 0x0124#define BUS_PLL_FREQ_DET 0x012c#define MFC_PLL_CON0 0x0130#define MFC_PLL_CON1 0x0134#define MFC_PLL_FREQ_DET 0x013c#define MUX_SEL_MIF0 0x0200#define MUX_SEL_MIF1 0x0204#define MUX_SEL_MIF2 0x0208#define MUX_SEL_MIF3 0x020c#define MUX_SEL_MIF4 0x0210#define MUX_SEL_MIF5 0x0214#define MUX_SEL_MIF6 0x0218#define MUX_SEL_MIF7 0x021c#define MUX_ENABLE_MIF0 0x0300#define MUX_ENABLE_MIF1 0x0304#define MUX_ENABLE_MIF2 0x0308#define MUX_ENABLE_MIF3 0x030c#define MUX_ENABLE_MIF4 0x0310#define MUX_ENABLE_MIF5 0x0314#define MUX_ENABLE_MIF6 0x0318#define MUX_ENABLE_MIF7 0x031c#define MUX_STAT_MIF0 0x0400#define MUX_STAT_MIF1 0x0404#define MUX_STAT_MIF2 0x0408#define MUX_STAT_MIF3 0x040c#define MUX_STAT_MIF4 0x0410#define MUX_STAT_MIF5 0x0414#define MUX_STAT_MIF6 0x0418#define MUX_STAT_MIF7 0x041c#define DIV_MIF1 0x0604#define DIV_MIF2 0x0608#define DIV_MIF3 0x060c#define DIV_MIF4 0x0610#define DIV_MIF5 0x0614#define DIV_MIF_PLL_FREQ_DET 0x0618#define DIV_STAT_MIF1 0x0704#define DIV_STAT_MIF2 0x0708#define DIV_STAT_MIF3 0x070c#define DIV_STAT_MIF4 0x0710#define DIV_STAT_MIF5 0x0714#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718#define ENABLE_ACLK_MIF0 0x0800#define ENABLE_ACLK_MIF1 0x0804#define ENABLE_ACLK_MIF2 0x0808#define ENABLE_ACLK_MIF3 0x080c#define ENABLE_PCLK_MIF 0x0900#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910#define ENABLE_SCLK_MIF 0x0a00#define ENABLE_IP_MIF0 0x0b00#define ENABLE_IP_MIF1 0x0b04#define ENABLE_IP_MIF2 0x0b08#define ENABLE_IP_MIF3 0x0b0c#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c#define CLKOUT_CMU_MIF 0x0c00#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04#define DREX_FREQ_CTRL0 0x1000#define DREX_FREQ_CTRL1 0x1004#define PAUSE 0x1008#define DDRPHY_LOCK_CTRL 0x100cstatic const unsigned long mif_clk_regs[] __initconst = {static const struct samsung_pll_clock mif_pll_clks[] __initconst = {"fout_mem0_pll" , "oscclk" ,"fout_mem1_pll" , "oscclk" ,"fout_bus_pll" , "oscclk" ,"fout_mfc_pll" , "oscclk" ,/* list of all parent clock list */ "mout_mfc_pll" , "dout_mfc_pll" , };"mout_bus_pll" , "dout_bus_pll" , };"mout_mem1_pll" , "dout_mem1_pll" , };"mout_mem0_pll" , "dout_mem0_pll" , };"oscclk" , "fout_mfc_pll" , };"oscclk" , "fout_bus_pll" , };"oscclk" , "fout_mem1_pll" , };"oscclk" , "fout_mem0_pll" , };"mout_mem0_pll_div2" , "mout_clkm_phy_b" , };"mout_bus_pll_div2" , "mout_clkm_phy_a" , };"mout_bus_pll_div2" , "mout_mfc_pll_div2" , };"mout_mem1_pll_div2" , "mout_clkm_phy_a" , };"mout_mem0_pll_div2" , "div_mif_pre" , };"mout_mem1_pll_div2" , "mout_bus_pll_div2" ,};"mout_aclk_disp_333_a" ,"mout_bus_pll_div2" , };"mout_mfc_pll_div2" , "sclk_mphy_pll" , };"mout_sclk_decon_vclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_vclk_a" ,"mout_mfc_pll_div2" , };"oscclk" , "mout_bus_pll_div2" , };"mout_sclk_decon_eclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_eclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_decon_tv_eclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_tv_eclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_dsd_b" , "mout_bus_pll_div2" , };"mout_sclk_dsd_a" , "sclk_mphy_pll" , };"oscclk" , "mout_mfc_pll_div2" , };"mout_sclk_dsim0_b" , "sclk_mphy_pll" , };"mout_sclk_dsim0_a" , "mout_mfc_pll_div2" };"mout_sclk_decon_tv_vclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_tv_vclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_dsim1_b" , "sclk_mphy_pll" , };"mout_sclk_dsim1_a" , "mout_mfc_pll_div2" ,};static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ "dout_mfc_pll" , "mout_mfc_pll" , 1, 1, 0),"dout_bus_pll" , "mout_bus_pll" , 1, 1, 0),"dout_mem1_pll" , "mout_mem1_pll" , 1, 1, 0),"dout_mem0_pll" , "mout_mem0_pll" , 1, 1, 0),static const struct samsung_mux_clock mif_mux_clks[] __initconst = {/* MUX_SEL_MIF0 */ "mout_mfc_pll_div2" , mout_mfc_pll_div2_p,"mout_bus_pll_div2" , mout_bus_pll_div2_p,"mout_mem1_pll_div2" , mout_mem1_pll_div2_p,"mout_mem0_pll_div2" , mout_mem0_pll_div2_p,"mout_mfc_pll" , mout_mfc_pll_p, MUX_SEL_MIF0,"mout_bus_pll" , mout_bus_pll_p, MUX_SEL_MIF0,"mout_mem1_pll" , mout_mem1_pll_p, MUX_SEL_MIF0,"mout_mem0_pll" , mout_mem0_pll_p, MUX_SEL_MIF0,/* MUX_SEL_MIF1 */ "mout_clk2x_phy_c" , mout_clk2x_phy_c_p,"mout_clk2x_phy_b" , mout_clk2x_phy_b_p,"mout_clk2x_phy_a" , mout_clk2x_phy_a_p,"mout_clkm_phy_c" , mout_clk2x_phy_c_p,"mout_clkm_phy_b" , mout_clkm_phy_b_p,"mout_clkm_phy_a" , mout_clk2x_phy_a_p,/* MUX_SEL_MIF2 */ "mout_aclk_mifnm_200" ,"mout_aclk_mifnm_400" ,/* MUX_SEL_MIF3 */ "mout_aclk_disp_333_b" ,"mout_aclk_disp_333_a" ,/* MUX_SEL_MIF4 */ "mout_sclk_decon_vclk_c" ,"mout_sclk_decon_vclk_b" ,"mout_sclk_decon_vclk_a" ,"mout_sclk_decon_eclk_c" ,"mout_sclk_decon_eclk_b" ,"mout_sclk_decon_eclk_a" ,/* MUX_SEL_MIF5 */ "mout_sclk_decon_tv_eclk_c" ,"mout_sclk_decon_tv_eclk_b" ,"mout_sclk_decon_tv_eclk_a" ,"mout_sclk_dsd_c" , mout_sclk_dsd_c_p,"mout_sclk_dsd_b" , mout_sclk_dsd_b_p,"mout_sclk_dsd_a" , mout_sclk_dsd_a_p,/* MUX_SEL_MIF6 */ "mout_sclk_dsim0_c" , mout_sclk_dsim0_c_p,"mout_sclk_dsim0_b" , mout_sclk_dsim0_b_p,"mout_sclk_dsim0_a" , mout_sclk_decon_p,/* MUX_SEL_MIF7 */ "mout_sclk_decon_tv_vclk_c" ,"mout_sclk_decon_tv_vclk_b" ,"mout_sclk_decon_tv_vclk_a" ,"mout_sclk_dsim1_c" , mout_sclk_dsim1_c_p,"mout_sclk_dsim1_b" , mout_sclk_dsim1_b_p,"mout_sclk_dsim1_a" , mout_sclk_decon_p,static const struct samsung_div_clock mif_div_clks[] __initconst = {/* DIV_MIF1 */ "div_sclk_hpm_mif" , "div_clk2x_phy" ,"div_aclk_drex1" , "div_clk2x_phy" , DIV_MIF1,"div_aclk_drex0" , "div_clk2x_phy" , DIV_MIF1,"div_clk2x_phy" , "mout_clk2x_phy_c" , DIV_MIF1,/* DIV_MIF2 */ "div_aclk_mif_266" , "mout_bus_pll_div2" ,"div_aclk_mifnd_133" , "div_mif_pre" ,"div_aclk_mif_133" , "div_mif_pre" ,"div_aclk_mifnm_200" ,"mout_aclk_mifnm_200" , DIV_MIF2, 8, 3),"div_aclk_mif_200" , "div_aclk_mif_400" ,"div_aclk_mif_400" , "mout_aclk_mifnm_400" ,/* DIV_MIF3 */ "div_aclk_bus2_400" , "div_mif_pre" ,"div_aclk_disp_333" , "mout_aclk_disp_333_b" ,"div_aclk_cpif_200" , "mout_aclk_mifnm_200" ,/* DIV_MIF4 */ "div_sclk_dsim1" , "mout_sclk_dsim1_c" ,"div_sclk_decon_tv_vclk" ,"mout_sclk_decon_tv_vclk_c" , DIV_MIF4, 20, 4),"div_sclk_dsim0" , "mout_sclk_dsim0_c" ,"div_sclk_dsd" , "mout_sclk_dsd_c" ,"div_sclk_decon_tv_eclk" ,"mout_sclk_decon_tv_eclk_c" , DIV_MIF4, 8, 4),"div_sclk_decon_vclk" ,"mout_sclk_decon_vclk_c" , DIV_MIF4, 4, 4),"div_sclk_decon_eclk" ,"mout_sclk_decon_eclk_c" , DIV_MIF4, 0, 4),/* DIV_MIF5 */ "div_mif_pre" , "mout_bus_pll_div2" , DIV_MIF5,static const struct samsung_gate_clock mif_gate_clks[] __initconst = {/* ENABLE_ACLK_MIF0 */ "clk2k_phy1" , "div_clk2x_phy" , ENABLE_ACLK_MIF0,"clk2x_phy0" , "div_clk2x_phy" , ENABLE_ACLK_MIF0,"clkm_phy1" , "mout_clkm_phy_c" , ENABLE_ACLK_MIF0,"clkm_phy0" , "mout_clkm_phy_c" , ENABLE_ACLK_MIF0,"rclk_drex1" , "oscclk" , ENABLE_ACLK_MIF0,"rclk_drex0" , "oscclk" , ENABLE_ACLK_MIF0,"aclk_drex1_tz" , "div_aclk_drex1" ,"aclk_drex0_tz" , "div_aclk_drex0" ,"aclk_drex1_perev" , "div_aclk_drex1" ,"aclk_drex0_perev" , "div_aclk_drex0" ,"aclk_drex1_memif" , "div_aclk_drex1" ,"aclk_drex0_memif" , "div_aclk_drex0" ,"aclk_drex1_sch" , "div_aclk_drex1" ,"aclk_drex0_sch" , "div_aclk_drex0" ,"aclk_drex1_busif" , "div_aclk_drex1" ,"aclk_drex0_busif" , "div_aclk_drex0" ,"aclk_drex1_busif_rd" , "div_aclk_drex1" ,"aclk_drex0_busif_rd" , "div_aclk_drex0" ,"aclk_drex1" , "div_aclk_drex1" ,"aclk_drex0" , "div_aclk_drex0" ,/* ENABLE_ACLK_MIF1 */ "aclk_asyncaxis_mif_imem" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF1, 28,"aclk_asyncaxis_noc_p_cci" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_noc_p_cci" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_cp1" ,"div_aclk_mifnm_200" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_cp1" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_cp0" ,"div_aclk_mifnm_200" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_cp0" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex1_3" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex1_3" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex1_1" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex1_1" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex1_0" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex1_0" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex0_3" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex0_3" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex0_1" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex0_1" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex0_0" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex0_0" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_ahb2apb_mif2p" , "div_aclk_mif_133" ,"aclk_ahb2apb_mif1p" , "div_aclk_mif_133" ,"aclk_ahb2apb_mif0p" , "div_aclk_mif_133" ,"aclk_ixiu_cci" , "div_aclk_mif_400" ,"aclk_xiu_mifsfrx" , "div_aclk_mif_200" ,"aclk_mifnp_133" , "div_aclk_mif_133" ,"aclk_mifnm_200" , "div_aclk_mifnm_200" ,"aclk_mifnd_133" , "div_aclk_mifnd_133" ,"aclk_mifnd_400" , "div_aclk_mif_400" ,"aclk_cci" , "div_aclk_mif_400" , ENABLE_ACLK_MIF1,/* ENABLE_ACLK_MIF2 */ "aclk_mifnd_266" , "div_aclk_mif_266" ,"aclk_ppmu_drex1s3" , "div_aclk_drex1" ,"aclk_ppmu_drex1s1" , "div_aclk_drex1" ,"aclk_ppmu_drex1s0" , "div_aclk_drex1" ,"aclk_ppmu_drex0s3" , "div_aclk_drex0" ,"aclk_ppmu_drex0s1" , "div_aclk_drex0" ,"aclk_ppmu_drex0s0" , "div_aclk_drex0" ,"aclk_axids_cci_mifsfrx" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF2, 7,"aclk_axisyncdns_cci" ,"div_aclk_mif_400" , ENABLE_ACLK_MIF2,"aclk_axisyncdn_cci" , "div_aclk_mif_400" ,"aclk_axisyncdn_noc_d" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF2,"aclk_asyncapbs_mif_cssys" ,"div_aclk_mifnd_133" , ENABLE_ACLK_MIF2, 0, 0, 0),/* ENABLE_ACLK_MIF3 */ "aclk_bus2_400" , "div_aclk_bus2_400" ,"aclk_disp_333" , "div_aclk_disp_333" ,"aclk_cpif_200" , "div_aclk_cpif_200" ,/* ENABLE_PCLK_MIF */ "pclk_ppmu_drex1s3" , "div_aclk_drex1" ,"pclk_ppmu_drex1s1" , "div_aclk_drex1" ,"pclk_ppmu_drex1s0" , "div_aclk_drex1" ,"pclk_ppmu_drex0s3" , "div_aclk_drex0" ,"pclk_ppmu_drex0s1" , "div_aclk_drex0" ,"pclk_ppmu_drex0s0" , "div_aclk_drex0" ,"pclk_asyncaxi_noc_p_cci" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 21,"pclk_asyncaxi_cp1" , "div_aclk_mif_133" ,"pclk_asyncaxi_cp0" , "div_aclk_mif_133" ,"pclk_asyncaxi_drex1_3" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 17, 0, 0),"pclk_asyncaxi_drex1_1" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 16, 0, 0),"pclk_asyncaxi_drex1_0" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 15, 0, 0),"pclk_asyncaxi_drex0_3" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 14, 0, 0),"pclk_asyncaxi_drex0_1" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 13, 0, 0),"pclk_asyncaxi_drex0_0" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 12, 0, 0),"pclk_mifsrvnd_133" , "div_aclk_mif_133" ,"pclk_pmu_mif" , "div_aclk_mif_133" ,"pclk_sysreg_mif" , "div_aclk_mif_133" ,"pclk_gpio_alive" , "div_aclk_mif_133" ,"pclk_abb" , "div_aclk_mif_133" ,"pclk_pmu_apbif" , "div_aclk_mif_133" ,"pclk_ddr_phy1" , "div_aclk_mif_133" ,"pclk_drex1" , "div_aclk_mif_133" ,"pclk_ddr_phy0" , "div_aclk_mif_133" ,"pclk_drex0" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ "pclk_drex0_tz" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ "pclk_drex1_tz" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ "pclk_monotonic_cnt" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_RTC */ "pclk_rtc" , "div_aclk_mif_133" ,/* ENABLE_SCLK_MIF */ "sclk_dsim1_disp" , "div_sclk_dsim1" ,"sclk_decon_tv_vclk_disp" ,"div_sclk_decon_tv_vclk" , ENABLE_SCLK_MIF,"sclk_dsim0_disp" , "div_sclk_dsim0" ,"sclk_dsd_disp" , "div_sclk_dsd" ,"sclk_decon_tv_eclk_disp" ,"div_sclk_decon_tv_eclk" , ENABLE_SCLK_MIF,"sclk_decon_vclk_disp" ,"div_sclk_decon_vclk" , ENABLE_SCLK_MIF,"sclk_decon_eclk_disp" ,"div_sclk_decon_eclk" , ENABLE_SCLK_MIF,"sclk_hpm_mif" , "div_sclk_hpm_mif" ,"sclk_mfc_pll" , "mout_mfc_pll_div2" ,"sclk_bus_pll" , "mout_bus_pll_div2" ,"sclk_bus_pll_apollo" , "sclk_bus_pll" ,"sclk_bus_pll_atlas" , "sclk_bus_pll" ,static const struct samsung_cmu_info mif_cmu_info __initconst = {static void __init exynos5433_cmu_mif_init(struct device_node *np)"samsung,exynos5433-cmu-mif" ,/* * Register offset definitions for CMU_PERIC #define DIV_PERIC 0x0600#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904#define ENABLE_SCLK_PERIC 0x0A00#define ENABLE_IP_PERIC0 0x0B00#define ENABLE_IP_PERIC1 0x0B04#define ENABLE_IP_PERIC2 0x0B08static const unsigned long peric_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump peric_suspend_regs[] = {/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ /* sclk: uart2-0 */ static const struct samsung_div_clock peric_div_clks[] __initconst = {/* DIV_PERIC */ "div_sclk_sci" , "oscclk" , DIV_PERIC, 4, 4),"div_sclk_sc_in" , "oscclk" , DIV_PERIC, 0, 4),static const struct samsung_gate_clock peric_gate_clks[] __initconst = {/* ENABLE_ACLK_PERIC */ "aclk_ahb2apb_peric2p" , "aclk_peric_66" ,"aclk_ahb2apb_peric1p" , "aclk_peric_66" ,"aclk_ahb2apb_peric0p" , "aclk_peric_66" ,"aclk_pericnp_66" , "aclk_peric_66" ,/* ENABLE_PCLK_PERIC0 */ "pclk_sci" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_gpio_finger" , "aclk_peric_66" ,"pclk_gpio_ese" , "aclk_peric_66" ,"pclk_pwm" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spdif" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_pcm1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2s" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spi2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spi1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spi0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_adcif" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_gpio_touch" , "aclk_peric_66" ,"pclk_gpio_nfc" , "aclk_peric_66" ,"pclk_gpio_peric" , "aclk_peric_66" ,"pclk_pmu_peric" , "aclk_peric_66" ,"pclk_sysreg_peric" , "aclk_peric_66" ,"pclk_uart2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,
Messung V0.5 C=96 H=99 G=97
¤ Dauer der Verarbeitung: 0.16 Sekunden
¤ *© Formatika GbR, Deutschland
