// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Samsung Electronics Co., Ltd. * Author: Kaustabh Chakraborty <kauschluss@disroot.org> * * Common Clock Framework support for Exynos7870. #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/of.h>#include <linux/platform_device.h>#include <dt-bindings/clock/samsung,exynos7870-cmu.h>#include "clk.h" #include "clk-exynos-arm64.h" /* * Register offsets for CMU_MIF (0x10460000) #define PLL_LOCKTIME_MIF_MEM_PLL 0x0000#define PLL_LOCKTIME_MIF_MEDIA_PLL 0x0020#define PLL_LOCKTIME_MIF_BUS_PLL 0x0040#define PLL_CON0_MIF_MEM_PLL 0x0100#define PLL_CON0_MIF_MEDIA_PLL 0x0120#define PLL_CON0_MIF_BUS_PLL 0x0140#define CLK_CON_GAT_MIF_MUX_MEM_PLL 0x0200#define CLK_CON_GAT_MIF_MUX_MEM_PLL_CON 0x0200#define CLK_CON_GAT_MIF_MUX_MEDIA_PLL 0x0204#define CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON 0x0204#define CLK_CON_GAT_MIF_MUX_BUS_PLL 0x0208#define CLK_CON_GAT_MIF_MUX_BUS_PLL_CON 0x0208#define CLK_CON_GAT_MIF_MUX_BUSD 0x0220#define CLK_CON_MUX_MIF_BUSD 0x0220#define CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA 0x0264#define CLK_CON_MUX_MIF_CMU_ISP_VRA 0x0264#define CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM 0x0268#define CLK_CON_MUX_MIF_CMU_ISP_CAM 0x0268#define CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP 0x026c#define CLK_CON_MUX_MIF_CMU_ISP_ISP 0x026c#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS 0x0270#define CLK_CON_MUX_MIF_CMU_DISPAUD_BUS 0x0270#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 0x0274#define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK 0x0274#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 0x0278#define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK 0x0278#define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL 0x027c#define CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL 0x027c#define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC 0x0280#define CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC 0x0280#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS 0x0284#define CLK_CON_MUX_MIF_CMU_FSYS_BUS 0x0284#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0 0x0288#define CLK_CON_MUX_MIF_CMU_FSYS_MMC0 0x0288#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1 0x028c#define CLK_CON_MUX_MIF_CMU_FSYS_MMC1 0x028c#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2 0x0290#define CLK_CON_MUX_MIF_CMU_FSYS_MMC2 0x0290#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 0x029c#define CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK 0x029c#define CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS 0x02a0#define CLK_CON_MUX_MIF_CMU_PERI_BUS 0x02a0#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1 0x02a4#define CLK_CON_MUX_MIF_CMU_PERI_UART1 0x02a4#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2 0x02a8#define CLK_CON_MUX_MIF_CMU_PERI_UART2 0x02a8#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0 0x02ac#define CLK_CON_MUX_MIF_CMU_PERI_UART0 0x02ac#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2 0x02b0#define CLK_CON_MUX_MIF_CMU_PERI_SPI2 0x02b0#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1 0x02b4#define CLK_CON_MUX_MIF_CMU_PERI_SPI1 0x02b4#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0 0x02b8#define CLK_CON_MUX_MIF_CMU_PERI_SPI0 0x02b8#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3 0x02bc#define CLK_CON_MUX_MIF_CMU_PERI_SPI3 0x02bc#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4 0x02c0#define CLK_CON_MUX_MIF_CMU_PERI_SPI4 0x02c0#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0 0x02c4#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR0 0x02c4#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1 0x02c8#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR1 0x02c8#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2 0x02cc#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR2 0x02cc#define CLK_CON_DIV_MIF_BUSD 0x0420#define CLK_CON_DIV_MIF_APB 0x0424#define CLK_CON_DIV_MIF_HSI2C 0x0430#define CLK_CON_DIV_MIF_CMU_G3D_SWITCH 0x0460#define CLK_CON_DIV_MIF_CMU_ISP_VRA 0x0464#define CLK_CON_DIV_MIF_CMU_ISP_CAM 0x0468#define CLK_CON_DIV_MIF_CMU_ISP_ISP 0x046c#define CLK_CON_DIV_MIF_CMU_DISPAUD_BUS 0x0470#define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK 0x0474#define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK 0x0478#define CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL 0x047c#define CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC 0x0480#define CLK_CON_DIV_MIF_CMU_FSYS_BUS 0x0484#define CLK_CON_DIV_MIF_CMU_FSYS_MMC0 0x0488#define CLK_CON_DIV_MIF_CMU_FSYS_MMC1 0x048c#define CLK_CON_DIV_MIF_CMU_FSYS_MMC2 0x0490#define CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK 0x049c#define CLK_CON_DIV_MIF_CMU_PERI_BUS 0x04a0#define CLK_CON_DIV_MIF_CMU_PERI_UART1 0x04a4#define CLK_CON_DIV_MIF_CMU_PERI_UART2 0x04a8#define CLK_CON_DIV_MIF_CMU_PERI_UART0 0x04ac#define CLK_CON_DIV_MIF_CMU_PERI_SPI2 0x04b0#define CLK_CON_DIV_MIF_CMU_PERI_SPI1 0x04b4#define CLK_CON_DIV_MIF_CMU_PERI_SPI0 0x04b8#define CLK_CON_DIV_MIF_CMU_PERI_SPI3 0x04bc#define CLK_CON_DIV_MIF_CMU_PERI_SPI4 0x04c0#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR0 0x04c4#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR1 0x04c8#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR2 0x04cc#define CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS 0x080c#define CLK_CON_GAT_MIF_HSI2C_AP_PCLKS 0x0828#define CLK_CON_GAT_MIF_HSI2C_CP_PCLKS 0x0828#define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0 0x0828#define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1 0x0828#define CLK_CON_GAT_MIF_HSI2C_AP_PCLKM 0x0840#define CLK_CON_GAT_MIF_HSI2C_CP_PCLKM 0x0840#define CLK_CON_GAT_MIF_HSI2C_IPCLK 0x0840#define CLK_CON_GAT_MIF_HSI2C_ITCLK 0x0840#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C 0x0840#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0 0x0840#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1 0x0840#define CLK_CON_GAT_MIF_CMU_G3D_SWITCH 0x0860#define CLK_CON_GAT_MIF_CMU_ISP_VRA 0x0864#define CLK_CON_GAT_MIF_CMU_ISP_CAM 0x0868#define CLK_CON_GAT_MIF_CMU_ISP_ISP 0x086c#define CLK_CON_GAT_MIF_CMU_DISPAUD_BUS 0x0870#define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK 0x0874#define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK 0x0878#define CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL 0x087c#define CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC 0x0880#define CLK_CON_GAT_MIF_CMU_FSYS_BUS 0x0884#define CLK_CON_GAT_MIF_CMU_FSYS_MMC0 0x0888#define CLK_CON_GAT_MIF_CMU_FSYS_MMC1 0x088c#define CLK_CON_GAT_MIF_CMU_FSYS_MMC2 0x0890#define CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK 0x089c#define CLK_CON_GAT_MIF_CMU_PERI_BUS 0x08a0#define CLK_CON_GAT_MIF_CMU_PERI_UART1 0x08a4#define CLK_CON_GAT_MIF_CMU_PERI_UART2 0x08a8#define CLK_CON_GAT_MIF_CMU_PERI_UART0 0x08ac#define CLK_CON_GAT_MIF_CMU_PERI_SPI2 0x08b0#define CLK_CON_GAT_MIF_CMU_PERI_SPI1 0x08b4#define CLK_CON_GAT_MIF_CMU_PERI_SPI0 0x08b8#define CLK_CON_GAT_MIF_CMU_PERI_SPI3 0x08bc#define CLK_CON_GAT_MIF_CMU_PERI_SPI4 0x08c0#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR0 0x08c4#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR1 0x08c8#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR2 0x08ccstatic const unsigned long mif_clk_regs[] __initconst = {static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {"ffac_mif_mux_bus_pll_div2" , "gout_mif_mux_bus_pll_con" , 1, 2,"ffac_mif_mux_media_pll_div2" , "gout_mif_mux_media_pll_con" ,"ffac_mif_mux_mem_pll_div2" , "gout_mif_mux_mem_pll_con" , 1, 2,static const struct samsung_pll_clock mif_pll_clks[] __initconst = {"fout_mif_bus_pll" , "oscclk" ,"fout_mif_media_pll" , "oscclk" ,"fout_mif_mem_pll" , "oscclk" ,/* List of parent clocks for muxes in CMU_MIF */ "ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" ,"gout_mif_mux_bus_pll_con" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" ,"gout_mif_mux_bus_pll_con" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" ,"gout_mif_mux_bus_pll_con" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"oscclk" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" };"ffac_mif_mux_bus_pll_div2" ,"ffac_mif_mux_media_pll_div2" ,"ffac_mif_mux_mem_pll_div2" };static const struct samsung_mux_clock mif_mux_clks[] __initconst = {"mout_mif_cmu_dispaud_bus" ,"mout_mif_cmu_dispaud_decon_eclk" ,"mout_mif_cmu_dispaud_decon_vclk" ,"mout_mif_cmu_fsys_bus" ,"mout_mif_cmu_fsys_mmc0" ,"mout_mif_cmu_fsys_mmc1" ,"mout_mif_cmu_fsys_mmc2" ,"mout_mif_cmu_fsys_usb20drd_refclk" ,"mout_mif_cmu_isp_cam" ,"mout_mif_cmu_isp_isp" ,"mout_mif_cmu_isp_sensor0" ,"mout_mif_cmu_isp_sensor1" ,"mout_mif_cmu_isp_sensor2" ,"mout_mif_cmu_isp_vra" ,"mout_mif_cmu_mfcmscl_mfc" ,"mout_mif_cmu_mfcmscl_mscl" ,"mout_mif_cmu_peri_bus" ,"mout_mif_cmu_peri_spi0" ,"mout_mif_cmu_peri_spi2" ,"mout_mif_cmu_peri_spi1" ,"mout_mif_cmu_peri_spi4" ,"mout_mif_cmu_peri_spi3" ,"mout_mif_cmu_peri_uart1" ,"mout_mif_cmu_peri_uart2" ,"mout_mif_cmu_peri_uart0" ,"mout_mif_busd" , mout_mif_busd_p,static const struct samsung_div_clock mif_div_clks[] __initconst = {"dout_mif_cmu_dispaud_bus" ,"gout_mif_mux_cmu_dispaud_bus" , CLK_CON_DIV_MIF_CMU_DISPAUD_BUS, 0,"dout_mif_cmu_dispaud_decon_eclk" ,"gout_mif_mux_cmu_dispaud_decon_eclk" ,"dout_mif_cmu_dispaud_decon_vclk" ,"gout_mif_mux_cmu_dispaud_decon_vclk" ,"dout_mif_cmu_fsys_bus" ,"gout_mif_mux_cmu_fsys_bus" , CLK_CON_DIV_MIF_CMU_FSYS_BUS, 0, 4),"dout_mif_cmu_fsys_mmc0" ,"gout_mif_mux_cmu_fsys_mmc0" , CLK_CON_DIV_MIF_CMU_FSYS_MMC0, 0, 10),"dout_mif_cmu_fsys_mmc1" ,"gout_mif_mux_cmu_fsys_mmc1" , CLK_CON_DIV_MIF_CMU_FSYS_MMC1, 0, 10),"dout_mif_cmu_fsys_mmc2" ,"gout_mif_mux_cmu_fsys_mmc2" , CLK_CON_DIV_MIF_CMU_FSYS_MMC2, 0, 10),"dout_mif_cmu_fsys_usb20drd_refclk" ,"gout_mif_mux_cmu_fsys_usb20drd_refclk" ,"dout_mif_cmu_g3d_switch" ,"ffac_mif_mux_bus_pll_div2" , CLK_CON_DIV_MIF_CMU_G3D_SWITCH, 0, 2),"dout_mif_cmu_isp_cam" ,"gout_mif_mux_cmu_isp_cam" , CLK_CON_DIV_MIF_CMU_ISP_CAM, 0, 4),"dout_mif_cmu_isp_isp" ,"gout_mif_mux_cmu_isp_isp" , CLK_CON_DIV_MIF_CMU_ISP_ISP, 0, 4),"dout_mif_cmu_isp_sensor0" ,"gout_mif_mux_cmu_isp_sensor0" , CLK_CON_DIV_MIF_CMU_ISP_SENSOR0, 0,"dout_mif_cmu_isp_sensor1" ,"gout_mif_mux_cmu_isp_sensor1" , CLK_CON_DIV_MIF_CMU_ISP_SENSOR1, 0,"dout_mif_cmu_isp_sensor2" ,"gout_mif_mux_cmu_isp_sensor2" , CLK_CON_DIV_MIF_CMU_ISP_SENSOR2, 0,"dout_mif_cmu_isp_vra" ,"gout_mif_mux_cmu_isp_vra" , CLK_CON_DIV_MIF_CMU_ISP_VRA, 0, 4),"dout_mif_cmu_mfcmscl_mfc" ,"gout_mif_mux_cmu_mfcmscl_mfc" , CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC, 0,"dout_mif_cmu_mfcmscl_mscl" ,"gout_mif_mux_cmu_mfcmscl_mscl" , CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL,"dout_mif_cmu_peri_bus" ,"gout_mif_mux_cmu_peri_bus" , CLK_CON_DIV_MIF_CMU_PERI_BUS, 0, 4),"dout_mif_cmu_peri_spi0" ,"gout_mif_mux_cmu_peri_spi0" , CLK_CON_DIV_MIF_CMU_PERI_SPI0, 0, 6),"dout_mif_cmu_peri_spi2" ,"gout_mif_mux_cmu_peri_spi2" , CLK_CON_DIV_MIF_CMU_PERI_SPI2, 0, 6),"dout_mif_cmu_peri_spi1" ,"gout_mif_mux_cmu_peri_spi1" , CLK_CON_DIV_MIF_CMU_PERI_SPI1, 0, 6),"dout_mif_cmu_peri_spi4" ,"gout_mif_mux_cmu_peri_spi4" , CLK_CON_DIV_MIF_CMU_PERI_SPI4, 0, 6),"dout_mif_cmu_peri_spi3" ,"gout_mif_mux_cmu_peri_spi3" , CLK_CON_DIV_MIF_CMU_PERI_SPI3, 0, 6),"dout_mif_cmu_peri_uart1" ,"gout_mif_mux_cmu_peri_uart1" , CLK_CON_DIV_MIF_CMU_PERI_UART1, 0, 4),"dout_mif_cmu_peri_uart2" ,"gout_mif_mux_cmu_peri_uart2" , CLK_CON_DIV_MIF_CMU_PERI_UART2, 0, 4),"dout_mif_cmu_peri_uart0" ,"gout_mif_mux_cmu_peri_uart0" , CLK_CON_DIV_MIF_CMU_PERI_UART0, 0, 4),"dout_mif_apb" , "dout_mif_busd" ,"dout_mif_busd" , "gout_mif_mux_busd" ,"dout_mif_hsi2c" , "ffac_mif_mux_media_pll_div2" ,static const struct samsung_gate_clock mif_gate_clks[] __initconst = {"gout_mif_cmu_dispaud_bus" ,"dout_mif_cmu_dispaud_bus" , CLK_CON_GAT_MIF_CMU_DISPAUD_BUS, 0,"gout_mif_cmu_dispaud_decon_eclk" ,"dout_mif_cmu_dispaud_decon_eclk" ,"gout_mif_cmu_dispaud_decon_vclk" ,"dout_mif_cmu_dispaud_decon_vclk" ,"gout_mif_cmu_fsys_bus" ,"dout_mif_cmu_fsys_bus" , CLK_CON_GAT_MIF_CMU_FSYS_BUS, 0,"gout_mif_cmu_fsys_mmc0" ,"dout_mif_cmu_fsys_mmc0" , CLK_CON_GAT_MIF_CMU_FSYS_MMC0, 0,"gout_mif_cmu_fsys_mmc1" ,"dout_mif_cmu_fsys_mmc1" , CLK_CON_GAT_MIF_CMU_FSYS_MMC1, 0,"gout_mif_cmu_fsys_mmc2" ,"dout_mif_cmu_fsys_mmc2" , CLK_CON_GAT_MIF_CMU_FSYS_MMC2, 0,"gout_mif_cmu_fsys_usb20drd_refclk" ,"dout_mif_cmu_fsys_usb20drd_refclk" ,"gout_mif_cmu_g3d_switch" ,"dout_mif_cmu_g3d_switch" , CLK_CON_GAT_MIF_CMU_G3D_SWITCH, 0,"gout_mif_cmu_isp_cam" ,"dout_mif_cmu_isp_cam" , CLK_CON_GAT_MIF_CMU_ISP_CAM, 0,"gout_mif_cmu_isp_isp" ,"dout_mif_cmu_isp_isp" , CLK_CON_GAT_MIF_CMU_ISP_ISP, 0,"gout_mif_cmu_isp_sensor0" ,"dout_mif_cmu_isp_sensor0" , CLK_CON_GAT_MIF_CMU_ISP_SENSOR0, 0,"gout_mif_cmu_isp_sensor1" ,"dout_mif_cmu_isp_sensor1" , CLK_CON_GAT_MIF_CMU_ISP_SENSOR1, 0,"gout_mif_cmu_isp_sensor2" ,"dout_mif_cmu_isp_sensor2" , CLK_CON_GAT_MIF_CMU_ISP_SENSOR2, 0,"gout_mif_cmu_isp_vra" ,"dout_mif_cmu_isp_vra" , CLK_CON_GAT_MIF_CMU_ISP_VRA, 0,"gout_mif_cmu_mfcmscl_mfc" ,"dout_mif_cmu_mfcmscl_mfc" , CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC, 0,"gout_mif_cmu_mfcmscl_mscl" ,"dout_mif_cmu_mfcmscl_mscl" , CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL, 0,"gout_mif_cmu_peri_bus" ,"dout_mif_cmu_peri_bus" , CLK_CON_GAT_MIF_CMU_PERI_BUS, 0,"gout_mif_cmu_peri_spi0" ,"dout_mif_cmu_peri_spi0" , CLK_CON_GAT_MIF_CMU_PERI_SPI0, 0,"gout_mif_cmu_peri_spi2" ,"dout_mif_cmu_peri_spi2" , CLK_CON_GAT_MIF_CMU_PERI_SPI2, 0,"gout_mif_cmu_peri_spi1" ,"dout_mif_cmu_peri_spi1" , CLK_CON_GAT_MIF_CMU_PERI_SPI1, 0,"gout_mif_cmu_peri_spi4" ,"dout_mif_cmu_peri_spi4" , CLK_CON_GAT_MIF_CMU_PERI_SPI4, 0,"gout_mif_cmu_peri_spi3" ,"dout_mif_cmu_peri_spi3" , CLK_CON_GAT_MIF_CMU_PERI_SPI3, 0,"gout_mif_cmu_peri_uart1" ,"dout_mif_cmu_peri_uart1" , CLK_CON_GAT_MIF_CMU_PERI_UART1, 0,"gout_mif_cmu_peri_uart2" ,"dout_mif_cmu_peri_uart2" , CLK_CON_GAT_MIF_CMU_PERI_UART2, 0,"gout_mif_cmu_peri_uart0" ,"dout_mif_cmu_peri_uart0" , CLK_CON_GAT_MIF_CMU_PERI_UART0, 0,"gout_mif_hsi2c_ap_pclkm" ,"dout_mif_hsi2c" , CLK_CON_GAT_MIF_HSI2C_AP_PCLKM, 0,"gout_mif_hsi2c_ap_pclks" ,"dout_mif_apb" , CLK_CON_GAT_MIF_HSI2C_AP_PCLKS, 14, CLK_IS_CRITICAL"gout_mif_hsi2c_cp_pclkm" ,"dout_mif_hsi2c" , CLK_CON_GAT_MIF_HSI2C_CP_PCLKM, 1,"gout_mif_hsi2c_cp_pclks" ,"dout_mif_apb" , CLK_CON_GAT_MIF_HSI2C_CP_PCLKS, 15, CLK_IS_CRITICAL"gout_mif_hsi2c_ipclk" , "dout_mif_hsi2c" ,"gout_mif_hsi2c_itclk" , "dout_mif_hsi2c" ,"gout_mif_cp_pclk_hsi2c" ,"dout_mif_hsi2c" , CLK_CON_GAT_MIF_CP_PCLK_HSI2C, 6, CLK_IS_CRITICAL"gout_mif_cp_pclk_hsi2c_bat_0" ,"dout_mif_hsi2c" , CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0, 4,"gout_mif_cp_pclk_hsi2c_bat_1" ,"dout_mif_hsi2c" , CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1, 5,"gout_mif_wrap_adc_if_osc_sys" ,"oscclk" , CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS, 3,"gout_mif_wrap_adc_if_pclk_s0" ,"dout_mif_apb" , CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0, 20,"gout_mif_wrap_adc_if_pclk_s1" ,"dout_mif_apb" , CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1, 21,"gout_mif_mux_bus_pll" ,"gout_mif_mux_bus_pll_con" , CLK_CON_GAT_MIF_MUX_BUS_PLL, 21,"gout_mif_mux_bus_pll_con" ,"fout_mif_bus_pll" , CLK_CON_GAT_MIF_MUX_BUS_PLL_CON, 12,"gout_mif_mux_cmu_dispaud_bus" ,"mout_mif_cmu_dispaud_bus" , CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS,"gout_mif_mux_cmu_dispaud_decon_eclk" ,"mout_mif_cmu_dispaud_decon_eclk" ,"gout_mif_mux_cmu_dispaud_decon_vclk" ,"mout_mif_cmu_dispaud_decon_vclk" ,"gout_mif_mux_cmu_fsys_bus" ,"mout_mif_cmu_fsys_bus" , CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS, 21,"gout_mif_mux_cmu_fsys_mmc0" ,"mout_mif_cmu_fsys_mmc0" , CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0, 21,"gout_mif_mux_cmu_fsys_mmc1" ,"mout_mif_cmu_fsys_mmc1" , CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1, 21,"gout_mif_mux_cmu_fsys_mmc2" ,"mout_mif_cmu_fsys_mmc2" , CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2, 21,"gout_mif_mux_cmu_fsys_usb20drd_refclk" ,"mout_mif_cmu_fsys_usb20drd_refclk" ,"gout_mif_mux_cmu_isp_cam" ,"mout_mif_cmu_isp_cam" , CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM, 21,"gout_mif_mux_cmu_isp_isp" ,"mout_mif_cmu_isp_isp" , CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP, 21,"gout_mif_mux_cmu_isp_sensor0" ,"mout_mif_cmu_isp_sensor0" , CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0,"gout_mif_mux_cmu_isp_sensor1" ,"mout_mif_cmu_isp_sensor1" , CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1,"gout_mif_mux_cmu_isp_sensor2" ,"mout_mif_cmu_isp_sensor2" , CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2,"gout_mif_mux_cmu_isp_vra" ,"mout_mif_cmu_isp_vra" , CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA, 21,"gout_mif_mux_cmu_mfcmscl_mfc" ,"mout_mif_cmu_mfcmscl_mfc" , CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC,"gout_mif_mux_cmu_mfcmscl_mscl" ,"mout_mif_cmu_mfcmscl_mscl" , CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL,"gout_mif_mux_cmu_peri_bus" ,"mout_mif_cmu_peri_bus" , CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS, 21,"gout_mif_mux_cmu_peri_spi0" ,"mout_mif_cmu_peri_spi0" , CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0, 21,"gout_mif_mux_cmu_peri_spi2" ,"mout_mif_cmu_peri_spi2" , CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2, 21,"gout_mif_mux_cmu_peri_spi1" ,"mout_mif_cmu_peri_spi1" , CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1, 21,"gout_mif_mux_cmu_peri_spi4" ,"mout_mif_cmu_peri_spi4" , CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4, 21,"gout_mif_mux_cmu_peri_spi3" ,"mout_mif_cmu_peri_spi3" , CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3, 21,"gout_mif_mux_cmu_peri_uart1" ,"mout_mif_cmu_peri_uart1" , CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1, 21,"gout_mif_mux_cmu_peri_uart2" ,"mout_mif_cmu_peri_uart2" , CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2, 21,"gout_mif_mux_cmu_peri_uart0" ,"mout_mif_cmu_peri_uart0" , CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0, 21,"gout_mif_mux_busd" , "mout_mif_busd" ,"gout_mif_mux_media_pll" ,"gout_mif_mux_media_pll_con" , CLK_CON_GAT_MIF_MUX_MEDIA_PLL, 21,"gout_mif_mux_media_pll_con" ,"fout_mif_media_pll" , CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON, 12,"gout_mif_mux_mem_pll" ,"gout_mif_mux_mem_pll_con" , CLK_CON_GAT_MIF_MUX_MEM_PLL, 21,"gout_mif_mux_mem_pll_con" ,"fout_mif_mem_pll" , CLK_CON_GAT_MIF_MUX_MEM_PLL_CON, 12,static const struct samsung_cmu_info mif_cmu_info __initconst = {/* * Register offsets for CMU_DISPAUD (0x148d0000) #define PLL_LOCKTIME_DISPAUD_PLL 0x0000#define PLL_LOCKTIME_DISPAUD_AUD_PLL 0x00c0#define PLL_CON0_DISPAUD_PLL 0x0100#define PLL_CON0_DISPAUD_AUD_PLL 0x01c0#define CLK_CON_GAT_DISPAUD_MUX_PLL 0x0200#define CLK_CON_GAT_DISPAUD_MUX_PLL_CON 0x0200#define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL 0x0204#define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON 0x0204#define CLK_CON_GAT_DISPAUD_MUX_BUS_USER 0x0210#define CLK_CON_MUX_DISPAUD_BUS_USER 0x0210#define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER 0x0214#define CLK_CON_MUX_DISPAUD_DECON_VCLK_USER 0x0214#define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER 0x0218#define CLK_CON_MUX_DISPAUD_DECON_ECLK_USER 0x0218#define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK 0x021c#define CLK_CON_MUX_DISPAUD_DECON_VCLK 0x021c#define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK 0x0220#define CLK_CON_MUX_DISPAUD_DECON_ECLK 0x0220#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 0x0224#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 0x0224#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 0x0228#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 0x0228#define CLK_CON_GAT_DISPAUD_MUX_MI2S 0x022c#define CLK_CON_MUX_DISPAUD_MI2S 0x022c#define CLK_CON_DIV_DISPAUD_APB 0x0400#define CLK_CON_DIV_DISPAUD_DECON_VCLK 0x0404#define CLK_CON_DIV_DISPAUD_DECON_ECLK 0x0408#define CLK_CON_DIV_DISPAUD_MI2S 0x040c#define CLK_CON_DIV_DISPAUD_MIXER 0x0410#define CLK_CON_GAT_DISPAUD_BUS 0x0810#define CLK_CON_GAT_DISPAUD_BUS_DISP 0x0810#define CLK_CON_GAT_DISPAUD_BUS_PPMU 0x0810#define CLK_CON_GAT_DISPAUD_APB_AUD 0x0814#define CLK_CON_GAT_DISPAUD_APB_AUD_AMP 0x0814#define CLK_CON_GAT_DISPAUD_APB_DISP 0x0814#define CLK_CON_GAT_DISPAUD_DECON_VCLK 0x081c#define CLK_CON_GAT_DISPAUD_DECON_ECLK 0x0820#define CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI 0x082c#define CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI 0x082c#define CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK 0x0830#define CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 0x0834#define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 0x0838#define CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK 0x083c#define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 0x0840static const unsigned long dispaud_clk_regs[] __initconst = {static const struct samsung_fixed_rate_clock dispaud_fixed_clks[] __initconst = {"frat_dispaud_audiocdclk0" , NULL, 0, 100000000),"frat_dispaud_mixer_bclk_bt" , NULL, 0, 12500000),"frat_dispaud_mixer_bclk_cp" , NULL, 0, 12500000),"frat_dispaud_mixer_bclk_fm" , NULL, 0, 12500000),"frat_dispaud_mixer_sclk_ap" , NULL, 0, 12500000),"frat_dispaud_mipiphy_rxclkesc0" , NULL, 0, 188000000),"frat_dispaud_mipiphy_txbyteclkhs" , NULL, 0, 188000000),static const struct samsung_pll_clock dispaud_pll_clks[] __initconst = {"fout_dispaud_aud_pll" ,"oscclk" , PLL_LOCKTIME_DISPAUD_AUD_PLL, PLL_CON0_DISPAUD_AUD_PLL,"fout_dispaud_pll" , "oscclk" ,/* List of parent clocks for muxes in CMU_DISPAUD */ "oscclk" , "gout_mif_cmu_dispaud_bus" };"oscclk" ,"gout_mif_cmu_dispaud_decon_eclk" };"oscclk" ,"gout_mif_cmu_dispaud_decon_vclk" };"gout_dispaud_mux_decon_eclk_user" ,"gout_dispaud_mux_pll_con" };"gout_dispaud_mux_decon_vclk_user" ,"gout_dispaud_mux_pll_con" };"gout_dispaud_mux_aud_pll_con" ,"frat_dispaud_audiocdclk0" };static const struct samsung_mux_clock dispaud_mux_clks[] __initconst = {"mout_dispaud_bus_user" ,"mout_dispaud_decon_eclk_user" ,"mout_dispaud_decon_vclk_user" ,"mout_dispaud_decon_eclk" ,"mout_dispaud_decon_vclk" ,"mout_dispaud_mi2s" , mout_dispaud_mi2s_p,static const struct samsung_div_clock dispaud_div_clks[] __initconst = {"dout_dispaud_apb" ,"gout_dispaud_mux_bus_user" , CLK_CON_DIV_DISPAUD_APB, 0, 2),"dout_dispaud_decon_eclk" ,"gout_dispaud_mux_decon_eclk" , CLK_CON_DIV_DISPAUD_DECON_ECLK, 0, 3),"dout_dispaud_decon_vclk" ,"gout_dispaud_mux_decon_vclk" , CLK_CON_DIV_DISPAUD_DECON_VCLK, 0, 3),"dout_dispaud_mi2s" , "gout_dispaud_mux_mi2s" ,"dout_dispaud_mixer" ,"gout_dispaud_mux_aud_pll_con" , CLK_CON_DIV_DISPAUD_MIXER, 0, 4),static const struct samsung_gate_clock dispaud_gate_clks[] __initconst = {"gout_dispaud_bus" ,"gout_dispaud_mux_bus_user" , CLK_CON_GAT_DISPAUD_BUS, 0,"gout_dispaud_bus_disp" ,"gout_dispaud_mux_bus_user" , CLK_CON_GAT_DISPAUD_BUS_DISP, 2,"gout_dispaud_bus_ppmu" ,"gout_dispaud_mux_bus_user" , CLK_CON_GAT_DISPAUD_BUS_PPMU, 3,"gout_dispaud_apb_aud" ,"dout_dispaud_apb" , CLK_CON_GAT_DISPAUD_APB_AUD, 2,"gout_dispaud_apb_aud_amp" ,"dout_dispaud_apb" , CLK_CON_GAT_DISPAUD_APB_AUD_AMP, 3,"gout_dispaud_apb_disp" ,"dout_dispaud_apb" , CLK_CON_GAT_DISPAUD_APB_DISP, 1,"gout_dispaud_con_aud_i2s_bclk_bt_in" ,"frat_dispaud_mixer_bclk_bt" ,"gout_dispaud_con_aud_i2s_bclk_fm_in" ,"frat_dispaud_mixer_bclk_fm" ,"gout_dispaud_con_cp2aud_bck" ,"frat_dispaud_mixer_bclk_cp" , CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK,"gout_dispaud_con_ext2aud_bck_gpio_i2s" ,"frat_dispaud_mixer_sclk_ap" ,"gout_dispaud_decon_eclk" ,"dout_dispaud_decon_eclk" , CLK_CON_GAT_DISPAUD_DECON_ECLK, 0,"gout_dispaud_decon_vclk" ,"dout_dispaud_decon_vclk" , CLK_CON_GAT_DISPAUD_DECON_VCLK, 0,"gout_dispaud_mi2s_amp_i2scodclki" , "dout_dispaud_mi2s" ,"gout_dispaud_mi2s_aud_i2scodclki" , "dout_dispaud_mi2s" ,"gout_dispaud_mixer_aud_sysclk" ,"dout_dispaud_mixer" , CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK, 0,"gout_dispaud_mux_aud_pll" ,"gout_dispaud_mux_aud_pll_con" , CLK_CON_GAT_DISPAUD_MUX_AUD_PLL,"gout_dispaud_mux_aud_pll_con" ,"fout_dispaud_aud_pll" , CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON, 12,"gout_dispaud_mux_bus_user" ,"mout_dispaud_bus_user" , CLK_CON_GAT_DISPAUD_MUX_BUS_USER, 21,"gout_dispaud_mux_decon_eclk_user" , "mout_dispaud_decon_eclk_user" ,"gout_dispaud_mux_decon_vclk_user" , "mout_dispaud_decon_vclk_user" ,"gout_dispaud_mux_mipiphy_rxclkesc0_user" ,"gout_dispaud_mux_mipiphy_rxclkesc0_user_con" ,"gout_dispaud_mux_mipiphy_rxclkesc0_user_con" ,"frat_dispaud_mipiphy_rxclkesc0" ,"gout_dispaud_mux_mipiphy_txbyteclkhs_user" ,"gout_dispaud_mux_mipiphy_txbyteclkhs_user_con" ,"gout_dispaud_mux_mipiphy_txbyteclkhs_user_con" ,"frat_dispaud_mipiphy_txbyteclkhs" ,"gout_dispaud_mux_decon_eclk" ,"mout_dispaud_decon_eclk" , CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK, 21,"gout_dispaud_mux_decon_vclk" ,"mout_dispaud_decon_vclk" , CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK, 21,"gout_dispaud_mux_mi2s" ,"mout_dispaud_mi2s" , CLK_CON_GAT_DISPAUD_MUX_MI2S, 21,"gout_dispaud_mux_pll" ,"gout_dispaud_mux_pll_con" , CLK_CON_GAT_DISPAUD_MUX_PLL, 21,"gout_dispaud_mux_pll_con" ,"fout_dispaud_pll" , CLK_CON_GAT_DISPAUD_MUX_PLL_CON, 12,static const struct samsung_cmu_info dispaud_cmu_info __initconst = {/* * Register offsets for CMU_FSYS (0x13730000) #define PLL_LOCKTIME_FSYS_USB_PLL 0x0000#define PLL_CON0_FSYS_USB_PLL 0x0100#define CLK_CON_GAT_FSYS_MUX_USB_PLL 0x0200#define CLK_CON_GAT_FSYS_MUX_USB_PLL_CON 0x0200#define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 0x0230#define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 0x0230#define CLK_CON_GAT_FSYS_BUSP3_HCLK 0x0804#define CLK_CON_GAT_FSYS_MMC0_ACLK 0x0804#define CLK_CON_GAT_FSYS_MMC1_ACLK 0x0804#define CLK_CON_GAT_FSYS_MMC2_ACLK 0x0804#define CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0 0x0804#define CLK_CON_GAT_FSYS_PPMU_ACLK 0x0804#define CLK_CON_GAT_FSYS_PPMU_PCLK 0x0804#define CLK_CON_GAT_FSYS_SROMC_HCLK 0x0804#define CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK 0x0804#define CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD 0x0804#define CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL 0x0804#define CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK 0x0828static const unsigned long fsys_clk_regs[] __initconst = {static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {"frat_fsys_usb20drd_phyclock" , NULL, 0, 60000000),static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {"fout_fsys_usb_pll" , "oscclk" ,static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {"gout_fsys_busp3_hclk" ,"gout_mif_cmu_fsys_bus" , CLK_CON_GAT_FSYS_BUSP3_HCLK, 2,"gout_fsys_mmc0_aclk" ,"gout_fsys_busp3_hclk" , CLK_CON_GAT_FSYS_MMC0_ACLK, 8,"gout_fsys_mmc1_aclk" ,"gout_fsys_busp3_hclk" , CLK_CON_GAT_FSYS_MMC1_ACLK, 9,"gout_fsys_mmc2_aclk" ,"gout_fsys_busp3_hclk" , CLK_CON_GAT_FSYS_MMC2_ACLK, 10,"gout_fsys_pdma0_aclk_pdma0" ,"gout_fsys_upsizer_bus1_aclk" , CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0,"gout_fsys_ppmu_aclk" ,"gout_mif_cmu_fsys_bus" , CLK_CON_GAT_FSYS_PPMU_ACLK, 17,"gout_fsys_ppmu_pclk" ,"gout_mif_cmu_fsys_bus" , CLK_CON_GAT_FSYS_PPMU_PCLK, 18,"gout_fsys_sromc_hclk" ,"gout_fsys_busp3_hclk" , CLK_CON_GAT_FSYS_SROMC_HCLK, 6,"gout_fsys_upsizer_bus1_aclk" ,"gout_mif_cmu_fsys_bus" , CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK, 12,"gout_fsys_usb20drd_aclk_hsdrd" ,"gout_fsys_busp3_hclk" , CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD, 20,"gout_fsys_usb20drd_hclk_usb20_ctrl" , "gout_fsys_busp3_hclk" ,"gout_fsys_usb20drd_hsdrd_ref_clk" ,"gout_mif_cmu_fsys_usb20drd_refclk" ,"gout_fsys_mux_usb20drd_phyclock_user" ,"gout_fsys_mux_usb20drd_phyclock_user_con" ,"gout_fsys_mux_usb20drd_phyclock_user_con" ,"frat_fsys_usb20drd_phyclock" ,"gout_fsys_mux_usb_pll" ,"gout_fsys_mux_usb_pll_con" , CLK_CON_GAT_FSYS_MUX_USB_PLL, 21,"gout_fsys_mux_usb_pll_con" ,"fout_fsys_usb_pll" , CLK_CON_GAT_FSYS_MUX_USB_PLL_CON, 12,static const struct samsung_cmu_info fsys_cmu_info __initconst = {/* * Register offsets for CMU_G3D (0x11460000) #define PLL_LOCKTIME_G3D_PLL 0x0000#define PLL_CON0_G3D_PLL 0x0100#define CLK_CON_GAT_G3D_MUX_PLL 0x0200#define CLK_CON_GAT_G3D_MUX_PLL_CON 0x0200#define CLK_CON_GAT_G3D_MUX_SWITCH_USER 0x0204#define CLK_CON_MUX_G3D_SWITCH_USER 0x0204#define CLK_CON_GAT_G3D_MUX 0x0208#define CLK_CON_MUX_G3D 0x0208#define CLK_CON_DIV_G3D_BUS 0x0400#define CLK_CON_DIV_G3D_APB 0x0404#define CLK_CON_GAT_G3D_ASYNCS_D0_CLK 0x0804#define CLK_CON_GAT_G3D_ASYNC_PCLKM 0x0804#define CLK_CON_GAT_G3D_CLK 0x0804#define CLK_CON_GAT_G3D_PPMU_ACLK 0x0804#define CLK_CON_GAT_G3D_QE_ACLK 0x0804#define CLK_CON_GAT_G3D_PPMU_PCLK 0x0808#define CLK_CON_GAT_G3D_QE_PCLK 0x0808#define CLK_CON_GAT_G3D_SYSREG_PCLK 0x0808static const unsigned long g3d_clk_regs[] __initconst = {static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {"fout_g3d_pll" , "oscclk" ,/* List of parent clocks for muxes in CMU_G3D */ "oscclk" , "gout_mif_cmu_g3d_switch" };"gout_g3d_mux_pll_con" ,"gout_g3d_mux_switch_user" };static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {"mout_g3d_switch_user" ,"mout_g3d" , mout_g3d_p, CLK_CON_MUX_G3D, 12, 1),static const struct samsung_div_clock g3d_div_clks[] __initconst = {"dout_g3d_apb" , "dout_g3d_bus" ,"dout_g3d_bus" , "gout_g3d_mux" ,static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {"gout_g3d_asyncs_d0_clk" ,"dout_g3d_bus" , CLK_CON_GAT_G3D_ASYNCS_D0_CLK, 1, CLK_IS_CRITICAL |"gout_g3d_async_pclkm" , "dout_g3d_bus" ,"gout_g3d_clk" , "dout_g3d_bus" ,"gout_g3d_ppmu_aclk" , "dout_g3d_bus" ,"gout_g3d_ppmu_pclk" , "dout_g3d_apb" ,"gout_g3d_qe_aclk" , "dout_g3d_bus" ,"gout_g3d_qe_pclk" , "dout_g3d_apb" ,"gout_g3d_sysreg_pclk" , "dout_g3d_apb" ,"gout_g3d_mux_switch_user" ,"mout_g3d_switch_user" , CLK_CON_GAT_G3D_MUX_SWITCH_USER, 21,"gout_g3d_mux" , "mout_g3d" , CLK_CON_GAT_G3D_MUX,"gout_g3d_mux_pll" , "gout_g3d_mux_pll_con" ,"gout_g3d_mux_pll_con" , "fout_g3d_pll" ,static const struct samsung_cmu_info g3d_cmu_info __initconst = {/* * Register offsets for CMU_ISP (0x144d0000) #define PLL_LOCKTIME_ISP_PLL 0x0000#define PLL_CON0_ISP_PLL 0x0100#define CLK_CON_GAT_ISP_MUX_PLL 0x0200#define CLK_CON_GAT_ISP_MUX_PLL_CON 0x0200#define CLK_CON_GAT_ISP_MUX_VRA_USER 0x0210#define CLK_CON_MUX_ISP_VRA_USER 0x0210#define CLK_CON_GAT_ISP_MUX_CAM_USER 0x0214#define CLK_CON_MUX_ISP_CAM_USER 0x0214#define CLK_CON_GAT_ISP_MUX_USER 0x0218#define CLK_CON_MUX_ISP_USER 0x0218#define CLK_CON_GAT_ISP_MUX_VRA 0x0220#define CLK_CON_MUX_ISP_VRA 0x0220#define CLK_CON_GAT_ISP_MUX_CAM 0x0224#define CLK_CON_MUX_ISP_CAM 0x0224#define CLK_CON_GAT_ISP_MUX_ISP 0x0228#define CLK_CON_MUX_ISP_ISP 0x0228#define CLK_CON_GAT_ISP_MUX_ISPD 0x022c#define CLK_CON_MUX_ISP_ISPD 0x022c#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 0x0230#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 0x0230#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 0x0234#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 0x0234#define CLK_CON_DIV_ISP_APB 0x0400#define CLK_CON_DIV_ISP_CAM_HALF 0x0404#define CLK_CON_GAT_ISP_VRA 0x0810#define CLK_CON_GAT_ISP_ISPD 0x0818#define CLK_CON_GAT_ISP_ISPD_PPMU 0x0818#define CLK_CON_GAT_ISP_CAM 0x081c#define CLK_CON_GAT_ISP_CAM_HALF 0x0820static const unsigned long isp_clk_regs[] __initconst = {static const struct samsung_fixed_rate_clock isp_fixed_clks[] __initconst = {"frat_isp_rxbyteclkhs0_sensor0" , NULL, 0, 188000000),"frat_isp_rxbyteclkhs0_sensor1" , NULL, 0, 188000000),static const struct samsung_pll_clock isp_pll_clks[] __initconst = {"fout_isp_pll" , "oscclk" ,/* List of parent clocks for muxes in CMU_ISP */ "oscclk" , "gout_mif_cmu_isp_cam" };"oscclk" , "gout_mif_cmu_isp_isp" };"oscclk" , "gout_mif_cmu_isp_vra" };"gout_isp_mux_cam_user" ,"gout_isp_mux_pll_con" };"gout_isp_mux_user" , "gout_isp_mux_pll_con" };"gout_isp_mux_vra" , "gout_isp_mux_cam" };"gout_isp_mux_vra_user" ,"gout_isp_mux_pll_con" };static const struct samsung_mux_clock isp_mux_clks[] __initconst = {"mout_isp_cam_user" , mout_isp_cam_user_p,"mout_isp_user" , mout_isp_user_p,"mout_isp_vra_user" , mout_isp_vra_user_p,"mout_isp_cam" , mout_isp_cam_p,"mout_isp_isp" , mout_isp_isp_p,"mout_isp_ispd" , mout_isp_ispd_p,"mout_isp_vra" , mout_isp_vra_p,static const struct samsung_div_clock isp_div_clks[] __initconst = {"dout_isp_apb" , "gout_isp_mux_vra" ,"dout_isp_cam_half" , "gout_isp_mux_cam" ,static const struct samsung_gate_clock isp_gate_clks[] __initconst = {"gout_isp_cam" , "gout_isp_mux_cam" ,"gout_isp_cam_half" , "dout_isp_cam_half" ,"gout_isp_ispd" , "gout_isp_mux_ispd" ,"gout_isp_ispd_ppmu" , "gout_isp_mux_ispd" ,"gout_isp_vra" , "gout_isp_mux_vra" ,"gout_isp_mux_cam_user" ,"mout_isp_cam_user" , CLK_CON_GAT_ISP_MUX_CAM_USER, 21,"gout_isp_mux_user" , "mout_isp_user" ,"gout_isp_mux_vra_user" ,"mout_isp_vra_user" , CLK_CON_GAT_ISP_MUX_VRA_USER, 21,"gout_isp_mux_rxbyteclkhs0_sensor1_user" ,"gout_isp_mux_rxbyteclkhs0_sensor1_user_con" ,"gout_isp_mux_rxbyteclkhs0_sensor1_user_con" ,"frat_isp_rxbyteclkhs0_sensor1" ,"gout_isp_mux_rxbyteclkhs0_sensor0_user" ,"gout_isp_mux_rxbyteclkhs0_sensor0_user_con" ,"gout_isp_mux_rxbyteclkhs0_sensor0_user_con" ,"frat_isp_rxbyteclkhs0_sensor0" ,"gout_isp_mux_cam" , "mout_isp_cam" ,"gout_isp_mux_isp" , "mout_isp_isp" ,
Messung V0.5 C=100 H=100 G=100
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