// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2023 Linaro Ltd. * Author: Peter Griffin <peter.griffin@linaro.org> * * Common Clock Framework support for GS101. #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/of.h>#include <linux/platform_device.h>#include <dt-bindings/clock/google,gs101.h>#include "clk.h" #include "clk-exynos-arm64.h" #include "clk-pll.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)/* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x1e080000) */ #define PLL_LOCKTIME_PLL_SHARED0 0x0000#define PLL_LOCKTIME_PLL_SHARED1 0x0004#define PLL_LOCKTIME_PLL_SHARED2 0x0008#define PLL_LOCKTIME_PLL_SHARED3 0x000c#define PLL_LOCKTIME_PLL_SPARE 0x0010#define PLL_CON0_PLL_SHARED0 0x0100#define PLL_CON1_PLL_SHARED0 0x0104#define PLL_CON2_PLL_SHARED0 0x0108#define PLL_CON3_PLL_SHARED0 0x010c#define PLL_CON4_PLL_SHARED0 0x0110#define PLL_CON0_PLL_SHARED1 0x0140#define PLL_CON1_PLL_SHARED1 0x0144#define PLL_CON2_PLL_SHARED1 0x0148#define PLL_CON3_PLL_SHARED1 0x014c#define PLL_CON4_PLL_SHARED1 0x0150#define PLL_CON0_PLL_SHARED2 0x0180#define PLL_CON1_PLL_SHARED2 0x0184#define PLL_CON2_PLL_SHARED2 0x0188#define PLL_CON3_PLL_SHARED2 0x018c#define PLL_CON4_PLL_SHARED2 0x0190#define PLL_CON0_PLL_SHARED3 0x01c0#define PLL_CON1_PLL_SHARED3 0x01c4#define PLL_CON2_PLL_SHARED3 0x01c8#define PLL_CON3_PLL_SHARED3 0x01cc#define PLL_CON4_PLL_SHARED3 0x01d0#define PLL_CON0_PLL_SPARE 0x0200#define PLL_CON1_PLL_SPARE 0x0204#define PLL_CON2_PLL_SPARE 0x0208#define PLL_CON3_PLL_SPARE 0x020c#define PLL_CON4_PLL_SPARE 0x0210#define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810#define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840#define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844#define CMU_HCHGEN_CLKMUX 0x0850#define POWER_FAIL_DETECT_PLL 0x0864#define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870#define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874#define EARLY_WAKEUP_APM_CTRL 0x0878#define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c#define EARLY_WAKEUP_DPU_CTRL 0x0880#define EARLY_WAKEUP_CSIS_CTRL 0x0884#define EARLY_WAKEUP_APM_DEST 0x0890#define EARLY_WAKEUP_CLUSTER0_DEST 0x0894#define EARLY_WAKEUP_DPU_DEST 0x0898#define EARLY_WAKEUP_CSIS_DEST 0x089c#define EARLY_WAKEUP_SW_TRIG_APM 0x08c0#define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8#define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8#define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0#define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8#define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0#define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104#define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108#define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804#define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808#define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c#define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820#define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824#define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828#define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840#define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844#define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848#define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c#define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850#define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c#define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860#define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864#define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c#define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870#define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874#define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878#define CLK_CON_DIV_CLKCMU_HPM 0x187c#define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c#define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894#define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c#define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4#define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8#define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac#define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0#define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc#define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0#define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4#define CLK_CON_DIV_CLKCMU_OTP 0x18c8#define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc#define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0#define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4#define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8#define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0#define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c#define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920#define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000#define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004#define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008#define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018#define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c#define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020#define DMYQCH_CON_OTP_QCH 0x3024#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c#define MIFMIRROR_QUEUE_CTRL_REG 0x3e00#define MIFMIRROR_QUEUE_ENTRY0 0x3e10#define MIFMIRROR_QUEUE_ENTRY1 0x3e14#define MIFMIRROR_QUEUE_ENTRY2 0x3e18#define MIFMIRROR_QUEUE_ENTRY3 0x3e1c#define MIFMIRROR_QUEUE_ENTRY4 0x3e20#define MIFMIRROR_QUEUE_ENTRY5 0x3e24#define MIFMIRROR_QUEUE_ENTRY6 0x3e28#define MIFMIRROR_QUEUE_ENTRY7 0x3e2c#define MIFMIRROR_QUEUE_BUSY 0x3e30#define GENERALIO_ACD_CHANNEL_0 0x3f00#define GENERALIO_ACD_CHANNEL_1 0x3f04#define GENERALIO_ACD_CHANNEL_2 0x3f08#define GENERALIO_ACD_CHANNEL_3 0x3f0c#define GENERALIO_ACD_MASK 0x3f14static const unsigned long cmu_top_clk_regs[] __initconst = {static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {/* CMU_TOP_PURECLKCOMP */ "fout_shared0_pll" , "oscclk" ,"fout_shared1_pll" , "oscclk" ,"fout_shared2_pll" , "oscclk" ,"fout_shared3_pll" , "oscclk" ,"fout_spare_pll" , "oscclk" ,/* List of parent clocks for Muxes in CMU_TOP */ "oscclk" , "fout_shared0_pll" };"oscclk" , "fout_shared1_pll" };"oscclk" , "fout_shared2_pll" };"oscclk" , "fout_shared3_pll" };"oscclk" , "fout_spare_pll" };"fout_shared2_pll" , "dout_cmu_shared0_div3" ,"fout_shared3_pll" , "dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" ,"fout_spare_pll" , "oscclk" ,"oscclk" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div5" , "fout_spare_pll" };"oscclk" , "dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" ,"oscclk" , "oscclk" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" };"dout_cmu_cmu_boost" ,"gout_cmu_boost_option1" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div5" , "fout_spare_pll" };"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" , "fout_spare_pll" ,"oscclk" , "oscclk" };"fout_shared1_pll" , "dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" , "fout_shared2_pll" ,"fout_shared3_pll" , "dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" , "fout_spare_pll" };"fout_shared1_pll" , "dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" , "fout_shared2_pll" ,"fout_shared3_pll" , "dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" , "fout_spare_pll" };"fout_shared1_pll" , "dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" , "fout_shared2_pll" ,"fout_shared3_pll" , "dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" , "fout_spare_pll" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" ,"fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div5" , "fout_spare_pll" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" ,"fout_spare_pll" , "oscclk" ,"oscclk" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" , "fout_spare_pll" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" , "fout_spare_pll" };"fout_shared2_pll" , "dout_cmu_shared0_div3" ,"fout_shared3_pll" , "dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"fout_spare_pll" , "fout_spare_pll" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"oscclk" , "dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" ,"fout_spare_pll" , "oscclk" ,"oscclk" , "oscclk" };"oscclk" , "dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" , "fout_spare_pll" };"oscclk" , "dout_cmu_shared2_div2" };"oscclk" , "dout_cmu_shared2_div2" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" ,"fout_spare_pll" };"oscclk" , "dout_cmu_shared2_div2" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" ,"fout_spare_pll" , "oscclk" ,"oscclk" , "oscclk" };"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div4" , "fout_spare_pll" };"oscclk" , "dout_cmu_shared2_div2" };"oscclk" , "dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" , "fout_spare_pll" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" , "fout_spare_pll" ,"oscclk" , "oscclk" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared0_div5" , "fout_spare_pll" };"fout_shared0_pll" , "fout_shared1_pll" ,"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "dout_cmu_shared0_div3" ,"fout_shared3_pll" , "fout_spare_pll" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"fout_shared2_pll" , "dout_cmu_shared0_div3" ,"fout_shared3_pll" , "dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"fout_spare_pll" , "oscclk" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"dout_cmu_shared0_div3" , "fout_shared3_pll" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"fout_spare_pll" , "oscclk" };"oscclk" ,"gout_cmu_boost_option1" };"dout_cmu_shared0_div4" ,"dout_cmu_shared1_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" ,"fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" ,"fout_spare_pll" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" ,"fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" , "fout_spare_pll" };"dout_cmu_shared0_div2" ,"dout_cmu_shared1_div2" ,"fout_shared2_pll" , "fout_shared3_pll" ,"dout_cmu_shared0_div3" ,"dout_cmu_shared1_div3" ,"dout_cmu_shared0_div4" , "fout_spare_pll" };"dout_cmu_shared0_div4" ,"dout_cmu_shared2_div2" ,"dout_cmu_shared3_div2" , "fout_spare_pll" };"mout_cmu_top_boost_option1" ,"dout_cmu_cmuref" };/* * Register name to clock name mangling strategy used in this file * * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu * * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {"mout_pll_shared0" , mout_pll_shared0_p,"mout_pll_shared1" , mout_pll_shared1_p,"mout_pll_shared2" , mout_pll_shared2_p,"mout_pll_shared3" , mout_pll_shared3_p,"mout_pll_spare" , mout_pll_spare_p,"mout_cmu_bo_bus" , mout_cmu_bo_bus_p,"mout_cmu_bus0_bus" , mout_cmu_bus0_bus_p,"mout_cmu_bus1_bus" , mout_cmu_bus1_bus_p,"mout_cmu_bus2_bus" , mout_cmu_bus2_bus_p,"mout_cmu_cis_clk0" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk1" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk2" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk3" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk4" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk5" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk6" , mout_cmu_cis_clk0_7_p,"mout_cmu_cis_clk7" , mout_cmu_cis_clk0_7_p,"mout_cmu_cmu_boost" , mout_cmu_cmu_boost_p,"mout_cmu_boost_option1" ,"mout_cmu_core_bus" , mout_cmu_core_bus_p,"mout_cmu_cpucl0_dbg" ,"mout_cmu_cpucl0_switch" ,"mout_cmu_cpucl1_switch" ,"mout_cmu_cpucl2_switch" ,"mout_cmu_csis_bus" , mout_cmu_csis_bus_p,"mout_cmu_disp_bus" , mout_cmu_disp_bus_p,"mout_cmu_dns_bus" , mout_cmu_dns_bus_p,"mout_cmu_dpu_bus" , mout_cmu_dpu_p,"mout_cmu_eh_bus" , mout_cmu_eh_bus_p,"mout_cmu_g2d_g2d" , mout_cmu_g2d_g2d_p,"mout_cmu_g2d_mscl" , mout_cmu_g2d_mscl_p,"mout_cmu_g3aa_g3aa" , mout_cmu_g3aa_g3aa_p,"mout_cmu_g3d_busd" , mout_cmu_g3d_busd_p,"mout_cmu_g3d_glb" , mout_cmu_g3d_glb_p,"mout_cmu_g3d_switch" ,"mout_cmu_gdc_gdc0" , mout_cmu_gdc_gdc0_p,"mout_cmu_gdc_gdc1" , mout_cmu_gdc_gdc1_p,"mout_cmu_gdc_scsc" , mout_cmu_gdc_scsc_p,"mout_cmu_hpm" , mout_cmu_hpm_p,"mout_cmu_hsi0_bus" , mout_cmu_hsi0_bus_p,"mout_cmu_hsi0_dpgtc" ,"mout_cmu_hsi0_usb31drd" ,"mout_cmu_hsi0_usbdpdbg" ,"mout_cmu_hsi1_bus" , mout_cmu_hsi1_bus_p,"mout_cmu_hsi1_pcie" , mout_cmu_hsi1_pcie_p,"mout_cmu_hsi2_bus" , mout_cmu_hsi2_bus_p,"mout_cmu_hsi2_mmc_card" ,"mout_cmu_hsi2_pcie" , mout_cmu_hsi2_pcie0_p,"mout_cmu_hsi2_ufs_embd" ,"mout_cmu_ipp_bus" , mout_cmu_ipp_bus_p,"mout_cmu_itp_bus" , mout_cmu_itp_bus_p,"mout_cmu_mcsc_itsc" , mout_cmu_mcsc_itsc_p,"mout_cmu_mcsc_mcsc" , mout_cmu_mcsc_mcsc_p,"mout_cmu_mfc_mfc" , mout_cmu_mfc_mfc_p,"mout_cmu_mif_busp" , mout_cmu_mif_busp_p,"mout_cmu_mif_switch" ,"mout_cmu_misc_bus" , mout_cmu_misc_bus_p,"mout_cmu_misc_sss" , mout_cmu_misc_sss_p,"mout_cmu_pdp_bus" , mout_cmu_pdp_bus_p,"mout_cmu_pdp_vra" , mout_cmu_pdp_vra_p,"mout_cmu_peric0_bus" ,"mout_cmu_peric0_ip" , mout_cmu_peric0_ip_p,"mout_cmu_peric1_bus" ,"mout_cmu_peric1_ip" , mout_cmu_peric1_ip_p,"mout_cmu_tnr_bus" , mout_cmu_tnr_bus_p,"mout_cmu_top_boost_option1" ,"mout_cmu_top_cmuref" ,"mout_cmu_tpu_bus" , mout_cmu_tpu_bus_p,"mout_cmu_tpu_tpu" , mout_cmu_tpu_tpu_p,"mout_cmu_tpu_tpuctl" ,"mout_cmu_tpu_uart" , mout_cmu_tpu_uart_p,"mout_cmu_cmuref" , mout_cmu_cmuref_p,static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {"dout_cmu_bo_bus" , "gout_cmu_bo_bus" ,"dout_cmu_bus0_bus" , "gout_cmu_bus0_bus" ,"dout_cmu_bus1_bus" , "gout_cmu_bus1_bus" ,"dout_cmu_bus2_bus" , "gout_cmu_bus2_bus" ,"dout_cmu_cis_clk0" , "gout_cmu_cis_clk0" ,"dout_cmu_cis_clk1" , "gout_cmu_cis_clk1" ,"dout_cmu_cis_clk2" , "gout_cmu_cis_clk2" ,"dout_cmu_cis_clk3" , "gout_cmu_cis_clk3" ,"dout_cmu_cis_clk4" , "gout_cmu_cis_clk4" ,"dout_cmu_cis_clk5" , "gout_cmu_cis_clk5" ,"dout_cmu_cis_clk6" , "gout_cmu_cis_clk6" ,"dout_cmu_cis_clk7" , "gout_cmu_cis_clk7" ,"dout_cmu_core_bus" , "gout_cmu_core_bus" ,"dout_cmu_cpucl0_dbg" ,"gout_cmu_cpucl0_dbg" , CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),"dout_cmu_cpucl0_switch" ,"gout_cmu_cpucl0_switch" , CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),"dout_cmu_cpucl1_switch" ,"gout_cmu_cpucl1_switch" , CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),"dout_cmu_cpucl2_switch" ,"gout_cmu_cpucl2_switch" , CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),"dout_cmu_csis_bus" , "gout_cmu_csis_bus" ,"dout_cmu_disp_bus" , "gout_cmu_disp_bus" ,"dout_cmu_dns_bus" , "gout_cmu_dns_bus" ,"dout_cmu_dpu_bus" , "gout_cmu_dpu_bus" ,"dout_cmu_eh_bus" , "gout_cmu_eh_bus" ,"dout_cmu_g2d_g2d" , "gout_cmu_g2d_g2d" ,"dout_cmu_g2d_mscl" , "gout_cmu_g2d_mscl" ,"dout_cmu_g3aa_g3aa" , "gout_cmu_g3aa_g3aa" ,"dout_cmu_g3d_busd" , "gout_cmu_g3d_busd" ,"dout_cmu_g3d_glb" , "gout_cmu_g3d_glb" ,"dout_cmu_g3d_switch" ,"gout_cmu_g3d_switch" , CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),"dout_cmu_gdc_gdc0" , "gout_cmu_gdc_gdc0" ,"dout_cmu_gdc_gdc1" , "gout_cmu_gdc_gdc1" ,"dout_cmu_gdc_scsc" , "gout_cmu_gdc_scsc" ,"dout_cmu_hpm" , "gout_cmu_hpm" ,"dout_cmu_hsi0_bus" , "gout_cmu_hsi0_bus" ,"dout_cmu_hsi0_dpgtc" ,"gout_cmu_hsi0_dpgtc" , CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),"dout_cmu_hsi0_usb31drd" ,"gout_cmu_hsi0_usb31drd" , CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),"dout_cmu_hsi1_bus" , "gout_cmu_hsi1_bus" ,"dout_cmu_hsi1_pcie" , "gout_cmu_hsi1_pcie" ,"dout_cmu_hsi2_bus" , "gout_cmu_hsi2_bus" ,"dout_cmu_hsi2_mmc_card" ,"gout_cmu_hsi2_mmc_card" , CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),"dout_cmu_hsi2_pcie" , "gout_cmu_hsi2_pcie" ,"dout_cmu_hsi2_ufs_embd" ,"gout_cmu_hsi2_ufs_embd" , CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),"dout_cmu_ipp_bus" , "gout_cmu_ipp_bus" ,"dout_cmu_itp_bus" , "gout_cmu_itp_bus" ,"dout_cmu_mcsc_itsc" , "gout_cmu_mcsc_itsc" ,"dout_cmu_mcsc_mcsc" , "gout_cmu_mcsc_mcsc" ,"dout_cmu_mfc_mfc" , "gout_cmu_mfc_mfc" ,"dout_cmu_mif_busp" , "gout_cmu_mif_busp" ,"dout_cmu_misc_bus" , "gout_cmu_misc_bus" ,"dout_cmu_misc_sss" , "gout_cmu_misc_sss" ,"dout_cmu_pdp_bus" , "gout_cmu_pdp_bus" ,"dout_cmu_pdp_vra" , "gout_cmu_pdp_vra" ,"dout_cmu_peric0_bus" ,"gout_cmu_peric0_bus" , CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),"dout_cmu_peric0_ip" , "gout_cmu_peric0_ip" ,"dout_cmu_peric1_bus" ,"gout_cmu_peric1_bus" , CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),"dout_cmu_peric1_ip" , "gout_cmu_peric1_ip" ,"dout_cmu_tnr_bus" , "gout_cmu_tnr_bus" ,"dout_cmu_tpu_bus" , "gout_cmu_tpu_bus" ,"dout_cmu_tpu_tpu" , "gout_cmu_tpu_tpu" ,"dout_cmu_tpu_tpuctl" ,"gout_cmu_tpu_tpuctl" , CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),"dout_cmu_tpu_uart" , "gout_cmu_tpu_uart" ,"dout_cmu_cmu_boost" , "gout_cmu_cmu_boost" ,"dout_cmu_cmuref" , "gout_cmu_cmuref" ,"dout_cmu_shared0_div2" ,"mout_pll_shared0" , CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),"dout_cmu_shared0_div3" ,"mout_pll_shared0" , CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),"dout_cmu_shared0_div4" ,"dout_cmu_shared0_div2" , CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),"dout_cmu_shared0_div5" ,"mout_pll_shared0" , CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),"dout_cmu_shared1_div2" ,"mout_pll_shared1" , CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),"dout_cmu_shared1_div3" ,"mout_pll_shared1" , CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),"dout_cmu_shared1_div4" ,"mout_pll_shared1" , CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),"dout_cmu_shared2_div2" ,"mout_pll_shared2" , CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),"dout_cmu_shared3_div2" ,"mout_pll_shared3" , CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {"dout_cmu_hsi0_usbdpdbg" ,"gout_cmu_hsi0_usbdpdbg" , 1, 4, 0),"dout_cmu_otp" , "oscclk" , 1, 8, 0),static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {"gout_cmu_bus0_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),"gout_cmu_bus1_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),"gout_cmu_bus2_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),"gout_cmu_core_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),"gout_cmu_cpucl0_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,"gout_cmu_cpucl1_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,"gout_cmu_cpucl2_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,"gout_cmu_mif_boost" ,"mout_cmu_boost_option1" , CLK_CON_GAT_CLKCMU_MIF_BOOST,"gout_cmu_mif_switch" ,"mout_cmu_mif_switch" , CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),"gout_cmu_bo_bus" , "mout_cmu_bo_bus" ,"gout_cmu_bus0_bus" , "mout_cmu_bus0_bus" ,"gout_cmu_bus1_bus" , "mout_cmu_bus1_bus" ,"gout_cmu_bus2_bus" , "mout_cmu_bus2_bus" ,"gout_cmu_cis_clk0" , "mout_cmu_cis_clk0" ,"gout_cmu_cis_clk1" , "mout_cmu_cis_clk1" ,"gout_cmu_cis_clk2" , "mout_cmu_cis_clk2" ,"gout_cmu_cis_clk3" , "mout_cmu_cis_clk3" ,"gout_cmu_cis_clk4" , "mout_cmu_cis_clk4" ,"gout_cmu_cis_clk5" , "mout_cmu_cis_clk5" ,"gout_cmu_cis_clk6" , "mout_cmu_cis_clk6" ,"gout_cmu_cis_clk7" , "mout_cmu_cis_clk7" ,"gout_cmu_cmu_boost" , "mout_cmu_cmu_boost" ,"gout_cmu_core_bus" , "mout_cmu_core_bus" ,"gout_cmu_cpucl0_dbg" ,"mout_cmu_cpucl0_dbg" , CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,"gout_cmu_cpucl0_switch" ,"mout_cmu_cpucl0_switch" , CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,"gout_cmu_cpucl1_switch" ,"mout_cmu_cpucl1_switch" , CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,"gout_cmu_cpucl2_switch" ,"mout_cmu_cpucl2_switch" , CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,"gout_cmu_csis_bus" , "mout_cmu_csis_bus" ,"gout_cmu_disp_bus" , "mout_cmu_disp_bus" ,"gout_cmu_dns_bus" , "mout_cmu_dns_bus" ,"gout_cmu_dpu_bus" , "mout_cmu_dpu_bus" ,"gout_cmu_eh_bus" , "mout_cmu_eh_bus" ,"gout_cmu_g2d_g2d" , "mout_cmu_g2d_g2d" ,"gout_cmu_g2d_mscl" , "mout_cmu_g2d_mscl" ,"gout_cmu_g3aa_g3aa" , "mout_cmu_g3aa_g3aa" ,"gout_cmu_g3d_busd" , "mout_cmu_g3d_busd" ,"gout_cmu_g3d_glb" , "mout_cmu_g3d_glb" ,"gout_cmu_g3d_switch" ,"mout_cmu_g3d_switch" , CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,"gout_cmu_gdc_gdc0" , "mout_cmu_gdc_gdc0" ,"gout_cmu_gdc_gdc1" , "mout_cmu_gdc_gdc1" ,"gout_cmu_gdc_scsc" , "mout_cmu_gdc_scsc" ,"gout_cmu_hpm" , "mout_cmu_hpm" ,"gout_cmu_hsi0_bus" , "mout_cmu_hsi0_bus" ,"gout_cmu_hsi0_dpgtc" ,"mout_cmu_hsi0_dpgtc" , CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,"gout_cmu_hsi0_usb31drd" ,"mout_cmu_hsi0_usb31drd" , CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,"gout_cmu_hsi0_usbdpdbg" ,"mout_cmu_hsi0_usbdpdbg" , CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,"gout_cmu_hsi1_bus" , "mout_cmu_hsi1_bus" ,"gout_cmu_hsi1_pcie" , "mout_cmu_hsi1_pcie" ,"gout_cmu_hsi2_bus" , "mout_cmu_hsi2_bus" ,"gout_cmu_hsi2_mmc_card" ,"mout_cmu_hsi2_mmc_card" , CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,"gout_cmu_hsi2_pcie" , "mout_cmu_hsi2_pcie" ,"gout_cmu_hsi2_ufs_embd" ,"mout_cmu_hsi2_ufs_embd" , CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,"gout_cmu_ipp_bus" , "mout_cmu_ipp_bus" ,"gout_cmu_itp_bus" , "mout_cmu_itp_bus" ,"gout_cmu_mcsc_itsc" , "mout_cmu_mcsc_itsc" ,"gout_cmu_mcsc_mcsc" , "mout_cmu_mcsc_mcsc" ,"gout_cmu_mfc_mfc" , "mout_cmu_mfc_mfc" ,"gout_cmu_mif_busp" , "mout_cmu_mif_busp" ,"gout_cmu_misc_bus" , "mout_cmu_misc_bus" ,"gout_cmu_misc_sss" , "mout_cmu_misc_sss" ,"gout_cmu_pdp_bus" , "mout_cmu_pdp_bus" ,"gout_cmu_pdp_vra" , "mout_cmu_pdp_vra" ,"gout_cmu_peric0_bus" ,"mout_cmu_peric0_bus" , CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,"gout_cmu_peric0_ip" , "mout_cmu_peric0_ip" ,"gout_cmu_peric1_bus" ,"mout_cmu_peric1_bus" , CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,"gout_cmu_peric1_ip" , "mout_cmu_peric1_ip" ,"gout_cmu_tnr_bus" , "mout_cmu_tnr_bus" ,"gout_cmu_top_cmuref" ,"mout_cmu_top_cmuref" , CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,"gout_cmu_tpu_bus" , "mout_cmu_tpu_bus" ,"gout_cmu_tpu_tpu" , "mout_cmu_tpu_tpu" ,"gout_cmu_tpu_tpuctl" ,"mout_cmu_tpu_tpuctl" , CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,"gout_cmu_tpu_uart" , "mout_cmu_tpu_uart" ,static const struct samsung_cmu_info top_cmu_info __initconst = {static void __init gs101_cmu_top_init(struct device_node *np)/* Register CMU_TOP early, as it's a dependency for other early domains */ "google,gs101-cmu-top" ,/* ---- CMU_APM ------------------------------------------------------------- */ /* Register Offset definitions for CMU_APM (0x17400000) */ #define APM_CMU_APM_CONTROLLER_OPTION 0x0800#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
Messung V0.5 C=97 H=99 G=97
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