// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2024 SpacemiT Technology Co. Ltd * Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org> #include <linux/array_size.h>#include <linux/auxiliary_bus.h>#include <linux/clk-provider.h>#include <linux/delay.h>#include <linux/idr.h>#include <linux/mfd/syscon.h>#include <linux/minmax.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/slab.h>#include <soc/spacemit/k1-syscon.h>#include "ccu_common.h" #include "ccu_pll.h" #include "ccu_mix.h" #include "ccu_ddn.h" #include <dt-bindings/clock/spacemit,k1-syscon.h>struct spacemit_ccu_data {const char *reset_name;struct clk_hw **hws;static DEFINE_IDA(auxiliary_ids);/* APBS clocks start, APBS region contains and only contains all PLL clocks */ /* * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for * peripherals. static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {_PLL1_LOCK,_PLL2_LOCK,_PLL3_LOCK,8, 1,), 11, 1);13, 1);), 23, 1);64, 1);), 10, 1);, 100, 1);/* APBS clocks end */ /* MPMU clocks start */ , 1););, 6, 1);16, 3);1);, 1);9), 24, 1);1);1);2, 1);3, 1);2);D);1), 50, 1););static const struct clk_parent_data apb_parents[] = {/* MPMU clocks end */ /* APBC clocks start */ static const struct clk_parent_data uart_clk_parents[] = {;static const struct clk_parent_data pwm_parents[] = {static const struct clk_parent_data ssp_parents[] = {static const struct clk_parent_data twsi_parents[] = {/* * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. * Combine functional and bus bits together as a gate to avoid sharing the * write-only register between different clock hardwares. | BIT(0), 0);static const struct clk_parent_data timer_parents[] = {;;(1), 0);static const struct clk_parent_data sspa_parents[] = {T(1), 0);static const struct clk_parent_data can_parents[] = {), 0);););););););););););););););););););););););););););/* Placeholder to workaround quirk of the register */ 0), 0);0), 0);0), 0);););T, BIT(0), 0);/* APBC clocks end */ /* APMU clocks start */ static const struct clk_parent_data pmua_aclk_parents[] = {0, 1, 0);static const struct clk_parent_data cci550_clk_parents[] = {(12), 0, 2,static const struct clk_parent_data cpu_c0_hi_clk_parents[] = {static const struct clk_parent_data cpu_c0_clk_parents[] = {), 0, 3,L, 6, 3,L, 9, 3,static const struct clk_parent_data cpu_c1_hi_clk_parents[] = {static const struct clk_parent_data cpu_c1_clk_parents[] = {), 0, 3,L, 6, 3,static const struct clk_parent_data jpg_parents[] = {, 2, 3,static const struct clk_parent_data ccic2phy_parents[] = {1, BIT(5), 0);static const struct clk_parent_data ccic3phy_parents[] = {, 1, BIT(30), 0);static const struct clk_parent_data csi_parents[] = {BIT(15),static const struct clk_parent_data camm_parents[] = {8, 2,8, 2,8, 2,static const struct clk_parent_data isp_cpp_parents[] = {6, 1,static const struct clk_parent_data isp_bus_parents[] = {3, BIT(23),static const struct clk_parent_data isp_parents[] = {8, 2,static const struct clk_parent_data dpumclk_parents[] = {,static const struct clk_parent_data dpuesc_parents[] = {, 0);static const struct clk_parent_data dpubit_parents[] = {3, BIT(31),static const struct clk_parent_data dpupx_parents[] = {static const struct clk_parent_data dpu_spi_parents[] = {, 8, 3,TRL, BIT(3), 0);RL, BIT(5), 0);BIT(6), 0);static const struct clk_parent_data v2d_parents[] = {), 12, 2,static const struct clk_parent_data ccic_4x_parents[] = {, 3,static const struct clk_parent_data ccic1phy_parents[] = {(5), 0);(3), 0);static const struct clk_parent_data sdh01_parents[] = {(11), 5, 3,(11), 5, 3,static const struct clk_parent_data sdh2_parents[] = {11), 5, 3,), 0);), 0);0);static const struct clk_parent_data qspi_parents[] = {12), 6, 3,(3), 0);;static const struct clk_parent_data aes_parents[] = {static const struct clk_parent_data vpu_parents[] = {), 10, 3,static const struct clk_parent_data gpu_parents[] = {), 18, 3,static const struct clk_parent_data emmc_parents[] = {IT(11),S_CTRL, 12,static const struct clk_parent_data audio_parents[] = {IT(15),static const struct clk_parent_data hdmi_parents[] = {(29), 5,_0, BIT(2), 0);0, BIT(1), 0);BIT(0), 0);_1, BIT(2), 0);1, BIT(1), 0);BIT(0), 0);_2, BIT(2), 0);2, BIT(1), 0);BIT(0), 0);IT(0), 0);(15), 0);IT(0), 0);(15), 0);BIT(3), 0);/* APMU clocks end */ static struct clk_hw *k1_ccu_pll_hws[] = {static const struct spacemit_ccu_data k1_ccu_pll_data = {/* The PLL CCU implements no resets */ static struct clk_hw *k1_ccu_mpmu_hws[] = {static const struct spacemit_ccu_data k1_ccu_mpmu_data = {"mpmu-reset" ,static struct clk_hw *k1_ccu_apbc_hws[] = {static const struct spacemit_ccu_data k1_ccu_apbc_data = {"apbc-reset" ,static struct clk_hw *k1_ccu_apmu_hws[] = {static const struct spacemit_ccu_data k1_ccu_apmu_data = {"apmu-reset" ,static const struct spacemit_ccu_data k1_ccu_rcpu_data = {"rcpu-reset" ,static const struct spacemit_ccu_data k1_ccu_rcpu2_data = {"rcpu2-reset" ,static const struct spacemit_ccu_data k1_ccu_apbc2_data = {"apbc2-reset" ,static int spacemit_ccu_register(struct device *dev,struct regmap *regmap,struct regmap *lock_regmap,const struct spacemit_ccu_data *data)struct clk_hw_onecell_data *clk_data;int i, ret;/* Nothing to do if the CCU does not implement any clocks */ if (!data->hws)return 0;if (!clk_data)return -ENOMEM;for (i = 0; i < data->num; i++) {struct clk_hw *hw = data->hws[i];struct ccu_common *common;const char *name;if (!hw) {continue ;if (ret) {"Cannot register clock %d - %s\n" ,return ret;if (ret)"failed to add clock hardware provider (%d)\n" , ret);return ret;static void spacemit_cadev_release(struct device *dev)struct auxiliary_device *adev = to_auxiliary_dev(dev);static void spacemit_adev_unregister(void *data)struct auxiliary_device *adev = data;static int spacemit_ccu_reset_register(struct device *dev,struct regmap *regmap,const char *reset_name)struct spacemit_ccu_adev *cadev;struct auxiliary_device *adev;int ret;/* Nothing to do if the CCU does not implement a reset controller */ if (!reset_name)return 0;sizeof (*cadev), GFP_KERNEL);if (!cadev)return -ENOMEM;if (ret < 0)goto err_free_cadev;if (ret)goto err_free_aux_id;if (ret) {return ret;return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);return ret;static int k1_ccu_probe(struct platform_device *pdev)struct regmap *base_regmap, *lock_regmap = NULL;const struct spacemit_ccu_data *data;struct device *dev = &pdev->dev;int ret;if (IS_ERR(base_regmap))return dev_err_probe(dev, PTR_ERR(base_regmap),"failed to get regmap\n" );/* * The lock status of PLLs locate in MPMU region, while PLLs themselves * are in APBS region. Reference to MPMU syscon is required to check PLL * status. if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll" )) {struct device_node *mpmu = of_parse_phandle(dev->of_node,"spacemit,mpmu" , 0);if (!mpmu)return dev_err_probe(dev, -ENODEV,"Cannot parse MPMU region\n" );if (IS_ERR(lock_regmap))return dev_err_probe(dev, PTR_ERR(lock_regmap),"failed to get lock regmap\n" );if (ret)return dev_err_probe(dev, ret, "failed to register clocks\n" );if (ret)return dev_err_probe(dev, ret, "failed to register resets\n" );return 0;static const struct of_device_id of_k1_ccu_match[] = {"spacemit,k1-pll" ,"spacemit,k1-syscon-mpmu" ,"spacemit,k1-syscon-apbc" ,"spacemit,k1-syscon-apmu" ,"spacemit,k1-syscon-rcpu" ,"spacemit,k1-syscon-rcpu2" ,"spacemit,k1-syscon-apbc2" ,static struct platform_driver k1_ccu_driver = {"spacemit,k1-ccu" ,"SpacemiT K1 CCU driver" );"Haylen Chu " );"GPL" );
Messung V0.5 C=97 H=96 G=96
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