/** * struct qce_device - crypto engine device structure * @queue: crypto request queue * @lock: the lock protects queue and req * @done_work: workqueue context * @req: current active request * @result: result of current transform * @base: virtual IO base * @dev: pointer to device structure * @core: core device clock * @iface: interface clock * @bus: bus clock * @dma: pointer to dma data * @burst_size: the crypto burst size * @pipe_pair_id: which pipe pair id the device using * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request
*/ struct qce_device { struct crypto_queue queue; struct mutex lock; struct work_struct done_work; struct crypto_async_request *req; int result; void __iomem *base; struct device *dev; struct clk *core, *iface, *bus; struct icc_path *mem_path; struct qce_dma_data dma; int burst_size; unsignedint pipe_pair_id; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret);
};
/** * struct qce_algo_ops - algorithm operations per crypto type * @type: should be CRYPTO_ALG_TYPE_XXX * @register_algs: invoked by core to register the algorithms * @unregister_algs: invoked by core to unregister the algorithms * @async_req_handle: invoked by core to handle enqueued request
*/ struct qce_algo_ops {
u32 type; int (*register_algs)(struct qce_device *qce); void (*unregister_algs)(struct qce_device *qce); int (*async_req_handle)(struct crypto_async_request *async_req);
};
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