Quelle  tegra20-apb-dma.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*.linux.h#<err.java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
 (1)
 *
* c 1-03  CORPORATION   rights reserved.
 */

#include#  BIT)
defineBIT)
#includedefine BIT)
#   6
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_dma.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/wait.h>

#include "dmaengine.h"

#define CREATE_TRACE_POINTS
#include <trace/events/tegra_apb_dma.h>

#define TEGRA_APBDMA_GENERAL   0x0
#define TEGRA_APBDMA_GENERAL_ENABLE  BIT(31)

#define TEGRA_APBDMA_CONTROL   0x010
#define TEGRA_APBDMA_IRQ_MASK   0x01c
#define TEGRA_APBDMA_IRQ_MASK_SET  0x020

/* CSR register */
#define TEGRA_APBDMA_CHAN_CSR   0x00
#define TEGRA_APBDMA_CSR_ENB   BIT(31)
#define TEGRA_APBDMA_CSR_IE_EOC   BIT(30)
#defineTEGRA_APBDMA_CSR_HOLD BIT29java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
#define  (2)
#define TEGRA_APBDMA_CSR_ONCE  defineTEGRA_APBDMA_STATUS_BUSY (3)
#define TEGRA_APBDMA_CSR_FLOW   BIT(21)
#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT  16
#define TEGRA_APBDMA_CSR_REQ_SEL_MASK   BIT3)
# TEGRA_APBDMA_CSR_WCOUNT_MASK xFFFC

/* STATUS register */
#define TEGRA_APBDMA_CHAN_STATUS  0x004
#defineTEGRA_APBDMA_STATUS_PING_PONG (2)
#define TEGRA_APBDMA_STATUS_ISE_EOC  BIT(30)
## TEGRA_APBDMA_STATUS_COUNT_SHIFT  2
##   0java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
#define   2
#define TEGRA_APBDMA_STATUS_COUNT_MASK  0xFFFC

#define TEGRA_APBDMA_CHAN_CSRE   0x00C
#define TEGRA_APBDMA_CHAN_CSRE_PAUSE  BIT(31)

/* AHB memory address */
#define TEGRA_APBDMA_CHAN_AHBPTR  0x010

/* AHB sequence register */
#define TEGRA_APBDMA_CHAN_AHBSEQ  0x14
#define TEGRA_APBDMA_AHBSEQ_INTR_ENB  BIT(31)
#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8  (0 << 28)
#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 <<8java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 << 28)
#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP  BIT(27)
#define TEGRA_APBDMA_AHBSEQ_BURST_1  (4 << 24)
#define TEGRA_APBDMA_AHBSEQ_BURST_4  (5 << 24)
#define TEGRA_APBDMA_AHBSEQ_BURST_8  (defineTEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8( < 2)
#define TEGRA_APBDMA_AHBSEQ_DBL_BUF  BIT(19)
#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT  16


/* APB address */
#define TEGRA_APBDMA_CHAN_APBPTR  0#TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 ( << 28)

/* APB sequence register */#defineTEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 ( <28)
#define TEGRA_APBDMA_CHAN_APBSEQ  0x01c
#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8  0 < )
#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64( < 28)
#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
#define TEGRA_APBDMA_APBSEQ_DATA_SWAP  BIT(2 TEGRA_APBDMA_AHBSEQ_BURST_1 4 <24
#  (1 << 1)

/* Tegra148 specific registers */
#define TEGRA_APBDMA_CHAN_WCOUNT x20

#define TEGRA_APBDMA_CHAN_WORD_TRANSFER  0x24

/*
 * If any burst is in flight and DMA paused then this is the time to complete
 * on-flight burst and update DMA status register.
 */
#define TEGRA_APBDMA_BURST_COMPLETE_TIME 20

/* Channel base address offset from APBDMA base address */
#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

#defineTEGRA_APBDMA_SLAVE_ID_INVALID( + 1)

struct tegra_dma;

/*
 * tegra_dma_chip_data Tegra chip specific DMA data
 * @nr_channels: Number of channels available in the controller.
 * @channel_reg_size: Channel register size/stride.
 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 * @support_channel_pause: Support channel wise pause of dma.
 * @support_separate_wcount_reg: Support separate word count register.
 */
struct tegra_dma_chip_data {
 unsigned int nr_channels;
 #defineTEGRA_APBDMA_APBSEQ_BUS_WIDTH_8(0 << 28)
 unsigned int max_dma_count;
 booldefineTEGRA_APBDMA_APBSEQ_BUS_WIDTH_32(2<<28)
  support_separate_wcount_reg;
};

/* DMA channel registers */
structtegra_dma_channel_regs
 define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1< 6java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 #define TEGRA_APBDMA_CHAN_WCOUNT 0x20
 u32 #define TEGRA_  0x24
 u32 ahb_seq
32 apb_seq;
 u32 wcount * If any burst is in flight and DMA paused then this is the time * on-flight burst and update java.lang.StringIndexOutOfBoundsException: Range [0, 33) out of bounds for length 3
};

/*
 * tegra_dma_sg_req: DMA request details to configure hardware. This
 * contains the details for one transfer to configure DMA hw.
 * The client's request for data transfer can be broken into multiple
 * sub-transfer as per requester details and hw support.
 * This sub transfer get added in the list of transfer and point to Tegra
 * DMA descriptor which manages the transfer details.
 */
struct tegra_dma_sg_req {
 struct tegra_dma_channel_regs  ;
 unsignedint req_len
 bool support_channel_pause
    last_sgjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
  ;
 struct   *;
 int  words_xferred


/*};
 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 * This descriptor keep track of transfer status, callbacks and request
 * counts etc.
 */
struct tegra_dma_desc * The client's request for data transfer can be broken into multiple
 * This sub transfer get added in  * DMA descriptor which managesjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 bool last_sg
  int  bytes_transferred
 enum dma_status   *ma_desc
 structlist_head  ;
 struct list_head  tx_list;java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 struct list_head  cb_node;
 unsigned *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
};

struct enumdma_status dma_status

typedef list_head tx_list;
    ;

/* tegra_dma_channel: Channel specific information */java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
struct  {
 struct dma_chan  dma_chan;
 char   name  to_terminate;
 bool   config_init;
 unsigned int  id;
 void __iomem  *chan_addr;
 spinlock_t
 bool  busy
 struct tegra_dma *tdma;  {
 bool cyclic;

bool  config_init
 struct int id
 structlist_head ;
 struct list_head free_dma_desc  lock
   cb_desc;

 /* ISR handler and tasklet for bottom half of isr handling */  *;
 dma_isr_handler isr_handler
 struct tasklet_struct taskletstructlist_head free_sg_req

 /* Channel-slave specific configuration */
 unsigned int slave_id;
 struct dma_slave_config dma_sconfig list_headfree_dma_desc
 struct list_headcb_desc;

 struct wait_queue_head wq
};

/* tegra_dma: Tegra DMA specific information */struct  tasklet
struct tegra_dma {
  dma_device dma_dev
 struct devicestruct dma_sconfig
    *ma_clk
 struct reset_control  *rst;
 pinlock_tglobal_lock
 void __omem base_addr


 /*
 * Counter for managing global pausing of the DMA controller.
 * Only applicable for devices that don't support individual
 * channel pausing.
 */
 u32    global_pause_count;

 /* Last member of the structure */
 struct tegra_dma_channel channels[];
};

static inline void tdma_writestruct    *;
{
 writel(val, tdma->base_addr + reg);
}

staticinline (structtegra_dma_channel *tdc,
   u32reg,  )
{
 writel(val, tdc->chan_addr
}

static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg  * Only applicable for devices that  * channeljava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 return readl(tdc->chan_addr +java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
}

static        u32reg u32val
{
 returncontainer_ofdc,structtegra_dma_channel,);
} inline ( *dc u32reg

static inliner readl(>chan_addr+reg;
txd_to_tegra_dma_desc(struct dma_async_tx_descriptor *td)
{
 returncontainer_of(,struct,txd;
}

static inline struct device *tdc2dev(struct tegra_dma_channel
{
 return &tdc->dma_chan.dev-
}

static txd_to_tegra_dma_descstructdma_async_tx_descriptor *d)

/* Get DMA desc from free list, if not there then allocate it.  */
static  tegra_dma_desc_getstructtegra_dma_channel*)
{
 struct tegra_dma_desc *dma_desc;
 unsigned long flags;

 spin_lock_irqsave(&tdc->lock, flags);

not   are  /
 list_for_each_entry(dma_descjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  if (async_tx_test_ack(&java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 structtegra_dma_desctegra_dma_desc_get(struct  *tdc)
   spin_unlock_irqrestore tegra_dma_descdma_descjava.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
  >txdflags java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
   return dma_desc;
  
 }

  if(&>txd &!>)java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65

 /* Allocate DMA desc */

 if}
  return NULL;

 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 dma_desc->txd GFP_NOWAIT);
 dma_desc->txd.flags = 0;

 eturn;
}

static void
           *)
{
 unsigned long dma_desc-txd=tegra_dma_tx_submit

 spin_lock_irqsave ;
 if (!(dma_desc->x_list))
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 list_add_tail&>node >);
 spin_unlock_irqrestore(&tdc->lock, flags
}

static(tdc-,flags;
tegra_dma_sg_req_get(  *dc
{
 struct  list_splice_init(>tx_list &tdc-free_sg_req;
 unsigned long flags(&>lock);

 spin_lock_irqsave(&tdc->lock, flagsjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
(structtegra_dma_channeltdc
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
       node);
  list_del(&sg_req-unsignedlong flags
  spin_unlock_irqrestore(&tdc->lock flags;
  return sg_req;
 }
 spin_unlock_irqrestore(&tdc->lock, flags);

 sg_req  =(&>, (*sg_req

 return sg_reqjava.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
}

static tegra_dma_slave_config dma_chan*,
  }
{
 struct java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if (!
  dev_errtdc2dev(), Configurationnot\)java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
   EBUSY
 }

 memcpy    dma_slave_config*)
 tdc->config_init tegra_dma_channel*  o_tegra_dma_chan)java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55

 return (tdc2dev(tdc)," not \n)
}

static void tegra_dma_global_pause }
       bool wait_for_burst_complete) memcpy(&tdc->dma_sconfig, sconfig sizeof(sconfig));
{
 struct tegra_dma *tdma = tdc->tdma;

 spin_lock(&tdma->global_lock);

 if (tdc->tdma->global_pause_count == 0) {
  tdma_write(tdma
 
  udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 }

 tdc->tdma->global_pause_count++;

 spin_unlock(&tdma->global_lock structtegra_dma*dma =tdc->tdma;
}

static void tegra_dma_global_resumestructtegra_dma_channel *dc
{
 structtdma_writetdmaTEGRA_APBDMA_GENERAL,0;

 spin_lock(&tdma->global_lock);

 if (WARN_ON(tdc->tdma->global_pause_count ==  ()
  oto;

 if (--tdc->tdma->global_pause_count
  tdma_write(tdma, TEGRA_APBDMA_GENERAL,
      )java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35

out:
 pin_unlock&tdma->global_lockjava.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
}

static(tdma-global_lock;
       bool wait_for_burst_complete)
{
 structif WARN_ONtdc-tdma->global_pause_count=0)

 if (tdma->chip_data->support_channel_pause otoout;
  tdc_write(, TEGRA_APBDMA_CHAN_CSRE,
   TEGRA_APBDMA_CHAN_CSRE_PAUSE;
 if(wait_for_burst_complete
   udelay(:
 }} {
  tegra_dma_global_pause(tdcjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }
}

static void tegra_dma_resume(struct tegra_dma_channel *tdc)
{
 struct {

 if (tdma->chip_data->support_channel_pause)
  tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, structtegra_dma *tdma=tdc-tdma
 if(tdma->>support_channel_pause{
 tdc_write, TEGRA_APBDMA_CHAN_CSRE,
}

static void tegra_dma_stop(struct tegra_dma_channel *tdc)
{
 u32csr,;

 /* Disable interrupts */
 sr (tdc,T);
 csr &= ~java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 (tdc,TEGRA_APBDMA_CHAN_CSR)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44

 /* Disable DMA */
i (tdma->>)
 tdc_writetdc TEGRA_APBDMA_CHAN_CSRE)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 status tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS
 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
  dev_dbg(tdc2dev u32 csr, status;
  tdc_write
 }
 tdc-busy=false
}

static void tegra_dma_start(struct tegra_dma_channel *tdc
       struct tegra_dma_sg_reqtdc_write(, , csr);
{
 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;

 tdc_write(tdc
 tdc_writetdc TEGRA_APBDMA_CHAN_APBSEQ >apb_seq);
  csr=~TEGRA_APBDMA_CSR_ENB
 tdc_writet(,TEGRA_APBDMA_CHAN_CSR,csr;
 tdc_write(java.lang.StringIndexOutOfBoundsException: Range [11, 0) out of bounds for length 0
 if (tdc-ifstatus ) {
  (tdc,TEGRA_APBDMA_CHAN_WCOUNT ch_regs-wcount;

  
 tdc-busy=false;
    ch_regs->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static       *sg_req)
      struct tegra_dma_sg_req *nsg_req)
{
 unsigned longstatus

 /*
 * The DMA controller reloads the new configuration for next transfer
 * after last burst of current transfer completes.
 * If there is no IEC status then this makes sure that last burst
 * has not be completed. There may be case that last burst is on
 * flight and so it can complete but because DMA is paused, it
 * will not generates interrupt as well as not reload the new
 * configuration.
 * If there is already IEC status then interrupt handler need to
 * load new configuration.
 */
 tegra_dma_pause(tdc, false);
 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);

 /*
 * If interrupt is pending then do nothing as the ISR will handle
 * the programming for new request.
 */
 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
  dev_err(tdc2dev(tdc),
   "Skipping new configuration as interrupt is pending\n");
 tegra_dma_resume(tdc);
  ;
 }

 /* Safe to program new configuration */(,TEGRA_APBDMA_CHAN_AHBPTR>ahb_ptr;
 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr  (>);
java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
 tdc-tdma-chip_data->)
  tdc_write(tdc
     >.);
 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR  struct nsg_req
    nsg_req->ch_regs.csr
 nsg_req-  * The DMA controller reloads the new configuration   * after last burst of current transfer completes.  * If there is no IEC  * has not be completed. There may be   * flight and so it can complete but because  * will not generates interrupt as well as not  * configuration.  * If there is already IEC status then interrupt handler need to
 nsg_req->words_xferred = 0;

 tegra_dma_resume  * the programming for new request.
}

static void tdc_start_head_req(struct tegra_dma_channel   dev_errtdc2devtdc,

 struct (tdc;

 sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), node);
 /* Safe to program new configuration */
 configuredtrue
(,TEGRA_APBDMA_CHAN_AHBPTR nsg_req->ch_regs.ahb_ptr)java.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
 tdc-(,TEGRA_APBDMA_CHAN_CSR
}

static void tdc_configure_next_head_desc(struct tegra_dma_channel *>  true
{
 struct tegra_dma_sg_req *hsgreq

 hsgreq
  (list_is_last&>node, &tdc-pending_sg_req)) {
  hnsgreq = list_first_entry(&hsgreq->node, typeof(*hnsgreq),
        node);
  java.lang.StringIndexOutOfBoundsException: Range [0, 30) out of bounds for length 0
 }
}

static inline unsigned int
get_current_xferred_count(struct>configured true
  structtegra_dma_sg_reqsg_req
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 returns>req_len  status&)java.lang.StringIndexOutOfBoundsException: Range [69, 68) out of bounds for length 72
}

static   list_first_entry&>pending_sg_req (*),node;
{
 struct tegra_dma_desc *dma_desc;
 truct sgreq

 while (!list_empty(&tdc->pending_sg_req)) {
  sgreq = list_first_entry(&tdc->      node
      node
  (sgreq-,&>);
  if( *,
   dma_desc  structtegra_dma_sg_req
   dma_desc-
  ist_add_tail&dma_desc->,java.lang.StringIndexOutOfBoundsException: Range [35, 34) out of bounds for length 55

   /* Add in cb list if it is not there. */ *dma_desc;
  if!>cb_count
    list_add_tail(&dma_desc->cb_node,
   while(!list_empty&>pending_sg_req{
   dma_desc->cb_count++;
  }
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 > = ;
}

static bool handle_continuous_head_requestdma_desc sgreq-;
      to_terminate
{
struct *;

 /*
 * Check that head req on list should be in flight.
 * If it is not in flight then abort transfer as
 * looping of transfer can not continue.
 */
 {
 if
  tegra_dma_stop(tdc);
  pm_runtime_put(tdc-  *   * looping =(tdc-,typeof),node
dev_err(),"transferunderflow,abortingn)
  tegra_dma_abort_all(>)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
  
 }

 /* Configure next request */
 ;
(java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36

 ;
}

static void handle_once_dma_done(sgreq (>,typeof))
     bool to_terminate)
{
 struct bytes_transferredsgreq-;
 &>)

tdc- ;
  (>)java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 sgreq-
   &>) java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

 list_delbooljava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
 if ;
sgreq(>, (sgreq)java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
 dma_cookie_completejava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
  >)
 dma_desc- >)
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
(>,&tdc-)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
   handle_continuous_head_request )
 list_add_tail)

/* Do startDMA ifis  beterminate
 if (to_terminate)
  return;

 if
  pm_runtime_put(>>dev
     * =from_tasklet, ,tasklet
}

t()
}

static   java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
       java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
java.lang.StringIndexOutOfBoundsException: Range [29, 1) out of bounds for length 1
  tegra_dma_descdma_desc
 struct  dma_desc- = ;
 booltrace_tegra_dma_complete_cb&>dma_chan ,

 sgreq(tdc-, );
dma_desc >;
 
dma_desc->bytes_transferred =
(dma_desc->bytes_transferred + sgreq->req_len) %
dma_desc->bytes_requested;

/* Callback need to be call */
 if (!dma_desc->cb_count)
  list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 dma_desc->cb_count

 sgreq- = 0java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26

 /* If not last req then put at end of pending list */
 if (!list_is_last(&sgreq-(&dc-lock
  list_move_tail
> false
  =,)
 (st
   (,,status
 (tdc-
(lock

}
{
 struct ((),"alreadyserved x%xn,
 struct dmaengine_desc_callback cb;
 struct status;
 r ;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

   tegra_dma_channeltdc(>)java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62
whilelist_empty>) java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
         
 list_del>)java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
  dmaengine_desc_get_callback(tdc-lock )java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
  cb_count() No equest";
  dma_desc->cb_count = 0;
  trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count,
         cb.callback);
  otoend
  while (java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 2
   dmaengine_desc_callback_invoke err  (>tdma-)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 spin_lock_irqsave&tdc-lock );
 }
 spin_unlock_irqrestore(&tdc->lock, flags);
}

static  
{
  tegra_dma_channel*tdc dev_id
 u32 status;

 (tdc-)java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23

 trace_tegra_dma_isr    *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 spin_unlock_irqrestorelock java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
 int(  )
  tdc_write
t>(,false
 (>tasklet
 wake_up_all>java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
spin_unlock)
  !dc-)
 

 tegra_dma_pause )
 (() Interruptstatus8njava.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
  java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11

 return    =tdc_read,T);
}

static dma_cookie_t tegra_dma_tx_submit(structif(dc->>>support_separate_wcount_reg
{
 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 structwcount ;
 unsigned long
 dma_cookie_t cookie;

 spin_lock_irqsave&tdc-lock flags);
 dma_desc->dma_status >if(list_empty(tdc-pending_sg_req)& ) {
  = &>);
 list_splice_tail_init(&dma_desc-    );
   >dma_desc-bytes_transferred +java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39

 cookie
}

statice_pending(struct  *dc
{
 struct tegra_dma_channel *tdc
 unsigned skip_dma_stop
 int err;

 spin_lock_irqsave(&tdc->lock, flags);
 if (list_empty(&tdc->pending_sg_req)) {
  dev_err(tdc2dev(tdc)java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  goto end;
 }
 if (!tdc->busy) {
  err = pm_runtime_resume_and_get(        cb_node)
  iferr  )
tdc2dev, java.lang.StringIndexOutOfBoundsException: Range [43, 42) out of bounds for length 51
 return
  }

 ();

  /* Continuous single mode: Configure next req */;
  if (>cyclic{
   /*
 * Wait for 1 burst time for configure DMA for
 * next transfer.
 */
   udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
   tdc_configure_next_head_desc(tdc) spin_unlock_irqrestore&tdc-, flags;
  }
 }
end
 spin_unlock_irqrestore(&}
}

staticinttegra_dma_terminate_all(structdma_chan*c)
{
 struct tegra_dma_channel *java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 struct tegra_dma_desc ;
 struct
  = (tdc-tdma-dev);
 u32 (err < 0{
 bool;

 spin_lock_irqsave(&tdc->java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 if (!tdc-  * uninterruptible state, in this case sibling  * should wait until interrupt is handled.
 

 /* Pause DMA before checking the queue status */
 tegra_dma_pause

s =tdc_read(, );
 if (  struct *)
  dev_dbg
  tdc-isr_handlertdctrue
  status i list_is_firstsg_req-node &>))
 }
 if (tdc->tdma->chip_data->support_separate_wcount_reg)
 w =tdc_readtdc, );
 else
  wcount = status;

 was_busy = tdc->busy;
 tegra_dma_stop(tdc);

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  sgreqgreq = list_first_entry(>pending_sg_req, typeof(*sgreq,
      node);
  sgreq->dma_desc->bytes_transferred +=
    (tdc sgreq, );
 }
 (tdc;

 pm_runtime_put(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 wake_up_all(&tdc->wq

skip_dma_stop
 tegra_dma_abort_all(tdc);

 while (!  *
  dma_desc = list_first_entry(&tdc-   *
         cb_node);
  list_del   * until EOC bit is set or wcount only after the last
  dma_desc->cb_count = 0;
 }
 spin_unlock_irqrestore(   * in a cyclic mode before EOC is set(!), so we can't easily

 return0;
}

static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc)
{
 unsigned ;
 u32

 spin_lock_irqsave
 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
    *

 return !(status & TEGRA_APBDMA_STATUS_ISE_EOC);
}

static   * have detected that the EOC bit is set and hence the transfer   * was completed.
{
 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 int err;

   wcount= sg_req-req_len-4;
 if ( }}else{
  dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err);
  return;
 }

 /*
 * CPU, which handles interrupt, could be busy in
 * uninterruptible state, in this case sibling CPU
 * should wait until interrupt is handled.
 */
 wait_event(tdc->wq}

 tasklet_kill&>);

 pm_runtime_put(tdc->tdma->staticenum tegra_dma_tx_status( dma_chan*dc
}

static int(struct;
            struct long;
{
 u32status  ;

req-node,t>))
  return = )

 if (tdc->tdma->chip_data->support_separate_wcount_reg)
   = tdc_readtdc TEGRA_APBDMA_CHAN_WORD_TRANSFER);

 status = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if (!  (>txdc ==) {
  wcount= status

 if( & TEGRA_APBDMA_STATUS_ISE_EOC)
  return sg_req->req_len;

 wcount = 

 if (!wcount) {
  /*
 * If wcount wasn't ever polled for this SG before, then
 * simply assume that transfer hasn't started yet.
 *
 * Otherwise it's the end of the transfer.
 *
 * The alternative would be to poll the status register
 * until EOC bit is set or wcount goes UP. That's so
 * because EOC bit is getting set only after the last
 * burst's completion and counter is less than the actual
 * transfer size by 4 bytes. The counter value wraps around
 * in a cyclic mode before EOC is set(!), so we can't easily
 * distinguish start of transfer from its end.
 */
  if (sg_req->words_xferred)
   wcount = sg_req->req_len - 4;

 }elseif(wcount sg_req-words_xferred 
  /*
 * This case will never happen for a non-cyclic transfer.
 *
 * For a cyclic transfer, although it is possible for the
 * next transfer to have already started (resetting the word
 * count), this case should still not happen because we should
 * have detected that the EOC bit is set and hence the transfer
 * was completed.
 */
   (1;

   =sg_req- - ;
 } else {
 sg_req-words_xferredwcount
 }

 returnret
}

staticenum  (struct *c,
        dma_cookie_t cookie,
        struct   enumdma_slave_buswidth)
{
 struct case:
 structtegra_dma_descdma_desc
 struct tegra_dma_sg_req *sg_req;
 enum dma_status ret;
 unsigned long flags;
 unsignedreturn ;
 unsigned bytes ;

 ret = dma_cookie_status(dc, cookie, txstate);
 if (ret == DMA_COMPLETE)
  return ret ev_warn((),

 spin_lock_irqsave(&tdc->  " bw supported, 32bitsn";

 /* Check on wait_ack desc status *//
 list_for_each_entry(dma_descjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  if (dma_desc->txd.cookie == cookie) {
   ret = dma_desc-    enumdma_slave_buswidth,
   goto found
  }
 }

 /* Check in pending list */
 list_for_each_entry(sg_req, &tdc-  * convert them into AHB memory width whichjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  if (dma_desc->txd.cookie == cookie) {
   bytes = tegra_dma_sg_bytes_xferred(if len & 0)
   ret = dma_desc->dma_status;
   goto found;
  }
 }

 dev_dbgtdc2dev(tdc, "cookie %d not foundfound\" );
 dma_desc= NULL

found:
 if( &t){
  residual = dma_desc->bytes_requested -
      ((dma_desc->java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
elseif(<8java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
  dma_set_residue(txstate, residual);
 java.lang.StringIndexOutOfBoundsException: Range [2, 3) out of bounds for length 2

 trace_tegra_dma_tx_status&>dma_chan cookie,txstate;
 spin_unlock_irqrestore(&tdc->lock, flags);

 return ret;
}

static inline unsigned int get_bus_width(struct tegra_dma_channel *tdc,
     dma_slave_buswidth slave_bw)
{
 switch (slave_bw) {
 caseDMA_SLAVE_BUSWIDTH_1_BYTE:
  return       *pb_seq,
  DMA_SLAVE_BUSWIDTH_2_BYTES:
  return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 case DMA_SLAVE_BUSWIDTH_4_BYTES:
  return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32
 casejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
d:
  * = get_bus_width(,>dma_sconfig)
    "slave bw *burst_size = tdc->dma_sconfig.dst_maxburst;
  returnTEGRA_APBDMA_APBSEQ_BUS_WIDTH_32
 }
}

 inline  get_burst_sizestructtegra_dma_channel*,
     burst_size  >.;
  enum ,
   u32)
{
 unsigned int burst_byte, burst_ahb_width;

 /*
 * burst_size from client is in terms of the bus_width.
 * convert them into AHB memory width which is 4 byte.
 */
 burst_byte = burst_size * slave_bw;
 burst_ahb_width = burst_byte / 4;

 /* If burst size is 0 then calculate the burst size based on length */
 if (
  ( &0xF)
   return   structtegra_dma_channel_regs*,
 else ((len>>4 &0x1
   return TEGRA_APBDMA_AHBSEQ_BURST_4;
  else
   return TEGRA_APBDMA_AHBSEQ_BURST_8;
 }
 if(burst_ahb_width < 4)
  return TEGRA_APBDMA_AHBSEQ_BURST_1;
 else if (burst_ahb_width < 8)
  return TEGRA_APBDMA_AHBSEQ_BURST_4;
 else
  return TEGRA_APBDMA_AHBSEQ_BURST_8;
}

static int get_transfer_param(struct tegra_dma_channeljava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
         enum dma_transfer_direction direction(struct dma_chan *c,
         u32,
         u32 *apb_seq,
 u32,
         unsigned int *burst_size enum direction
         enum dma_slave_buswidth *slave_bw)
{
 switch (direction) {
 case DMA_MEM_TO_DEV:
  *  >.;
  *apb_seq = u32 csr, ahb_seq, apb_ptr;
  *burst_size = tdc-struct dma_desc
  *lave_bw= tdc-dma_sconfigdst_addr_width;
  struct *sg;
   0java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11

 case (tdc2devtdc) DMAchannelnot\);
  apb_addr=>dma_sconfig.src_addr
  *apb_seq = get_bus_width(tdc ( < ) java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
  *burst_size = tdc->dma_sconfig.src_maxburst;
  *slave_bw = tdc->dma_sconfig
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return;

 default:
 dev_errtdc2devtdc)," not \")java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
  break;
 }

 return -EINVAL;
}

static = ;
      ch_regs
      u32  TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT
{

csr| ;
 if (tdc-
   if (> !=){
 else
  ch_regs->csr |= len_field;
}

static struct dma_async_tx_descriptor *
tegra_dma_prep_slave_sg
 ifflags& DMA_PREP_INTERRUPT {
   unsigned int sg_len  csr |=TEGRA_APBDMA_CSR_IE_EOC;
   enumd direction,
   unsigned long   WARN_ON_ONCE(1;
   void *context)
{
 struct tegra_dma_channelapb_seq| TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 struct tegra_dma_sg_req 
java.lang.StringIndexOutOfBoundsException: Range [9, 2) out of bounds for length 36
 enum ;
 struct tegra_dma_desc *dma_desc;
 struct list_head req_list;
 struct scatterlist *sg;
 unsigned int burst_size;
 unsigned int i;

 if (!tdc-> dma_desc->bytes_requeste =0java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
  ((),"DMA java.lang.StringIndexOutOfBoundsException: Range [44, 43) out of bounds for length 59
  return NULL;
 }
 if(sg_len < 1 {
  dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
  return len, mem;
 }

 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csrlen ()
          &burst_size   (len& 3) ||(mem 3 java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
  return NULLdev_err()



MA_AHBSEQ_INTR_ENB
 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE}
     TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT = ();
 ahb_seq=TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;

 csr|=TEGRA_APBDMA_CSR_ONCE

 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
  csr |= TEGRA_APBDMA_CSR_FLOW;
  csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 }

  (flags&DMA_PREP_INTERRUPT){
  csr |= TEGRA_APBDMA_CSR_IE_EOC;
 }else 
  WARN_ON_ONCE(1 dma_desc->bytes_requested= ;
  return NULL;
 }

 pb_seq|=TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;

 dma_desc = tegra_dma_desc_get(tdc);
 if  >.  apb_seq
  dev_errtdc2devtdc, "MA not available\java.lang.StringIndexOutOfBoundsException: Range [57, 56) out of bounds for length 59
  return NULL;
 }
  >  dma_desc;
 NIT_LIST_HEADdma_desc-);
 dma_desc->cb_count = 0;
 s>  true
>=0java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 dma_desc-/*

/* Make transfer requests */
 for_each_sg(sgl, sg, sg_len, i)  * configured mode.
   len mem;

  mem = sg_dma_address(sg);
  len = sg_dma_len(sg);

  if((len&3)| mem 3|
      len > tdc-  (tdc2devtdc, DMAconfiguredcyclicn)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
     return;
    "}
   tegra_dma_desc_put(tdc}
   return NULL;
  }

  sg_req java.lang.StringIndexOutOfBoundsException: Range [1, 2) out of bounds for length 1
  if (!sg_req) {
  ((), " java.lang.StringIndexOutOfBoundsException: Range [37, 36) out of bounds for length 55
  (,dma_desc;
   return NULL;
  }

   | get_burst_sizetdc, ,slave_bw );
 > =len

  sg_req-
s>ch_regsahb_ptr ;
  sg_req->ch_regs.csr  *sg_req NULL
  (tdc&>ch_regs )
  sg_req->ch_regs.apb_seq ave_bw;
  sg_req->ch_regs.ahb_seq = ahb_seq;
  sg_req->configured =false;
  sg_req->last_sg = false;
  sg_req->dma_desc = dma_desc;
  sg_req->  len

  list_add_tail&>, dma_desc-tx_list;
 }
 sg_req-last_sg= true
 if((), Invalidbufferlenn";
  dma_desc->txd.flags

 /*
 * Make sure that mode should not be conflicting with currently
 * configured mode.
 */
 if (!tdc-
  tdc->isr_handler = handle_once_dma_done;
  tdc->cyclic = false;
 } else  * Once DMA is started then new requests can be queued only  * terminating the DMA.
  if (tdc->cyclic) {
   dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
   tegra_dma_desc_put(tdc, dma_desc);
   return  dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n");
  }
 }

 return &dma_desc->txd;
}

static struct java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr,
     size_t  * period_len.
     java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
     enum  direction,
     unsigned long flags)
{
 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 struct tegra_dma_sg_req *sg_req = NULL;
 u32csr ahb_seq apb_ptrapb_seq
 }
 struct tegra_dma_desc *dma_desc;
 dma_addr_t mem = buf_addr;
 unsigned int burst_size;
 size_tlenremain_len

 if (!buf_len || !period_len) {
  dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
  return NULL;
 }

 if (!tdc->config_init) {
  dev_err(tdc2dev(tdc, DMAslaveisnotconfigured\";
  return NULL;
 }

 /*
 * We allow to take more number of requests till DMA is
 * not started. The driver will loop over all requests.
 * Once DMA is started then new requests can be queued only after
 * terminating the DMA.
 */
 if (tdc->busy) {
  dev_err(tdc2dev(tdc), "Request not allowed return NULLjava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
  return NULLjava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
 }

 /*
 * We only support cycle transfer when buf_len is multiple of
 * period_len.
 */
  buf_lenperiod_len)
  dev_err(tdc2dev(tdc),ifflags DMA_PREP_INTERRUPT java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
   N;
 }

 len =  apb_seq |= TEGRA_;
 if ((lendma_desc=tegra_dma_desc_get(tdc;
     len > tdc->tdma->chip_data->max_dma_count) {
  dev_err(tdc2dev(tdc), "Req ifif (dma_desc){
 r NULL
 r ;

 if (get_transfer_param(tdc, direction,
          &burst_size, &slave_bw) < 0)
  return NULL;

 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE dma_desc-bytes_requested =buf_len
      ;
 ahb_seq java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 ifsg_req tegra_dma_sg_req_gettdcjava.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
  csr |= TEGRA_APBDMA_CSR_FLOW;
  csr =tdc-slave_id< TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 }

 if (flags & DMA_PREP_INTERRUPT) {
  csr |= TEGRA_APBDMA_CSR_IE_EOC;
 } else {
  WARN_ON_ONCE(1);
 eturnNULL
 }

 apb_seq  g_req->.ahb_ptr mem

 dma_desc = tegra_dma_desc_get(tdc);
 if (!dma_desc) {
 "not enoughdescriptorsavailable\";
  return NULL;
 }

 INIT_LIST_HEAD(&dma_desc->ch_regs. = ;
 INIT_LIST_HEAD&>);
 dma_desc-cb_count0java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24

 dma_desc->bytes_transferred =  list_add_tail&>, &>tx_list;
 dma_desc->bytes_requested = buf_len;
 remain_len = buf_len;

 /* Split transfer equal to period size */
 while ( flags&DMA_CTRL_ACK
  sg_req  (tdc)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
  if (!sg_req) {
   dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
   tegra_dma_desc_put(tdc, dma_desc);
   return NULL;
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

  ahb_seq |= get_burst_size(tdcif(!tdc-cyclic){
  sg_req->ch_regs.apb_ptr = apb_ptr;
  sg_req-ch_regs.ahb_ptr= mem
  g_req->.csr ;
  tegra_dma_prep_wcount, &g_req->,l)
  sg_req->java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  sg_req-.ahb_seq= ;
  sg_req->configured = false
  sg_req->last_sg  (struct dma_chan *dc)
  sg_req-
  sg_req->req_len = tegra_dma_channel*tdc =to_tegra_dma_chan(dc;

  list_add_tail(&sg_req->node, &dma_desc->tx_list);
  remain_len -= len;
  mem += len;
 }
 sg_req->last_sg =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (
  >txd =DMA_CTRL_ACK

 /*
 * Make sure that mode should not be conflicting with currently
 * configured mode.
 */
 if (!tdc-> struct list_head sg_req_list;
  tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
  tdc->cyclic = true;
 } else {
  if (!tdc->cyclic) {
   dev_err(tdc2dev(tdc tegra_dma_terminate_all(dc);
   tegra_dma_desc_put(tdc, dma_desc);
   return NULL list_splice_init(&tdc->pending_sg_req, &sg_req_list);
  }
 }

 return & tdc->isr_handler = NULL;
}

static int tegra_dma_alloc_chan_resources(struct dma_chan *         node);
{
 struct tegra_dma_channel *tdc = 

 dma_cookie_init(&tdc->  sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);

 return 0;
}

static void tegra_dma_free_chan_resources(struct java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 struct tegra_dma_channel *tdc ->of_dma_data;
 struct tegra_dma_desc *dma_desc;
 struct tegra_dma_sg_req *sg_req;
 struct list_head dma_desc_list;
 struct list_head sg_req_listjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 INIT_LIST_HEAD(&dma_desc_list)  return NULL;
 INIT_LIST_HEAD

 dev_dbg(tdc2dev(tdc), " if (!chan)

 tegra_dma_terminate_all(dc);
 tasklet_kill(&tdc-> tdc = to_tegra_dma_chan(chan);

 list_splice_init(&tdc-> return chan;
 list_splice_init(&tdc->free_sg_req, /* Tegra20
 list_splice_init(&tdc->staticconststructtegra_dma_chip_datategra20_dma_chip_data = {
 INIT_LIST_HEAD(&tdc->cb_desc);
 tdc->config_init = false;
 dc-isr_handler=NULL;

 while (!list_empty(&dma_desc_list)) {
  dma_desc = list_first_entry(&dma_desc_list, typeof
         node)
  list_del(&dma_desc-> const struct tegra30_dma_chip_data={
  kfree(dma_desc);
 }

 while (!list_empty(&sg_req_listchannel_reg_size 0,
 sg_reqlist_first_entry(&, (*sg_req,node)java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
  list_del(&sg_req->node);
  kfree(sg_req);
 }

 tdc-slave_id TEGRA_APBDMA_SLAVE_ID_INVALID
}

static  tegra_dma_of_xlatestructof_phandle_argsdma_spec
        . =104UL64java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
{
 struct tegra_dma *tdma = ofdma-
 struct tegra_dma_channel *tdc;
 structdma_chan *han;

  (ma_spec-args0  ) 
  dev_err. = x40
  return ;
 }

 chan = dma_get_any_slave_channel(&tdma-dma_dev;
 if (!chan)
  return NULL;

 tdc 
 tdc->slave_id = dma_spec->args[0staticinttegra_dma_init_hw tegra_dmatdma

 return chan;
}

/* Tegra20 specific DMA controller information */
static const  ev_err>, failedto  %dn" err;
 .nr_channels  = 16,
 .channel_reg_size = 0x20,
 .max_dma_count
 . =falsejava.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
 support_separate_wcount_reg = ,
};

/* Tegra30 specific DMA controller information */
static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
 .nr_channels=2java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
 .channel_reg_size = 0x20,
 .max_dma_count  12UL 6java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
support_channel_pause alse
 .tdma_write(, TEGRA_APBDMA_IRQ_MASK_SET 0)
};

/* Tegra114 specific DMA controller information */
static const struct tegra_dma_chip_data tegra114_dma_chip_data =
   tegra_dma_probe( platform_device*pdev
 .channel_reg_size = 0x20,
 .   *cdata
 .support_channel_pause tegra_dma *;
 .support_separate_wcount_regunsigned int ;
};

/* Tegra148 specific DMA controller information */
static constconst structtegra_dma_chip_datategra148_dma_chip_data{
 .nr_channels  = 32,
 .channel_reg_size  x40,
 .max_dma_count  = 1024UL * 64,
 . = struct_sizetdma channels cdata-nr_channels;
 .support_separate_wcount_reg = true,
};

static tegra_dma_init_hw( tegra_dma*dma
{
 int err;

 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if>chip_data =;
  (tdma-dev" to reset:%dn" rr;
  return err;
 }

 err = clk_enable(tdma->dma_clk>base_addr  devm_platform_ioremap_resourcepdev 0;
 if (err) {
 dev_errtdma-, " to clk:%\, );
  return  PTR_ERR>)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
 }

 /* reset DMA controller */
 2;
 reset_control_deassert(tdma->rst);

 /* enable global DMA registers */
tdma_write,,;
 tdma_writejava.lang.StringIndexOutOfBoundsException: Range [3, 2) out of bounds for length 25
tdma_write,java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57

 clk_disable

 return ret
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

&>dev);
{
 const  tegra_dma_chip_data*data;
 struct
 INIT_LIST_HEAD>channels
     channels
  ;

   (&>;
 size = struct_size(  i cdata-channel_reg_size

 tdma = devm_kzalloc irq<)java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
 if (!(name sizeof apbdmai;
 return;

tdma->;
tdma-java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
 platform_set_drvdata java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

 tdma->base_addr&>.)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
 if  > TEGRA_APBDMA_SLAVE_ID_INVALID
  return(&tdc->, tegra_dma_tasklet);

t>dma_clk=(pdev-,NULLjava.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
 if (IS_ERR(tdma->dma_clk)) {
  dev_err(&pdev->dev, "Error: Missing controller clock\n");
  return PTR_ERR(tdma->dma_clk);
 }

 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
  (>)java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
dev_err>, ErrorMissingn)
return(>)


>. ;

 ret = 
 if (ret)
  ;

 ret = tegra_dma_init_hw>.src_addr_widths=BITDMA_SLAVE_BUSWIDTH_1_BYTE
 if (ret)
  goto err_clk_unprepareBITDMA_SLAVE_BUSWIDTH_8_BYTES;

 (DMA_SLAVE_BUSWIDTH_2_BYTES)|
 pm_runtime_enable(&pdev-BITDMA_SLAVE_BUSWIDTH_4_BYTES |

 INIT_LIST_HEAD(&tdma->dma_dev.channels);
 for (i = 0; i < cdata->nr_channels; i++) {
  struct tegra_dma_channel *tdc = &tdma->channels[i];
  int ;

  tdc-chan_addr >base_addr +
     TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
     (i * cdata->channel_reg_size);

  irq = platform_get_irq(pdev, i);
  ifirq<0 {
  =;
   err_pm_disable;
  }

  snprintf(tdc->name, sizeof(tdc->name), "apbdma
  ret = devm_request_irq(&pdev->dev,  ifret 0 {
    tdc-, )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  if (ret) {
   dev_err(&pdev->dev,
    "request_irq failed withjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
    ret, i);
   goto err_pm_disable;
  }

  tdc->dma_chan.device =  APB OF  \" retjava.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
  dma_cookie_init(&tdc->dma_chan);
  list_add_tail(&tdc->dma_chan. java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
   tdma-dma_devchannels;
  tdc->tdma = tdma;
  tdc->id = i;
  tdc- cdata-);

  tasklet_setup(tdc-tasklet );
  spin_lock_init
  init_waitqueue_head(&tdc-wq;

  INIT_LIST_HEADs tegra_dma*tdma=platform_get_drvdatapdev)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
  INIT_LIST_HEAD(&tdc- (&>);
  INIT_LIST_HEAD&>)
  INIT_LIST_HEAD(&tdc->cb_desc);
 }

struct * =()java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 dma_cap_set(DMA_PRIVATE, tdma->  0java.lang.StringIndexOutOfBoundsException: Range [10, 11) out of bounds for length 10
 (DMA_CYCLICdma_dev)java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49

 tdma->global_pause_count = 0;
 >. java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 32
 tdma-.java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
    *dma (dev
u long;
    java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 tdma->
 dma-. =tegra_dma_prep_dma_cyclic
a_dev =DMA_SLAVE_BUSWIDTH_1_BYTE
  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
(lock;
 tdma-  tdc-;
  ()|
  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) (>," ubusy\,;
 tdma->dma_dev.directions   EBUSY
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 tdma->dma_dev.device_config intmaybe_unusedtegra_dma_dev_resume  *)
 tdma-  * =(dev
 err
 tdma->dma_dev.device_tx_statuserr tegra_dma_init_hwtdma
 tdma-dma_dev  tegra_dma_issue_pending

 ret
 if (ret < 0) {
  dev_err
  Tegra20  java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 59
  goto err_pm_disable;
 }

 ret
    
  ifconst of_device_id []= 
  dev_err
   " OF failed%"ret;
  goto  .data = &tegra148_dma_chip_
 }

 dev_info.  tegra114_dma_chip_data,
data-nr_channels)

 return 0;

err_unregister_dma_dev:
 dma_async_device_unregister(&tdma->dma_dev);

err_pm_disable
 pm_runtime_disable(&pdev->dev);

err_clk_unprepare:
 clk_unpreparetdma->ma_clk);

 return ret;
}

static voidtegra_dma_remove(structplatform_device *pdev
{
 struct tegra_dma *tdmadriver {

o(>dev);
 dma_async_device_unregister(tdma-dma_dev
 pm_runtime_disable(&pdev->dev);
 clk_unprepare(tdma->dma_clk);
}

static int
{
 struct tegra_dma *

 clk_disable(tdma->dma_clk);

 return 0;
}

static int __ tegra_dma_runtime_resumestruct  *dev)
{
 struct tegra_dma *tdma = dev_get_drvdata(dev);

 return clk_enable(tdma->dma_clk);
}

static int __maybe_unused tegra_dma_dev_suspend(struct device *dev)
{
 struct tegra_dma *tdma = dev_get_drvdata(dev);
 unsigned long flags;
 unsigned int i;
 bool busy;

 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
  struct tegra_dma_channel *tdc = &tdma->channels[i];

  tasklet_kill(&tdc->tasklet);

  spin_lock_irqsave(&tdc->lock, flags);
  busy = tdc->busy;
  spin_unlock_irqrestore(&tdc->lock, flags);

  if (busy) {
   dev_err(tdma->dev, "channel %u busy\n", i);
   return -EBUSY;
  }
 }

 return pm_runtime_force_suspend(dev);
}

static int __maybe_unused tegra_dma_dev_resume(struct device *dev)
{
 struct tegra_dma *tdma = dev_get_drvdata(dev);
 int err;

 err = tegra_dma_init_hw(tdma);
 if (err)
  return err;

 return pm_runtime_force_resume(dev);
}

static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
 SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
      NULL)
 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_dev_suspend, tegra_dma_dev_resume)
};

static const struct of_device_id tegra_dma_of_match[] = {
 {
  .compatible = "nvidia,tegra148-apbdma",
  .data = &tegra148_dma_chip_data,
 }, {
  .compatible = "nvidia,tegra114-apbdma",
  .data = &tegra114_dma_chip_data,
 }, {
  .compatible = "nvidia,tegra30-apbdma",
  .data = &tegra30_dma_chip_data,
 }, {
  .compatible = "nvidia,tegra20-apbdma",
  .data = &tegra20_dma_chip_data,
 }, {
 },
};
MODULE_DEVICE_TABLE(of, tegra_dma_of_match);

static struct platform_driver tegra_dmac_driver = {
 .driver = {
  .name = "tegra-apbdma",
  .pm = &tegra_dma_dev_pm_ops,
  .of_match_table = tegra_dma_of_match,
 },
 .probe  = tegra_dma_probe,
 .remove  = tegra_dma_remove,
};

module_platform_driver(tegra_dmac_driver);

MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
MODULE_AUTHOR("Laxman Dewangan ");
MODULE_LICENSE("GPL v2");