reg = ARIZONA_GPIO1_CTRL + offset;
ret = regmap_read(arizona->regmap, reg, &val); if (ret < 0) return ret;
/* Resume to read actual registers for input pins */ if (val & ARIZONA_GPN_DIR) {
ret = pm_runtime_get_sync(chip->parent); if (ret < 0) {
dev_err(chip->parent, "Failed to resume: %d\n", ret);
pm_runtime_put_autosuspend(chip->parent); return ret;
}
/* Register is cached, drop it to ensure a physical read */
ret = regcache_drop_region(arizona->regmap, reg, reg); if (ret < 0) {
dev_err(chip->parent, "Failed to drop cache: %d\n",
ret);
pm_runtime_put_autosuspend(chip->parent); return ret;
}
ret = regmap_read(arizona->regmap, reg, &val); if (ret < 0) {
pm_runtime_put_autosuspend(chip->parent); return ret;
}
pm_runtime_put_autosuspend(chip->parent);
}
if (val & ARIZONA_GPN_LVL) return 1; else return 0;
}
switch (arizona->type) { case WM5102: case WM5110: case WM8280: case WM8997: case WM8998: case WM1814:
arizona_gpio->gpio_chip.ngpio = 5; break; case WM1831: case CS47L24:
arizona_gpio->gpio_chip.ngpio = 2; break; default:
dev_err(&pdev->dev, "Unknown chip variant %d\n",
arizona->type); return -EINVAL;
}
if (pdata->gpio_base)
arizona_gpio->gpio_chip.base = pdata->gpio_base; else
arizona_gpio->gpio_chip.base = -1;
pm_runtime_enable(&pdev->dev);
ret = devm_gpiochip_add_data(&pdev->dev, &arizona_gpio->gpio_chip,
arizona_gpio); if (ret < 0) {
pm_runtime_disable(&pdev->dev);
dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
ret); return ret;
}
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