/* * Copyright 2007-8 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher
*/
/** * amdgpu_display_hotplug_work_func - work handler for display hotplug event * * @work: work struct pointer * * This is the hotplug event work handler (all ASICs). * The work gets scheduled from the IRQ handler if there * was a hotplug interrupt. It walks through the connector table * and calls hotplug handler for each connector. After this, it sends * a DRM hotplug event to alert userspace. * * This design approach is required in order to defer hotplug event handling * from the IRQ handler to a work handler because hotplug handler has to use * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may * sleep).
*/ void amdgpu_display_hotplug_work_func(struct work_struct *work)
{ struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
hotplug_work.work); struct drm_device *dev = adev_to_drm(adev); struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; struct drm_connector_list_iter iter;
mutex_lock(&mode_config->mutex);
drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)
amdgpu_connector_hotplug(connector);
drm_connector_list_iter_end(&iter);
mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */
drm_helper_hpd_irq_event(dev);
}
for (i = 0; i < work->shared_count; ++i) if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) return;
/* Wait until we're out of the vertical blank period before the one * targeted by the flip
*/ if (amdgpu_crtc->enabled &&
(amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
&vpos, &hpos, NULL, NULL,
&crtc->hwmode)
& (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
(int)(work->target_vblank -
amdgpu_get_vblank_counter_kms(crtc)) > 0) {
schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); return;
}
/* We borrow the event spin lock for protecting flip_status */
spin_lock_irqsave(&crtc->dev->event_lock, flags);
/* Do the flip (mmio) */
adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
/* Set the flip status */
amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
/* unpin of the old buffer */
r = amdgpu_bo_reserve(work->old_abo, true); if (likely(r == 0)) {
amdgpu_bo_unpin(work->old_abo);
amdgpu_bo_unreserve(work->old_abo);
} else
DRM_ERROR("failed to reserve buffer after flip\n");
/* pin the new buffer */
r = amdgpu_bo_reserve(new_abo, false); if (unlikely(r != 0)) {
DRM_ERROR("failed to reserve new abo buffer before flip\n"); goto cleanup;
}
if (!adev->enable_virtual_display) {
new_abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
r = amdgpu_bo_pin(new_abo,
amdgpu_display_supported_domains(adev, new_abo->flags)); if (unlikely(r != 0)) {
DRM_ERROR("failed to pin new abo buffer before flip\n"); goto unreserve;
}
}
r = amdgpu_ttm_alloc_gart(&new_abo->tbo); if (unlikely(r != 0)) {
DRM_ERROR("%p bind failed\n", new_abo); goto unpin;
}
r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
&work->shared_count,
&work->shared); if (unlikely(r != 0)) {
DRM_ERROR("failed to get fences for buffer\n"); goto unpin;
}
pflip_cleanup: if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
DRM_ERROR("failed to reserve new abo in error path\n"); goto cleanup;
}
unpin: if (!adev->enable_virtual_display)
amdgpu_bo_unpin(new_abo);
unreserve:
amdgpu_bo_unreserve(new_abo);
cleanup:
amdgpu_bo_unref(&work->old_abo); for (i = 0; i < work->shared_count; ++i)
dma_fence_put(work->shared[i]);
kfree(work->shared);
kfree(work);
return r;
}
int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx)
{ struct drm_device *dev; struct amdgpu_device *adev; struct drm_crtc *crtc; bool active = false; int ret;
if (!set || !set->crtc) return -EINVAL;
dev = set->crtc->dev;
ret = pm_runtime_get_sync(dev->dev); if (ret < 0) goto out;
ret = drm_crtc_helper_set_config(set, ctx);
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) if (crtc->enabled)
active = true;
pm_runtime_mark_last_busy(dev->dev);
adev = drm_to_adev(dev); /* if we have active crtcs and we don't have a power ref, * take the current one
*/ if (active && !adev->have_disp_power_ref) {
adev->have_disp_power_ref = true; return ret;
} /* if we have no active crtcs, then go to * drop the power ref we got before
*/ if (!active && adev->have_disp_power_ref)
adev->have_disp_power_ref = false;
out: /* drop the power reference we got coming in here */
pm_runtime_put_autosuspend(dev->dev); return ret;
}
/* on hw with routers, select right port */ if (amdgpu_connector->router.ddc_valid)
amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
if (use_aux)
ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); else
ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
if (ret != 2) /* Couldn't find an accessible DDC on this connector */ returnfalse; /* Probe also for valid EDID header * EDID header starts with: * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. * Only the first 6 bytes must be valid as * drm_edid_block_valid() can fix the last 2 bytes
*/ if (drm_edid_header_is_valid(buf) < 6) { /* Couldn't find an accessible EDID on this * connector
*/ returnfalse;
} returntrue;
}
#ifdefined(CONFIG_DRM_AMD_DC) /* * if amdgpu_bo_support_uswc returns false it means that USWC mappings * is not supported for this board. But this mapping is required * to avoid hang caused by placement of scanout BO in GTT on certain * APUs. So force the BO placement to VRAM in case this architecture * will not allow USWC mappings. * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
*/ if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
amdgpu_bo_support_uswc(bo_flags) &&
adev->dc_enabled &&
adev->mode_info.gpu_vm_support)
domain |= AMDGPU_GEM_DOMAIN_GTT; #endif
if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) return lookup_format_info(dcc_retile_formats,
ARRAY_SIZE(dcc_retile_formats),
format);
if (AMD_FMT_MOD_GET(DCC, modifier)) return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
format);
/* returning NULL will cause the default format structs to be used. */ return NULL;
}
/* * Tries to extract the renderable DCC offset from the opaque metadata attached * to the buffer.
*/ staticint
extract_render_dcc_offset(struct amdgpu_device *adev, struct drm_gem_object *obj,
uint64_t *offset)
{ struct amdgpu_bo *rbo; int r = 0;
uint32_t metadata[10]; /* Something that fits a descriptor + header. */
uint32_t size;
rbo = gem_to_amdgpu_bo(obj);
r = amdgpu_bo_reserve(rbo, false);
if (unlikely(r)) { /* Don't show error message when returning -ERESTARTSYS */ if (r != -ERESTARTSYS)
DRM_ERROR("Unable to reserve buffer: %d\n", r); return r;
}
r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
amdgpu_bo_unreserve(rbo);
if (r) return r;
/* * The first word is the metadata version, and we need space for at least * the version + pci vendor+device id + 8 words for a descriptor.
*/ if (size < 40 || metadata[0] != 1) return -EINVAL;
/* * If the userspace driver uses retiling the tiling flags do not contain * info on the renderable DCC buffer. Luckily the opaque metadata contains * the info so we can try to extract it. The kernel does not use this info * but we should convert it to a modifier plane for getfb2, so the * userspace driver that gets it doesn't have to juggle around another DCC * plane internally.
*/ if (extract_render_dcc_offset(adev, afb->base.obj[0],
&render_dcc_offset) == 0 &&
render_dcc_offset != 0 &&
render_dcc_offset != afb->base.offsets[1] &&
render_dcc_offset < UINT_MAX) {
uint32_t dcc_block_bits; /* of base surface data */
switch (ver) { case AMD_FMT_MOD_TILE_VER_GFX9: { /* * TODO: for pipe aligned we may need to check the alignment of the * total size of the surface, which may need to be bigger than the * natural alignment due to some HW workarounds
*/ return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
} case AMD_FMT_MOD_TILE_VER_GFX10: case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: case AMD_FMT_MOD_TILE_VER_GFX11: { int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
if (rfb->base.pitches[plane] % block_pitch) {
drm_dbg_kms(rfb->base.dev, "pitch %d for plane %d is not a multiple of block pitch %d\n",
rfb->base.pitches[plane], plane, block_pitch); return -EINVAL;
} if (rfb->base.pitches[plane] < min_pitch) {
drm_dbg_kms(rfb->base.dev, "pitch %d for plane %d is less than minimum pitch %d\n",
rfb->base.pitches[plane], plane, min_pitch); return -EINVAL;
}
/* Force at least natural alignment. */ if (rfb->base.offsets[plane] % block_size) {
drm_dbg_kms(rfb->base.dev, "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
rfb->base.offsets[plane], plane, block_size); return -EINVAL;
}
if (rfb->base.obj[0]->size < size) {
drm_dbg_kms(rfb->base.dev, "BO size 0x%zx is less than 0x%llx required for plane %d\n",
rfb->base.obj[0]->size, size, plane); return -EINVAL;
}
rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
r = amdgpu_bo_reserve(rbo, false);
if (unlikely(r)) { /* Don't show error message when returning -ERESTARTSYS */ if (r != -ERESTARTSYS)
DRM_ERROR("Unable to reserve buffer: %d\n", r); return r;
}
rfb->base.obj[0] = obj;
drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
mode_cmd->modifier[0])) {
drm_dbg_kms(dev, "unsupported pixel format %p4cc / modifier 0x%llx\n",
&mode_cmd->pixel_format, mode_cmd->modifier[0]);
ret = -EINVAL; goto err;
}
ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) goto err;
if (drm_drv_uses_atomic_modeset(dev))
ret = drm_framebuffer_init(dev, &rfb->base,
&amdgpu_fb_funcs_atomic); else
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
if (ret) goto err;
return 0;
err:
drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
rfb->base.obj[0] = NULL; return ret;
}
/* * This needs to happen before modifier conversion as that might change * the number of planes.
*/ for (i = 1; i < rfb->base.format->num_planes; ++i) { if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
i, mode_cmd->handles[0], mode_cmd->handles[i]);
ret = -EINVAL; return ret;
}
}
ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface,
&rfb->gfx12_dcc); if (ret) return ret;
if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n");
ret = check_tiling_flags_gfx6(rfb); if (ret) return ret;
}
if (!dev->mode_config.fb_modifiers_not_supported &&
!(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0))
ret = convert_tiling_flags_to_modifier_gfx12(rfb); else
ret = convert_tiling_flags_to_modifier(rfb);
if (ret) {
drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
rfb->tiling_flags); return ret;
}
}
ret = amdgpu_display_verify_sizes(rfb); if (ret) return ret;
for (i = 0; i < rfb->base.format->num_planes; ++i) {
drm_gem_object_get(rfb->base.obj[0]);
rfb->base.obj[i] = rfb->base.obj[0];
}
obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); if (obj == NULL) {
drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, can't create framebuffer\n",
mode_cmd->handles[0]);
return ERR_PTR(-ENOENT);
}
/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
bo = gem_to_amdgpu_bo(obj);
domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); if (drm_gem_is_imported(obj) && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
drm_gem_object_put(obj); return ERR_PTR(-EINVAL);
}
/* * Retrieve current video scanout position of crtc on a given gpu, and * an optional accurate timestamp of when query happened. * * \param dev Device to query. * \param pipe Crtc to query. * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). * For driver internal use only also supports these flags: * * USE_REAL_VBLANKSTART to use the real start of vblank instead * of a fudged earlier start of vblank. * * GET_DISTANCE_TO_VBLANKSTART to return distance to the * fudged earlier start of vblank in *vpos and the distance * to true start of vblank in *hpos. * * \param *vpos Location where vertical scanout position should be stored. * \param *hpos Location where horizontal scanout position should go. * \param *stime Target location for timestamp taken immediately before * scanout position query. Can be NULL to skip timestamp. * \param *etime Target location for timestamp taken immediately after * scanout position query. Can be NULL to skip timestamp. * * Returns vpos as a positive number while in active scanout area. * Returns vpos as a negative number inside vblank, counting the number * of scanlines to go until end of vblank, e.g., -1 means "one scanline * until start of active scanout / end of vblank." * * \return Flags, or'ed together as follows: * * DRM_SCANOUTPOS_VALID = Query successful. * DRM_SCANOUTPOS_INVBL = Inside vblank. * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of * this flag means that returned position may be offset by a constant but * unknown small number of scanlines wrt. real scanout position. *
*/ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, unsignedint pipe, unsignedint flags, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, conststruct drm_display_mode *mode)
{
u32 vbl = 0, position = 0; int vbl_start, vbl_end, vtotal, ret = 0; bool in_vbl = true;
struct amdgpu_device *adev = drm_to_adev(dev);
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
/* Get optional system timestamp before query. */ if (stime)
*stime = ktime_get();
if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
ret |= DRM_SCANOUTPOS_VALID;
/* Get optional system timestamp after query. */ if (etime)
*etime = ktime_get();
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
/* Decode into vertical and horizontal scanout position. */
*vpos = position & 0x1fff;
*hpos = (position >> 16) & 0x1fff;
/* Valid vblank area boundaries from gpu retrieved? */ if (vbl > 0) { /* Yes: Decode. */
ret |= DRM_SCANOUTPOS_ACCURATE;
vbl_start = vbl & 0x1fff;
vbl_end = (vbl >> 16) & 0x1fff;
} else { /* No: Fake something reasonable which gives at least ok results. */
vbl_start = mode->crtc_vdisplay;
vbl_end = 0;
}
/* Called from driver internal vblank counter query code? */ if (flags & GET_DISTANCE_TO_VBLANKSTART) { /* Caller wants distance from real vbl_start in *hpos */
*hpos = *vpos - vbl_start;
}
/* Fudge vblank to start a few scanlines earlier to handle the * problem that vblank irqs fire a few scanlines before start * of vblank. Some driver internal callers need the true vblank * start to be used and signal this via the USE_REAL_VBLANKSTART flag. * * The cause of the "early" vblank irq is that the irq is triggered * by the line buffer logic when the line buffer read position enters * the vblank, whereas our crtc scanout position naturally lags the * line buffer read position.
*/ if (!(flags & USE_REAL_VBLANKSTART))
vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
/* Test scanout position against vblank region. */ if ((*vpos < vbl_start) && (*vpos >= vbl_end))
in_vbl = false;
/* In vblank? */ if (in_vbl)
ret |= DRM_SCANOUTPOS_IN_VBLANK;
/* Called from driver internal vblank counter query code? */ if (flags & GET_DISTANCE_TO_VBLANKSTART) { /* Caller wants distance from fudged earlier vbl_start */
*vpos -= vbl_start; return ret;
}
/* Check if inside vblank area and apply corrective offsets: * vpos will then be >=0 in video scanout area, but negative * within vblank area, counting down the number of lines until * start of scanout.
*/
/* Inside "upper part" of vblank area? Apply corrective offset if so: */ if (in_vbl && (*vpos >= vbl_start)) {
vtotal = mode->crtc_vtotal;
/* With variable refresh rate displays the vpos can exceed * the vtotal value. Clamp to 0 to return -vbl_end instead * of guessing the remaining number of lines until scanout.
*/
*vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
}
/* Correct for shifted end of vbl at vbl_end. */
*vpos = *vpos - vbl_end;
return ret;
}
int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
{ if (crtc < 0 || crtc >= adev->mode_info.num_crtc) return AMDGPU_CRTC_IRQ_NONE;
switch (crtc) { case 0: return AMDGPU_CRTC_IRQ_VBLANK1; case 1: return AMDGPU_CRTC_IRQ_VBLANK2; case 2: return AMDGPU_CRTC_IRQ_VBLANK3; case 3: return AMDGPU_CRTC_IRQ_VBLANK4; case 4: return AMDGPU_CRTC_IRQ_VBLANK5; case 5: return AMDGPU_CRTC_IRQ_VBLANK6; default: return AMDGPU_CRTC_IRQ_NONE;
}
}
/* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used in amdgpu_dm_set_pixel() * they are called from the panic handler, and protected by the drm_panic spinlock.
*/ staticstruct amdgpu_bo *panic_abo;
/* Use the indirect MMIO to write each pixel to the GPU VRAM, * This is a simplified version of amdgpu_device_mm_access()
*/ staticvoid amdgpu_display_set_pixel(struct drm_scanout_buffer *sb, unsignedint x, unsignedint y,
u32 color)
{ struct amdgpu_res_cursor cursor; unsignedlong offset; struct amdgpu_bo *abo = panic_abo; struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
uint32_t tmp;
offset = x * 4 + y * sb->pitch[0];
amdgpu_res_first(abo->tbo.resource, offset, 4, &cursor);
abo = gem_to_amdgpu_bo(fb->obj[0]); if (!abo) return -EINVAL;
sb->width = fb->width;
sb->height = fb->height; /* Use the generic linear format, because tiling will be disabled in panic_flush() */
sb->format = drm_format_info(fb->format->format); if (!sb->format) return -EINVAL;
sb->pitch[0] = fb->pitches[0];
if (abo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) { if (abo->tbo.resource->mem_type != TTM_PL_VRAM) {
drm_warn(plane->dev, "amdgpu panic, framebuffer not in VRAM\n"); return -EINVAL;
} /* Only handle 32bits format, to simplify mmio access */ if (fb->format->cpp[0] != 4) {
drm_warn(plane->dev, "amdgpu panic, pixel format is not 32bits\n"); return -EINVAL;
}
sb->set_pixel = amdgpu_display_set_pixel;
panic_abo = abo; return 0;
} if (!abo->kmap.virtual &&
ttm_bo_kmap(&abo->tbo, 0, PFN_UP(abo->tbo.base.size), &abo->kmap)) {
drm_warn(plane->dev, "amdgpu bo map failed, panic won't be displayed\n"); return -ENOMEM;
} if (abo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK)
iosys_map_set_vaddr_iomem(&sb->map[0], abo->kmap.virtual); else
iosys_map_set_vaddr(&sb->map[0], abo->kmap.virtual);
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