/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * #include <linux/delay.h>#include <linux/kernel.h>#include <linux/firmware.h>#include <linux/module.h>#include <linux/pci.h>#include "amdgpu.h" #include "amdgpu_gfx.h" #include "amdgpu_psp.h" #include "nv.h" #include "nvd.h" #include "gc/gc_10_1_0_offset.h" #include "gc/gc_10_1_0_sh_mask.h" #include "smuio/smuio_11_0_0_offset.h" #include "smuio/smuio_11_0_0_sh_mask.h" #include "navi10_enum.h" #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" #include "soc15.h" #include "soc15_common.h" #include "clearstate_gfx10.h" #include "v10_structs.h" #include "gfx_v10_0.h" #include "gfx_v10_0_cleaner_shader.h" #include "nbio_v2_3.h" /* * Navi10 has two graphic rings to share each graphic pipe. * 1. Primary ring * 2. Async ring #define GFX10_NUM_GFX_RINGS_NV1X 1#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2#define GFX10_MEC_HPD_SIZE 2048#define F32_CE_PROGRAM_RAM_SIZE 65536#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L#define mmCGTT_GS_NGG_CLK_CTRL 0x5087#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1#define mmCGTT_SPI_RA0_CLK_CTRL 0x507a#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1#define mmCGTT_SPI_RA1_CLK_CTRL 0x507b#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8#define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L#define mmCGTS_TCC_DISABLE_gc_10_3 0x5006#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1#define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1#define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0#define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1#define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0#define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1#define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1#define mmVGT_TF_RING_SIZE_Vangogh 0x224e#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1#define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1#define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1#define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1#define mmSPI_CONFIG_CNTL_Vangogh 0x2440#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1#define mmGCR_GENERAL_CNTL_Vangogh 0x1580#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL#define mmCP_HYP_PFP_UCODE_ADDR 0x5814#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1#define mmCP_HYP_PFP_UCODE_DATA 0x5815#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1#define mmCP_HYP_CE_UCODE_ADDR 0x5818#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1#define mmCP_HYP_CE_UCODE_DATA 0x5819#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1#define mmCP_HYP_ME_UCODE_ADDR 0x5816#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1#define mmCP_HYP_ME_UCODE_DATA 0x5817#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1#define mmCPG_PSP_DEBUG 0x5c10#define mmCPG_PSP_DEBUG_BASE_IDX 1#define mmCPC_PSP_DEBUG 0x5c11#define mmCPC_PSP_DEBUG_BASE_IDX 1#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L//CC_GC_SA_UNIT_DISABLE #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L//GC_USER_SA_UNIT_DISABLE #define mmGC_USER_SA_UNIT_DISABLE 0x0fea#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L//PA_SC_ENHANCE_3 #define mmPA_SC_ENHANCE_3 0x1085#define mmPA_SC_ENHANCE_3_BASE_IDX 0#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L#define mmCGTT_SPI_CS_CLK_CTRL 0x507c#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1"amdgpu/navi10_ce.bin" );"amdgpu/navi10_pfp.bin" );"amdgpu/navi10_me.bin" );"amdgpu/navi10_mec.bin" );"amdgpu/navi10_mec2.bin" );"amdgpu/navi10_rlc.bin" );"amdgpu/navi14_ce_wks.bin" );"amdgpu/navi14_pfp_wks.bin" );"amdgpu/navi14_me_wks.bin" );"amdgpu/navi14_mec_wks.bin" );"amdgpu/navi14_mec2_wks.bin" );"amdgpu/navi14_ce.bin" );"amdgpu/navi14_pfp.bin" );"amdgpu/navi14_me.bin" );"amdgpu/navi14_mec.bin" );"amdgpu/navi14_mec2.bin" );"amdgpu/navi14_rlc.bin" );"amdgpu/navi12_ce.bin" );"amdgpu/navi12_pfp.bin" );"amdgpu/navi12_me.bin" );"amdgpu/navi12_mec.bin" );"amdgpu/navi12_mec2.bin" );"amdgpu/navi12_rlc.bin" );"amdgpu/sienna_cichlid_ce.bin" );"amdgpu/sienna_cichlid_pfp.bin" );"amdgpu/sienna_cichlid_me.bin" );"amdgpu/sienna_cichlid_mec.bin" );"amdgpu/sienna_cichlid_mec2.bin" );"amdgpu/sienna_cichlid_rlc.bin" );"amdgpu/navy_flounder_ce.bin" );"amdgpu/navy_flounder_pfp.bin" );"amdgpu/navy_flounder_me.bin" );"amdgpu/navy_flounder_mec.bin" );"amdgpu/navy_flounder_mec2.bin" );"amdgpu/navy_flounder_rlc.bin" );"amdgpu/vangogh_ce.bin" );"amdgpu/vangogh_pfp.bin" );"amdgpu/vangogh_me.bin" );"amdgpu/vangogh_mec.bin" );"amdgpu/vangogh_mec2.bin" );"amdgpu/vangogh_rlc.bin" );"amdgpu/dimgrey_cavefish_ce.bin" );"amdgpu/dimgrey_cavefish_pfp.bin" );"amdgpu/dimgrey_cavefish_me.bin" );"amdgpu/dimgrey_cavefish_mec.bin" );"amdgpu/dimgrey_cavefish_mec2.bin" );"amdgpu/dimgrey_cavefish_rlc.bin" );"amdgpu/beige_goby_ce.bin" );"amdgpu/beige_goby_pfp.bin" );"amdgpu/beige_goby_me.bin" );"amdgpu/beige_goby_mec.bin" );"amdgpu/beige_goby_mec2.bin" );"amdgpu/beige_goby_rlc.bin" );"amdgpu/yellow_carp_ce.bin" );"amdgpu/yellow_carp_pfp.bin" );"amdgpu/yellow_carp_me.bin" );"amdgpu/yellow_carp_mec.bin" );"amdgpu/yellow_carp_mec2.bin" );"amdgpu/yellow_carp_rlc.bin" );"amdgpu/cyan_skillfish2_ce.bin" );"amdgpu/cyan_skillfish2_pfp.bin" );"amdgpu/cyan_skillfish2_me.bin" );"amdgpu/cyan_skillfish2_mec.bin" );"amdgpu/cyan_skillfish2_mec2.bin" );"amdgpu/cyan_skillfish2_rlc.bin" );"amdgpu/gc_10_3_6_ce.bin" );"amdgpu/gc_10_3_6_pfp.bin" );"amdgpu/gc_10_3_6_me.bin" );"amdgpu/gc_10_3_6_mec.bin" );"amdgpu/gc_10_3_6_mec2.bin" );"amdgpu/gc_10_3_6_rlc.bin" );"amdgpu/gc_10_3_7_ce.bin" );"amdgpu/gc_10_3_7_pfp.bin" );"amdgpu/gc_10_3_7_me.bin" );"amdgpu/gc_10_3_7_mec.bin" );"amdgpu/gc_10_3_7_mec2.bin" );"amdgpu/gc_10_3_7_rlc.bin" );static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {/* cp header registers */ /* SE status registers */ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {/* compute registers */ /* cp header registers */ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {/* gfx queue registers */ /* gfx header registers */ static const struct soc15_reg_golden golden_settings_gc_10_1[] = {),static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {/* Pending on emulation bring up */ static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
Messung V0.5 C=91 H=98 G=94
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