/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * #ifndef SOC15_H#define SOC15_H#define GFX9_NUM_GFX_RINGS 1#define GFX9_NUM_COMPUTE_RINGS 8/* * PM4 #define PACKET_TYPE0 0#define PACKET_TYPE1 1#define PACKET_TYPE2 2#define PACKET_TYPE3 3#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \#define CP_PACKET2 0x80000000#define PACKET2_PAD_SHIFT 0#define PACKET2_PAD_MASK (0x3fffffff << 0)#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)#define PACKETJ_CONDITION_CHECK0 0#define PACKETJ_CONDITION_CHECK1 1#define PACKETJ_CONDITION_CHECK2 2#define PACKETJ_CONDITION_CHECK3 3#define PACKETJ_CONDITION_CHECK4 4#define PACKETJ_CONDITION_CHECK5 5#define PACKETJ_CONDITION_CHECK6 6#define PACKETJ_CONDITION_CHECK7 7#define PACKETJ_TYPE0 0#define PACKETJ_TYPE1 1#define PACKETJ_TYPE2 2#define PACKETJ_TYPE3 3#define PACKETJ_TYPE4 4#define PACKETJ_TYPE5 5#define PACKETJ_TYPE6 6#define PACKETJ_TYPE7 7#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \#define CP_PACKETJ_NOP 0x60000000#define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF)#define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F)#define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF)#define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF)/* Packet 3 types */ #define PACKET3_NOP 0x10#define PACKET3_SET_BASE 0x11#define PACKET3_BASE_INDEX(x) ((x) << 0)#define CE_PARTITION_BASE 3#define PACKET3_CLEAR_STATE 0x12#define PACKET3_INDEX_BUFFER_SIZE 0x13#define PACKET3_DISPATCH_DIRECT 0x15#define PACKET3_DISPATCH_INDIRECT 0x16#define PACKET3_ATOMIC_GDS 0x1D#define PACKET3_ATOMIC_MEM 0x1E#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned )(x)) & 0x3F) << 0)#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned )(x)) & 0xF) << 8)#define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned )(x)) & 0x3) << 25)#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned )(x)) << 0)#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned )(x)) << 0)#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned )(x)) << 0)#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned )(x)) << 0)#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned )(x)) << 0)#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned )(x)) << 0)#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned )(x)) & 0x1FFF) << 0)#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1#define PACKET3_OCCLUSION_QUERY 0x1F#define PACKET3_SET_PREDICATION 0x20#define PACKET3_REG_RMW 0x21#define PACKET3_COND_EXEC 0x22#define PACKET3_PRED_EXEC 0x23#define PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned )(x)) & 0x3FFF) << 0)#define PACKET3_PRED_EXEC__VIRTUAL_XCC_ID_SELECT(x) ((((unsigned )(x)) & 0xFF) << 24)#define PACKET3_DRAW_INDIRECT 0x24#define PACKET3_DRAW_INDEX_INDIRECT 0x25#define PACKET3_INDEX_BASE 0x26#define PACKET3_DRAW_INDEX_2 0x27#define PACKET3_CONTEXT_CONTROL 0x28#define PACKET3_INDEX_TYPE 0x2A#define PACKET3_DRAW_INDIRECT_MULTI 0x2C#define PACKET3_DRAW_INDEX_AUTO 0x2D#define PACKET3_NUM_INSTANCES 0x2F#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30#define PACKET3_INDIRECT_BUFFER_CONST 0x33#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34#define PACKET3_DRAW_INDEX_OFFSET_2 0x35#define PACKET3_DRAW_PREAMBLE 0x36#define PACKET3_WRITE_DATA 0x37#define WRITE_DATA_DST_SEL(x) ((x) << 8)/* 0 - register * 1 - memory (sync - via GRBM) * 2 - gl2 * 3 - gds * 4 - reserved * 5 - memory (async - direct) #define WR_ONE_ADDR (1 << 16)#define WR_CONFIRM (1 << 20)#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)/* 0 - LRU * 1 - Stream #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)/* 0 - me * 1 - pfp * 2 - ce #define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned )(x)) & 0xF) << 8)#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned )(x)) & 0x1) << 16)#define PACKET3_WRITE_DATA__RESUME_VF_MI300(x) ((((unsigned )(x)) & 0x1) << 19)#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned )(x)) & 0x1) << 20)#define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned )(x)) & 0x3) << 25)#define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned )(x)) & 0x3FFFF) << 0)#define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned )(x)) & 0x3FFFFFFF) << 2)#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned )(x))#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2#define PACKET3_WRITE_DATA__DST_SEL__GDS 3#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1#define PACKET3_WRITE_DATA__CACHE_POLICY__LRU 0#define PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1#define PACKET3_WRITE_DATA__CACHE_POLICY__NOA 2#define PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38#define PACKET3_MEM_SEMAPHORE 0x39# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)# define PACKET3_SEM_SEL_WAIT (0x7 << 29)#define PACKET3_WAIT_REG_MEM 0x3C#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)/* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)/* 0 - reg * 1 - mem #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)/* 0 - wait_reg_mem * 1 - wr_wait_wr_reg #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)/* 0 - me * 1 - pfp #define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned )(x)) & 0x7) << 0)#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned )(x)) & 0x3) << 4)#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned )(x)) & 0x3) << 6)#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned )(x)) & 0x3) << 22)#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned )(x)) & 0x1) << 24)#define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned )(x)) & 0x3) << 25)#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned )(x)) & 0x3FFFFFFF) << 2)#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned )(x)) & 0x3FFFF) << 0)#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned )(x)) & 0x3FFFF) << 0)#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned )(x))#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned )(x)) & 0x3FFFF) << 0)#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned )(x))#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned )(x))#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned )(x)) & 0x1) << 31)#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3#define PACKET3_INDIRECT_BUFFER 0x3F#define INDIRECT_BUFFER_VALID (1 << 23)#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)/* 0 - LRU * 1 - Stream * 2 - Bypass #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned )(x)) & 0x3FFFFFFF) << 2)#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned )(x))#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned )(x)) & 0xFFFFF) << 0)#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned )(x)) & 0x1) << 20)#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned )(x)) & 0x1) << 21)#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned )(x)) & 0x1) << 23)#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned )(x)) & 0xF) << 24)#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned )(x)) & 0x3) << 28)#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned )(x)) & 0x1) << 31)#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU 0#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1#define PACKET3_COPY_DATA 0x40#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned )(x)) & 0xF) << 0)#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned )(x)) & 0xF) << 8)#define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned )(x)) & 0x3) << 13)#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned )(x)) & 0x1) << 16)#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned )(x)) & 0x1) << 20)#define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned )(x)) & 0x3) << 25)#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned )(x)) & 0x1) << 29)#define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned )(x)) & 0x3FFFF) << 0)#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned )(x)) & 0x3FFFFFFF) << 2)#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned )(x)) & 0x1FFFFFFF) << 3)#define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned )(x))#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned )(x))#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned )(x))#define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned )(x)) & 0x3FFFF) << 0)#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned )(x)) & 0x3FFFFFFF) << 2)#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned )(x)) & 0x1FFFFFFF) << 3)#define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned )(x))#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0#define PACKET3_COPY_DATA__SRC_SEL__MEMORY 1#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2#define PACKET3_COPY_DATA__SRC_SEL__GDS 3#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 7#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 8#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2#define PACKET3_COPY_DATA__DST_SEL__GDS 3#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4#define PACKET3_COPY_DATA__DST_SEL__MEMORY 5#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU 0#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1#define PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU 0#define PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1#define PACKET3_PFP_SYNC_ME 0x42#define PACKET3_COND_WRITE 0x45#define PACKET3_EVENT_WRITE 0x46#define EVENT_TYPE(x) ((x) << 0)#define EVENT_INDEX(x) ((x) << 8)/* 0 - any non-TS event * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH #define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned )(x)) & 0x3F) << 0)#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned )(x)) & 0xF) << 8)#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned )(x)) & 0x1) << 31)#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned )(x)) & 0x3) << 29)#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned )(x)) & 0x1FFFFFFF) << 3)#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) (((unsigned )(x)) << 0)#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTATS 2#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4#define PACKET3_RELEASE_MEM 0x49#define EVENT_TYPE(x) ((x) << 0)#define EVENT_INDEX(x) ((x) << 8)#define EOP_TCL1_VOL_ACTION_EN (1 << 12)#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ #define EOP_TCL1_ACTION_EN (1 << 16)#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ #define EOP_TC_NC_ACTION_EN (1 << 19)#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */ #define EOP_EXEC (1 << 28) /* For Trailing Fence */ #define DATA_SEL(x) ((x) << 29)/* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value #define INT_SEL(x) ((x) << 24)/* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed #define DST_SEL(x) ((x) << 16)/* 0 - MC * 1 - TC/L2 #define PACKET3_PREAMBLE_CNTL 0x4A# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)#define PACKET3_DMA_DATA 0x50/* 1. header * 2. CONTROL * 3. SRC_ADDR_LO or DATA [31:0] * 4. SRC_ADDR_HI [31:0] * 5. DST_ADDR_LO [31:0] * 6. DST_ADDR_HI [7:0] * 7. COMMAND [30:21] | BYTE_COUNT [20:0] /* CONTROL */ # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)/* 0 - ME * 1 - PFP # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)/* 0 - LRU * 1 - Stream # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)/* 0 - DST_ADDR using DAS * 1 - GDS * 3 - DST_ADDR using L2 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)/* 0 - LRU * 1 - Stream # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)/* 0 - SRC_ADDR using SAS * 1 - GDS * 2 - DATA * 3 - SRC_ADDR using L2 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)/* COMMAND */ # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)/* 0 - memory * 1 - register # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)/* 0 - memory * 1 - register # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)#define PACKET3_ACQUIRE_MEM 0x58/* 1. HEADER * 2. COHER_CNTL [30:0] * 2.1 ENGINE_SEL [31:31] * 3. COHER_SIZE [31:0] * 4. COHER_SIZE_HI [7:0] * 5. COHER_BASE_LO [31:0] * 6. COHER_BASE_HI [23:0] * 7. POLL_INTERVAL [15:0] /* COHER_CNTL fields for CP_COHER_CNTL */ #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)#define PACKET3_REWIND 0x59#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned )(x))#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned )(x)) & 0xFF) << 0)#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI_VG10(x) ((((unsigned )(x)) & 0xFFFFFF) << 0)#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned )(x))#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned )(x)) & 0xFFFFFF) << 0)#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned )(x)) & 0x7FF) << 0)#define PACKET3_LOAD_UCONFIG_REG 0x5E#define PACKET3_LOAD_SH_REG 0x5F#define PACKET3_LOAD_CONFIG_REG 0x60#define PACKET3_LOAD_CONTEXT_REG 0x61#define PACKET3_SET_CONFIG_REG 0x68#define PACKET3_SET_CONFIG_REG_START 0x00002000#define PACKET3_SET_CONFIG_REG_END 0x00002c00#define PACKET3_SET_CONTEXT_REG 0x69#define PACKET3_SET_CONTEXT_REG_START 0x0000a000#define PACKET3_SET_CONTEXT_REG_END 0x0000a400#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73#define PACKET3_SET_SH_REG 0x76#define PACKET3_SET_SH_REG_START 0x00002c00#define PACKET3_SET_SH_REG_END 0x00003000#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned )(x)) & 0x1F) << 23)#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned )(x)) & 0xF) << 28)#define PACKET3_SET_SH_REG_OFFSET 0x77#define PACKET3_SET_QUEUE_REG 0x78#define PACKET3_SET_UCONFIG_REG 0x79#define PACKET3_SET_UCONFIG_REG_START 0x0000c000#define PACKET3_SET_UCONFIG_REG_END 0x0000c400#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned )(x)) & 0xFFFF) << 0)#define PACKET3_SCRATCH_RAM_WRITE 0x7D#define PACKET3_SCRATCH_RAM_READ 0x7E#define PACKET3_LOAD_CONST_RAM 0x80#define PACKET3_WRITE_CONST_RAM 0x81#define PACKET3_DUMP_CONST_RAM 0x83#define PACKET3_INCREMENT_CE_COUNTER 0x84#define PACKET3_INCREMENT_DE_COUNTER 0x85#define PACKET3_WAIT_ON_CE_COUNTER 0x86#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88#define PACKET3_SWITCH_BUFFER 0x8B#define PACKET3_FRAME_CONTROL 0x90# define FRAME_TMZ (1 << 0)# define FRAME_CMD(x) ((x) << 28)/* * x=0: tmz_begin * x=1: tmz_end #define PACKET3_INVALIDATE_TLBS 0x98# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)#define PACKET3_SET_RESOURCES 0xA0/* 1. header * 2. CONTROL * 3. QUEUE_MASK_LO [31:0] * 4. QUEUE_MASK_HI [31:0] * 5. GWS_MASK_LO [31:0] * 6. GWS_MASK_HI [31:0] * 7. OAC_MASK [15:0] * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)#define PACKET3_MAP_QUEUES 0xA2/* 1. header * 2. CONTROL * 3. CONTROL2 * 4. MQD_ADDR_LO [31:0] * 5. MQD_ADDR_HI [31:0] * 6. WPTR_ADDR_LO [31:0] * 7. WPTR_ADDR_HI [31:0] /* CONTROL */ # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)/* CONTROL2 */ # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)#define PACKET3_UNMAP_QUEUES 0xA3/* 1. header * 2. CONTROL * 3. CONTROL2 * 4. CONTROL3 * 5. CONTROL4 * 6. CONTROL5 /* CONTROL */ # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)/* 0 - PREEMPT_QUEUES * 1 - RESET_QUEUES * 2 - DISABLE_PROCESS_QUEUES * 3 - PREEMPT_QUEUES_NO_UNMAP # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)/* CONTROL2a */ # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)/* CONTROL2b */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)/* CONTROL3a */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)/* CONTROL3b */ # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)/* CONTROL4 */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)/* CONTROL5 */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)#define PACKET3_QUERY_STATUS 0xA4/* 1. header * 2. CONTROL * 3. CONTROL2 * 4. ADDR_LO [31:0] * 5. ADDR_HI [31:0] * 6. DATA_LO [31:0] * 7. DATA_HI [31:0] /* CONTROL */ # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)/* CONTROL2a */ # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)/* CONTROL2b */ # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)#define PACKET3_RUN_CLEANER_SHADER_9_0 0xD7/* 1. header * 2. RESERVED [31:0] #define PACKET3_RUN_CLEANER_SHADER 0xD2/* 1. header * 2. RESERVED [31:0] #define VCE_CMD_NO_OP 0x00000000#define VCE_CMD_END 0x00000001#define VCE_CMD_IB 0x00000002#define VCE_CMD_FENCE 0x00000003#define VCE_CMD_TRAP 0x00000004#define VCE_CMD_IB_AUTO 0x00000005#define VCE_CMD_SEMAPHORE 0x00000006#define VCE_CMD_IB_VM 0x00000102#define VCE_CMD_WAIT_GE 0x00000106#define VCE_CMD_UPDATE_PTB 0x00000107#define VCE_CMD_FLUSH_TLB 0x00000108#define VCE_CMD_REG_WRITE 0x00000109#define VCE_CMD_REG_WAIT 0x0000010a#define HEVC_ENC_CMD_NO_OP 0x00000000#define HEVC_ENC_CMD_END 0x00000001#define HEVC_ENC_CMD_FENCE 0x00000003#define HEVC_ENC_CMD_TRAP 0x00000004#define HEVC_ENC_CMD_IB_VM 0x00000102#define HEVC_ENC_CMD_REG_WRITE 0x00000109#define HEVC_ENC_CMD_REG_WAIT 0x0000010a#endif
Messung V0.5 C=94 H=96 G=94
¤ Dauer der Verarbeitung: 0.6 Sekunden
¤ *© Formatika GbR, Deutschland
