Quelle  soc21.c   Sprache: C

/*
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "amdgpu * Copyright 2021 Advanced Micro Devices, Inc. *
#include "amdgpu_atombios.h" * copy of this * to deal in the Software without restriction, including without * the rights to use, copy, modify, merge * and/or sell copies of the Software, and to permit persons to whom the
#include "amdgpu_ih.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_ucode.h"
#include "amdgpu_psp.h"
#include "amdgpu_smu.h"
#include "atom.h"
#include "amd_pcie.h"

#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
#include "mp/mp_13_0_0_offset.h"

#include "soc15.h"
#include "soc15_common.h"
#include "soc21.h"
#include "mxgpu_nv.h"

static const struct amd_ip_funcs soc21_common_ip_funcs;

/* SOC21 */
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
};

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
};

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
};

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
};

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
};

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
};

/* SRIOV SOC21, not const since data is controlled by host */
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)include
 
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

staticconst   =java.lang.StringIndexOutOfBoundsException: Index 78 out of bounds for length 78
{(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC46 ),
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
};

static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
 .codec_arrayjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
};

static struct amdgpu_video_codecscodec_countARRAY_SIZE),
 .codec_count (sriov_vcn_4_0_0_video_codecs_encode_array_vcn1
 ;
};

static  amdgpu_video_codec_info[] = java.lang.StringIndexOutOfBoundsException: Index 90 out of bounds for length 90
codec_info_build, 496 06 2}java.lang.StringIndexOutOfBoundsException: Index 80 out of bounds for length 80
 {codec_info_build(codec_info_build, 12 45,0},
staticconst  vcn_4_0_0_video_codecs_decode_array_vcn1
, 4320,
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)} ,28
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 struct [ java.lang.StringIndexOutOfBoundsException: Index 90 out of bounds for length 90
(, 406 06 2}
 {codec_info_build = ,
 {(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,68,134 ),
 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
};

static structamdgpu_video_codecs = {
 .codec_count = ARRAY_SIZE  amdgpu_video_codec_info [] = {
 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
};

staticstruct amdgpu_video_codecssriov_vcn_4_0_0_video_codecs_decode_vcn1={
. = ARRAY_SIZE),
 .codec_arraycodec_info_buildAMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV112 32 0),
};

static int soc21_query_video_codecs;
     const
{
  codec_info_build, 4096 06 ),
  return -EINVAL;

 switch icodec_info_build, 812 42 0)},
 case IP_VERSION(4, 0, 0):
 case IP_VERSION4 0 2:
 case IP_VERSION(4, 0, 4):
 case IP_VERSION(4, 0, 5):
  if (amdgpu_sriov_vf;
staticstruct sriov_vcn_4_0_0_video_codecs_encode_vcn0 {
  !(adevjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
  ifencode)
     *codecs =  codec_count ARRAY_SIZE(),
   else
     *codecs = ;
    struct sriov_vcn_4_0_0_video_codecs_decode_array_vcn0={
    if (encode)
     *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
    else
     *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
  }
  {(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC12 5,186}java.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76
  if (>vcn &AMDGPU_VCN_HARVEST_VCN0){
    if{(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV15 0
static  amdgpu_video_codec_info[] ={
    else
     *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
   } codec_info_build, 406 06 2}java.lang.StringIndexOutOfBoundsException: Index 80 out of bounds for length 80
    ifencode
   * = &;
    else;
     *codecs struct sriov_vcn_4_0_0_video_codecs_decode_vcn0
  }
  }
  return 0;
 case IP_VERSION(4, 0,   = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0
  if encode
   *codecs    (),
  else
   codecs&;
 ;
 default  soc21_query_video_codecs amdgpu_device adev encode
  return -  const struct *)
 }
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

  IP_VERSION,0)java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
{
  long, address;
 u32 r;

 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX   (adev-.harvest_config AMDGPU_VCN_HARVEST_VCN0) |java.lang.StringIndexOutOfBoundsException: Range [62, 63) out of bounds for length 62
 dataSOC15_REG_OFFSETGC0 );

   ifencode
(address(reg
 r   else
spin_unlock_irqrestoreadev->, flags
 return}elsejava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
}

static codecs;
{
   flags, data

 address = SOC15_REG_OFFSET (ncode
 data SOC15_REG_OFFSET(, ,regDIDT_IND_DATA

   codecsvcn_4_0_0_video_codecs_decode_vcn0;
  }
 WREG32
spin_unlock_irqrestoreadev-, flags)
}

static u32 soc21_get_config_memsize(struct amdgpu_device    ()
{
 return codecsvcn_4_0_0_video_codecs_decode_vcn0
}

static returnEINVAL
{
 >clock.reference_freqjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
}


voidsoc21_grbm_select amdgpu_deviceadev
       u32 me, u32 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 data SOC15_REG_OFFSET(GC , regDIDT_IND_DATA);
 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 grbm_gfx_cntl = REG_SET_FIELDgrbm_gfx_cntl,GRBM_GFX_CNTL MEID me;
 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

 REG32_SOC15, 0 , grbm_gfx_cntl
}

static bool soc21_read_disabled_bios(struct amdgpu_device(&adev-,flags
{
 /* todo */
 return false;
}

staticunsigned flags,data
 {  = SOC15_REG_OFFSET(, , regDIDT_IND_INDEX;
 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
 { SOC15_REG_ENTRY  = SOC15_REG_OFFSETGC0 regDIDT_IND_DATA);
 { SOC15_REG_ENTRY(, 0 )},
 (GC,0 regGRBM_STATUS_SE2}java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 {SOC15_REG_ENTRYGC, 0 )}java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 staticu32(structamdgpu_deviceadev
 {SOC15_REG_ENTRYSDMA1,0,regSDMA1_STATUS_REG,
 { SOC15_REG_ENTRY(
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 {SOC15_REG_ENTRYGC, , regCP_STALLED_STAT2),
 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
 returnadev-.spllreference_freq
 {java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS  u32,  pipe queueu32vmid
 {   = (grbm_gfx_cntlGRBM_GFX_CNTL , pipe
{SOC15_REG_ENTRY, 0,regCP_CPC_STALLED_STAT1
 { SOC15_REG_ENTRYGC ,regCP_CPC_STATUS,
 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
};

static uint32_t soc21_read_indexed_register( amdgpu_device  ,);
    sh_num)
{
 uint32_t

 mutex_lock return;
 if java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  amdgpu_gfx_select_se_sh,, sh_num0, 0)

 valSOC15_REG_ENTRY,0,)}java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44

 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 amdgpu_gfx_select_se_sh,0, 0, 0, 0;
 mutex_unlock(&adev->grbm_idx_mutex);
 return val;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static(,,regSDMA1_STATUS_REG)java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
          indexed se_num
          u32 sh_num(,0 ),
{
ifindexed
 return soc21_read_indexed_register, se_num, , reg_offset
 }  (,0 )},
  (eg_offset= (GC ,regGB_ADDR_CONFIG&adev-.config)
   return adev->gfxSOC15_REG_ENTRY, 0, regCP_CPC_STALLED_STAT1}java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
;
 }
}

static
       sh_num u32reg_offset u32 *value)
{
 uint32_t i;
 struct soc15_allowed_register_entry  *en;

 *value = 0;
 = 0; i <ARRAY_SIZEsoc21_allowed_read_registers; i++){
  en x_lockadev-);
  if  (se_num=0 | sh_num ! xffffffff
  continue
  java.lang.StringIndexOutOfBoundsException: Range [0, 6) out of bounds for length 0
   +en-reg_offset)java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
   continue;

  *value = (&>grbm_idx_mutex
      soc21_allowed_read_registersi].rbm_indexed,
     java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0
  return 0;
 }
return-;
}

#if 0
static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
{
 u32 i;
 int ret = 0;

 mdgpu_atombios_scratch_regs_engine_hung(adev,true

 /* disable BM */
 pci_clear_master(adev->pdev);

 amdgpu_device_cache_pci_state(adev->pdev);

 if  return (reg_offset;
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ret =amdgpu_dpm_mode1_reset);
 } else {
  dev_info(adev->       u32, u32reg_offset, u32 *alue)
  ret = soc15_allowed_register_entry  en
 }

 if (  (i  0  < RRAY_SIZEsoc21_allowed_read_registers) i+ 
 dev_err>dev, "mode1 \";
 mdgpu_device_load_pci_state>);

 /* wait for asic to come out of reset */
 for+en-))
   memsize adev->nbiofuncs->(adev;

( =xffffffff
   break;
  udelay(1);
 }

amdgpu_atombios_scratch_regs_engine_hungadevfalse);

 return ret;
}
#endif

 enum
soc21_asic_reset_method  *)
{
 if (amdgpu_reset_method == java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
      ret;
     amdgpu_reset_method == AMD_RESET_METHOD_BACO)
  return amdgpu_reset_method(adev);

 if/* disableBM/
  dev_warn(adev->dev, "Specified resetp(adev->);
  (adev-pdev

  ((adevMP1_HWIP ) java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
case(,00:
 case IP_VERSION(13, 0, 7):
 case IP_VERSION(13, 0, 10)  = amdgpu_dpm_mode1_resetadev)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
   =psp_gpu_reset);
 case IP_VERSION1,0, 4:
 case IP_VERSION(13, 0, 11):
 case IP_VERSION(14, 0,
 caseIP_VERSION4 ,1:
 case IP_VERSION(14, 0, 4):
 case IP_VERSION(14, 0, 5):
  return AMD_RESET_METHOD_MODE2;
default
  mdgpu_device_load_pci_state>pdev
   return/
  else
   return AMD_RESET_METHOD_MODE1;
}
}

static int soc21_asic_reset(structu32 = >nbio>get_memsize);
{
 int retb;

  (soc21_asic_reset_method(adev {
 case AMD_RESET_METHOD_PCI:
  dev_info(adev->dev,}
  ret = amdgpu_device_pci_reset(adev);
  break;
 caseAMD_RESET_METHOD_BACO
  dev_info ret;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  break
 case AMD_RESET_METHOD_MODE2:soc21_asic_reset_method( amdgpu_device)
  dev_info( if ( ==AMD_RESET_METHOD_MODE1
  ret= (adev;
  break;
 default:
  dev_info(adev->dev,       ==AMD_RESET_METHOD_BACO
  ret =
 reak
 }

 return ret   amdgpu_reset_method;
}

static intcase IP_VERSION(3 ,0:
{
case (1,0 0:
  returnAMD_RESET_METHOD_MODE1
}

static IP_VERSION1,0 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
{
 /* todo */return;
 return 0; if((adev)
}

static  soc21_program_aspmamdgpu_deviceadev)
{
   ;
 }

 if (static int(struct *)
  >nbio>program_aspm);
}

 struct soc21_common_ip_block {
 .type dev_info>dev PCI\)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 .major  dev_infoadev-dev " reset\";
 .inor 0
. = 0
 .funcscaseAMD_RESET_METHOD_MODE2
};

static bool soc21_need_full_reset(struct amdgpu_device *adev)
{
 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
caseIP_VERSION(1 ,0:
 case IP_VERSION(11, 0, 2):
 case IP_VERSION(11, 0, 3):
 default:
  return  = amdgpu_device_mode1_reset);
 }
}

static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
{
  }

 if (adev->flags & AMD_IS_APU)
  return false;

 returnret;
  * are already been loaded.
  */
 sol_reg = }
 if (sol_reg)
  return static int soc21_set_uvd_clocksstructamdgpu_deviceadevu32, u32dclk

 return false;
}

static void soc21_init_doorbell_index(struct amdgpu_device *adev
{
 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  voidsoc21_program_aspm amdgpu_deviceadev
 adev-
ev->doorbell_index = AMDGPU_NAVI10_DOORBELL_MEC_RING3
 adev-doorbell_index = AMDGPU_NAVI10_DOORBELL_MEC_RING4
 adev->doorbell_index (dev-.funcs-)
 adev-  >nbio>program_aspm);
 adev-
 adev->const struct amdgpu_ip_block_version soc21_common_ip_block = {
 adev->doorbell_index.userqueue_end =  type AMD_IP_BLOCK_TYPE_COMMON,
 adev-doorbell_indexgfx_ring0=AMDGPU_NAVI10_DOORBELL_GFX_RING0
 adev->doorbell_index. =AMDGPU_NAVI10_DOORBELL_GFX_RING1
 adev->doorbell_index.gfx_userqueue_start =
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 adev->doorbell_index.gfx_userqueue_endcaseIP_VERSION1 ,0:
  AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END
 adev->.mes_ring0 AMDGPU_NAVI10_DOORBELL_MES_RING0
 adev->doorbell_index.   true
 java.lang.StringIndexOutOfBoundsException: Range [13, 6) out of bounds for length 75
a>1  ;
 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH  * are already been loaded
 = AMDGPU_NAVI10_DOORBELL64_VCN0_1
a>.vcnvcn_ring2_3 AMDGPU_NAVI10_DOORBELL64_VCN2_3
 adev- true
 adev-
 adev-.vpe_ring =AMDGPU_NAVI10_DOORBELL64_VPEjava.lang.StringIndexOutOfBoundsException: Range [62, 63) out of bounds for length 62
NAVI10_DOORBELL64_FIRST_NON_CP
 adev->java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 >doorbell_index =AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT ;
 adev-.sdma_doorbell_range2
}

static void soc21_pre_asic_init(struct amdgpu_device *adev)
{
}

static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
       enter
{
 if (enter)
  >doorbell_indexuserqueue_end=AMDGPU_NAVI10_DOORBELL_USERQUEUE_END
 lse
 amdgpu_gfx_rlc_exit_safe_modeadev);

 if (adev->gfx.funcs->update_perfmon_mgcg)
  adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);

 return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END
 .read_disabled_bios= &soc21_read_disabled_bios
 .read_bios_from_rom = dev-doorbell_indexmes_ring1 =AMDGPU_NAVI10_DOORBELL_MES_RING1;
 .read_register&,
 .resetadev-doorbell_index[1  ;
 . adev->doorbell_index = ;
 .get_xclkadev->doorbell_indexvcn = ;
 .set_uvd_clocks.vcn = AMDGPU_NAVI10_DOORBELL64_VCN2_3
. = soc21_set_vce_clocks
 .get_config_memsize soc21_get_config_memsize
.nit_doorbell_index  soc21_init_doorbell_index
 .need_full_reset =&,
 .>doorbell_indexlast_non_cp AMDGPU_NAVI10_DOORBELL64_LAST_NON_CPjava.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73
. =&,
 .supports_baco = &amdgpu_dpm_is_baco_supported,
 .pre_asic_init &soc21_pre_asic_init
 .query_video_codecs = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
};

staticintsoc21_common_early_init amdgpu_ip_block)
{
 struct amdgpu_device

 adev->nbio.funcs->set_reg_remap(adev);
 adev->smc_rreg = NULL;
 adev->    ool)
 adev-
 if (enter)
 adev-pcie_rreg64 &amdgpu_device_indirect_rreg64
 adev->pcie_wreg64(adev0;
 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 adev->pciep_wreg = amdgpu_device_pcie_port_wregjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* TODO: will add them during VCN v2 implementation */
 adev->uvd_ctx_rreg  0;
 adev->uvd_ctx_wregjava.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 0

 adev-> read_disabled_bios =&soc21_read_disabled_bios
a>didt_wreg &;

.eset soc21_asic_reset

 adev->rev_id = amdgpu_device_get_rev_id(adev);
 adev-external_rev_id  0ff
switchamdgpu_ip_version, GC_HWIP0){
 . = &soc21_set_vce_clocksjava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  >cg_flagsAMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS |
#if 0

g =amdgpu_nbio_get_pcie_replay_count
#endif
   AMD_CG_SUPPORT_GFX_MGCG |
 pre_asic_initjava.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
 
  
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
 |
 > =amdgpu_device_indirect_wreg
   |
   |
a>pciep_rreg;
   dev- =;
  adev->pg_flags/* TODO: will add them during VCN v2 implementation */
 AMD_PG_SUPPORT_VCN_DPG
 AMD_PG_SUPPORT_JPEG
   AMD_PG_SUPPORT_ATHUBadev- =&;
  >didt_wreg&;
  adev->adev- = ;
  break;
c IP_VERSION1,0 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  cg_flags=
   AMD_CG_SUPPORT_GFX_CGCG  IP_VERSION10 0:
   AMD_CG_SUPPORT_GFX_CGLS |
   AMD_CG_SUPPORT_REPEATER_FGCG |
   AMD_CG_SUPPORT_VCN_MGCG |
   AMD_CG_SUPPORT_JPEG_MGCG
   AMD_CG_SUPPORT_ATHUB_MGCG AMD_CG_SUPPORT_GFX_CGLS
   #f0
    AMD_CG_SUPPORT_GFX_3D_ |
  AMD_CG_SUPPORT_GFX_3D_CGLS
  adev->pg_flags    |
    AMD_CG_SUPPORT_REPEATER_FGCG
  AMD_PG_SUPPORT_VCN_DPG
  AMD_PG_SUPPORT_JPEG
  AMD_PG_SUPPORT_ATHUB
  AMD_PG_SUPPORT_MMHUB;
  adev- AMD_CG_SUPPORT_ATHUB_MGCG |
  break;
 case IP_VERSION(11   |
  adev->cg_flagsAMD_CG_SUPPORT_IH_CG
   |
   |
  AMD_CG_SUPPORT_GFX_MGCG
   AMD_CG_SUPPORT_GFX_FGCG
   AMD_PG_SUPPORT_ATHUB
    |
 adev- =adev-> + 0; // TODO: need update
   AMD_CG_SUPPORT_MC_LS IP_VERSION(1 ,2:
   |
   AMD_CG_SUPPORT_HDP_LS    |
      |
   AMD_CG_SUPPORT_ATHUB_LS AMD_CG_SUPPORT_REPEATER_FGCG
   AMD_CG_SUPPORT_IH_CGAMD_CG_SUPPORT_VCN_MGCG
    AMD_CG_SUPPORT_JPEG_MGCG
    AMD_CG_SUPPORT_ATHUB_MGCG
  AMD_CG_SUPPORT_VCN_MGCG |
 AMD_CG_SUPPORT_JPEG_MGCG
  >pg_flags
   |
      |
   AMD_PG_SUPPORT_VCN_DPG
   AMD_PG_SUPPORT_JPEG;
  adev->external_rev_id = adev->rev_id ;
  break;
 caseIP_VERSION1,0 )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  adev-> >cg_flags
 AMD_CG_SUPPORT_JPEG_MGCG
  java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
   AMD_CG_SUPPORT_GFX_CGLSAMD_CG_SUPPORT_REPEATER_FGCG |
 AMD_CG_SUPPORT_REPEATER_FGCG java.lang.StringIndexOutOfBoundsException: Range [33, 34) out of bounds for length 33
   AMD_CG_SUPPORT_GFX_MGCG |  |
   |
   |
     |
     AMD_CG_SUPPORT_BIF_MGCG|
   AMD_PG_SUPPORT_VCN_DPG |
   AMD_PG_SUPPORT_JPEG;
  adev->external_rev_id = adev->rev_id +  AMD_CG_SUPPORT_BIF_LS
  break;
 case IP_VERSION(11, 0,adev->pg_flags=
  adev->cg_flags =
   AMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_GFX_FGCG |
   AMD_CG_SUPPORT_REPEATER_FGCG |
   AMD_CG_SUPPORT_GFX_PERF_CLK |
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS|
   AMD_CG_SUPPORT_HDP_MGCG |
   AMD_CG_SUPPORT_HDP_LS
   AMD_CG_SUPPORT_ATHUB_MGCG caseIP_VERSION1 ,3:
   AMD_CG_SUPPORT_ATHUB_LS |
   AMD_CG_SUPPORT_IH_CG |
   AMD_CG_SUPPORT_BIF_MGCG |
   AMD_CG_SUPPORT_BIF_LS |
   AMD_CG_SUPPORT_VCN_MGCG
  AMD_CG_SUPPORT_JPEG_MGCG
  adev->pg_flags =  r  x20
    case IP_VERSION 0:
  >cg_flags=
AMD_PG_SUPPORT_JPEG
 >external_rev_id >rev_id+x80
  |
 case(1 ,0:
  adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
   AMD_CG_SUPPORT_JPEG_MGCG |
   AMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS |
   AMD_CG_SUPPORT_GFX_MGCG |
   AMD_CG_SUPPORT_GFX_FGCG |
    AMD_CG_SUPPORT_ATHUB_MGCG
_CLK
   |
   AMD_CG_SUPPORT_BIF_MGCG |
   |
 AMD_CG_SUPPORT_VCN_MGCG
 AMD_CG_SUPPORT_HDP_LS java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 ;
case(1,)
   >cg_flags  java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
   AMD_CG_SUPPORT_ATHUB_LS  |
  |
 |
 ;
  AMD_CG_SUPPORT_GFX_3D_CGLS
   |
 |
   AMD_PG_SUPPORT_JPEG |
   AMD_PG_SUPPORT_GFX_PG;
  if (adev-  |
   adev->external_rev_id = 0x1;   |
 else
 adev- = >rev_idx10
  reak
 case IP_VERSION AMD_PG_SUPPORT_JPEG_DPG java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
  adev->cg_flags =
 AMD_CG_SUPPORT_GFX_CGCG
  adev->xternal_rev_id x1
   |
    >external_rev_idadev-rev_id+0;
   |
   AMD_CG_SUPPORT_GFX_PERF_CLK |
  AMD_CG_SUPPORT_GFX_3D_CGCG |
   AMD_CG_SUPPORT_GFX_3D_CGLS |
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS|
    |
   AMD_CG_SUPPORT_HDP_DS  |
   AMD_CG_SUPPORT_HDP_SD |
   AMD_CG_SUPPORT_ATHUB_MGCG |
   AMD_CG_SUPPORT_ATHUB_LS |
   AMD_CG_SUPPORT_IH_CG |
   AMD_CG_SUPPORT_BIF_MGCG |
   AMD_CG_SUPPORT_BIF_LS |
   AMD_CG_SUPPORT_VCN_MGCG |
   AMD_CG_SUPPORT_JPEG_MGCG;
  adev->pg_flags   AMD_CG_SUPPORT_GFX_PERF_CLK |
  AMD_PG_SUPPORT_GFX_PG|
   AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_VCN_DPG |
     |
 > =adev- + xc1
  break;
 case IP_VERSIONAMD_CG_SUPPORT_JPEG_MGCG
 > =AMD_CG_SUPPORT_VCN_MGCG
 AMD_CG_SUPPORT_JPEG_MGCG|
   AMD_CG_SUPPORT_GFX_CGCG;
  AMD_CG_SUPPORT_GFX_CGLS
 |
   AMD_CG_SUPPORT_GFX_FGCG |
   AMD_CG_SUPPORT_REPEATER_FGCG |
   AMD_CG_SUPPORT_GFX_PERF_CLK |
   AMD_CG_SUPPORT_GFX_3D_CGCG |
   AMD_CG_SUPPORT_GFX_3D_CGLS |
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS |
   AMD_CG_SUPPORT_HDP_LS |
  AMD_CG_SUPPORT_HDP_DS
   AMD_CG_SUPPORT_HDP_SD |
   AMD_CG_SUPPORT_ATHUB_MGCG |
   AMD_CG_SUPPORT_ATHUB_LS |
   AMD_CG_SUPPORT_IH_CG |
   AMD_CG_SUPPORT_BIF_MGCG |
    AMD_CG_SUPPORT_REPEAT |
 adev-> = MD_PG_SUPPORT_VCN_DPG
  AMD_CG_SUPPORT_GFX_3D_CGCG
  AMD_CG_SUPPORT_GFX_3D_CGLS
 AMD_PG_SUPPORT_JPEG
 AMD_PG_SUPPORT_GFX_PG
adev- =adev- + 0;
  break;
 case IP_VERSION(1 AMD_CG_SUPPORT_HDP_SD
  adev->cg_flags  AMD_CG_SUPPORT_ATHUB_LS
   AMD_CG_SUPPORT_IH_CG
   AMD_CG_SUPPORT_GFX_CGCG |
   AMD_CG_SUPPORT_GFX_CGLS |
_GFX_MGCG
   AMD_CG_SUPPORT_GFX_FGCG  AMD_PG_SUPPORT_VCN
  AMD_CG_SUPPORT_REPEATER_FGCG
   AMD_CG_SUPPORT_GFX_PERF_CLK |
   AMD_CG_SUPPORT_GFX_3D_CGCG adev-external_rev_idadev- +0;
 case IP_VERSION(1 5)java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
   AMD_CG_SUPPORT_MC_MGCG |
   AMD_CG_SUPPORT_MC_LS |
   AMD_CG_SUPPORT_HDP_LS  AMD_CG_SUPPORT_REPEATER_FGCG
   AMD_CG_SUPPORT_HDP_DS|
    |
  AMD_CG_SUPPORT_ATHUB_MGCGjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
    |
  AMD_CG_SUPPORT_IH_CG|
   AMD_CG_SUPPORT_BIF_MGCG
  ;
  adev->   |
   AMD_PG_SUPPORT_VCN |
   AMD_PG_SUPPORT_JPEG_DPG |
   AMD_PG_SUPPORT_JPEG |
    >pg_flags=AMD_PG_SUPPORT_VCN_DPG
  >external_rev_idadev- + 05;
  break;
 default:
  /* FIXME: not supported yet */>external_rev_idadev-> +0x50
 return-;
 }

 if (amdgpu_sriov_vf(adev)) {
  amdgpu_virt_init_setting(adev);
  xgpu_nv_mailbox_set_irq_funcs
 }

r 0;
}

static}
{
 struct * =ip_block->dev

 if (amdgpu_sriov_vf
 xgpu_nv_mailbox_get_irq)
  if ((adev->vcn
  !(adev java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
   amdgpu_virt_update_sriov_video_codec(adev xgpu_nv_mailbox_get_irq();
      sriov_vcn_4_0_0_video_codecs_encode_array_vcn1
 video_codecs_encode_array_vcn1),
     amdgpu_virt_update_sriov_video_codec,
         (sriov_vcn_4_0_0_video_codecs_decode_array_vcn1
  } else {
   amdgpu_virt_update_sriov_video_codec(adev,
            sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
      ARRAY_SIZE),
            sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
   (sriov_vcn_4_0_0_video_codecs_decode_array_vcn0
  }
   {
  if(>nbio &&
      adev->nbio.ras_err_event_athub_irq.funcs)
  /* don't need to fail gpu late init
 * if enabling athub_err_event interrupt failed
 * nbio v4_3 only support fatal error hanlding
 * just enable the interrupt directly */
   amdgpu_irq_get(adev,  } else {
 }

 /* Enable selfring doorbell aperture late because doorbell BAR
 * aperture will change if resize BAR successfully in gmc sw_init.
 */
 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev  amdgpu_irq_get(dev adev-nbioras_err_event_athub_irq)

 return 0;
}

static   * aperture will change if resize BAR successfully in gmc sw_init  
{
 struct java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if (amdgpu_sriov_vf(adev))
  xgpu_nv_mailbox_add_irq_idadev;

staticintsoc21_common_sw_init(struct)
}

  (  *)
{
 struct

 /* enable aspm */
 soc21_program_aspm(adev);
 /* setup nbio registers */
 adev->nbio
 /* remap HDP registers to a hole in mmio space,
 * for the purpose of expose those registers
 * to process space
 */
 if (adev->nbio.funcs->java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
   soc21_program_aspmadev
 /* enable the doorbell aperture */
 adev-.funcs-(adev true);

 return 0;
}

static /* remap HDP registers to a hole in mmio space,
{
struct amdgpu_device *adev = ip_block->adev;

/* Disable the doorbell aperture and selfring doorbell aperture
 * separately in hw_fini because soc21_enable_doorbell_aperture
 * has been removed and there is no need to delay disabling
 * selfring doorbell.
 */
 adev->nbio.funcs-
 adev->nbio.java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 if(mdgpu_sriov_vfadev) java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
  xgpu_nv_mailbox_put_irq(adev);
 } else {
  if (adev->  * has been removed and there is no need to delay  * selfring doorbell.
      adev->nbio.ras_err_event_athub_irq.funcs >nbiofuncs-(adevfalse)
   amdgpu_irq_put
 }

 return 0;
}

static int soc21_common_suspend(struct
{
 returnsoc21_common_hw_fini);
}

static bool  amdgpu_irq_put, adev-.ras_err_event_athub_irq,0;
{
 u32  return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10

 /* Will reset for the following suspend abort cases.
 * 1) Only reset dGPU side.
 * 2) S3 suspend got aborted and TOS is active.
 *    As for dGPU suspend abort cases the SOL value
 *    will be kept as zero at this resume point.
 */
 if}
  sol_reg1 = RREG32_SOC15static soc21_need_reset_on_resume *)
  msleep(1  sol_reg1sol_reg2
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  return (sol_reg1 !  * 2) S3 suspend got aborted and TOS is active  *    As for dGPU suspend abort cases the SOL value  *    will be kept as zero at this resume point.
 }

 return msleep0)java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
}

static int soc21_common_resume(struct amdgpu_ip_block  returnsol_reg1 sol_reg2)java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
{
 struct

 if int( amdgpu_ip_block)
  dev_info(adev-  *adev >java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
;
 }

 return soc21_common_hw_init(ip_block);
}

static bool }
{
 return returneturn soc21_common_hw_initip_block;
}

static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
         boolsoc21_common_is_idle amdgpu_ip_blockip_block
{
 eturn;

 switch
caseIP_VERSION4 3, )java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 case IP_VERSION( ,1:
 case IP_VERSION(7, 7, 0):
 case IP_VERSION(7, 7, 1):
 case java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 case IP_VERSION(7  IP_VERSION4 , )
 case IP_VERSION(7 case IP_VERSION,7 )java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 case IP_VERSION(7, 11,   IP_VERSION(,11 )
  adev->nbio.funcs->update_medium_grain_clock_gating(  (,1,3:
  adev-.funcs-update_medium_grain_clock_gating(adev
    state AMD_CG_STATE_GATE
     >nbio>update_medium_grain_light_sleep,
 adev-.funcs-(adev
     adev-hdp>update_clock_gating,
  break;
 default:
 break
 default:
 break;
}

static int soc21_common_set_powergating_state }
        enum amd_powergating_state state)
{
 struct amdgpu_device *adev staticint soc21_common_set_powergating_state( amdgpu_ip_block,

 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
 case IP_VERSION(  amdgpu_deviceadev>adev
 case IP_VERSION(6, 0, 2):
 adev-.funcs-(adev
    state == AMD_PG_STATE_GATEcase IP_VERSION,0 ):
  break;
 default
b;
 }

 return 0;
}

static void
{
 struct amdgpu_device *adev = ip_block->

 adev->nbio.funcs->get_clockgating_state(adev, flags);

 adev->hdp.funcs->get_clock_gating_state(adev, flags);
}

static const struct amd_ip_funcs soc21_common_ip_funcs = {
 . = "",
 .early_initjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .late_init = soc21_common_late_init,
 .sw_init=soc21_common_sw_init
 .hw_init = soc21_common_hw_init,
 .hw_fini = soc21_common_hw_fini conststruct soc21_common_ip_funcs {
 .suspend = soc21_common_suspend,
 .esumesoc21_common_resume
 .is_idle = soc21_common_is_idle,
 .set_clockgating_state = soc21_common_set_clockgating_state,
 .set_powergating_state = soc21_common_set_powergating_state =soc21_common_hw_init
 .get_clockgating_state = soc21_common_get_clockgating_state,
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2