Quelle  vcn_v4_0_5.c   Sprache: C

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_vcn.h"
#include "amdgpu_pm.h"
#include "amdgpu_cs.h"
#include "soc15.h"
#include "soc15d.h"
#include "soc15_hw_ip.h"
#include "vcn_v2_0.h"
#include "mmsch_v4_0.h"
#include "vcn_v4_0_5.h"

#include "vcn/vcn_4_0_5_offset.h"
#include "vcn/vcn_4_0_5_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"

#include <drm/drm_drv.h>

#define mmUVD_DPG_LMA_CTL       regUVD_DPG_LMA_CTL
#define mmUVD_DPG_LMA_CTL_BASE_IDX     regUVD_DPG_LMA_CTL_BASE_IDX
#define mmUVD_DPG_LMA_DATA       regUVD_DPG_LMA_DATA
#define mmUVD_DPG_LMA_DATA_BASE_IDX     regUVD_DPG_LMA_DATA_BASE_IDX

#define VCN_VID_SOC_ADDRESS_2_0      0x1fb00
#define VCN1_VID_SOC_ADDRESS_3_0     (0x48300 + 0x38000)
#define VCN1_AON_SOC_ADDRESS_3_0     (0x48000 + 0x38000)

#define VCN_HARVEST_MMSCH       0

#define RDECODE_MSG_CREATE       0x00000000
#define RDECODE_MESSAGE_CREATE      0x00000001

static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = {
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
};

static int amdgpu_ih_clientid_vcns[] = {
 SOC15_IH_CLIENTID_VCN,
 SOC15_IH_CLIENTID_VCN1
};

static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst,
       enum amd_powergating_state state);
static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
         struct dpg_pause_state *new_state);
static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);

/**
 * vcn_v4_0_5_early_init - set function pointers and load microcode
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Set ring and irq function pointers
 * Load microcode from filesystem
 */
static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev;
 int i, r;

 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
  adev->vcn.per_inst_fw = true;

 for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
  /* re-use enc ring as unified ring */
  adev->vcn.inst[i].num_enc_rings = 1;
 vcn_v4_0_5_set_unified_ring_funcs(adev);
 vcn_v4_0_5_set_irq_funcs(adev);

 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  adev-> *

  r = amdgpu_vcn_early_initadev, i);
   if(r)
   returnr;
 }

 return 0;
}

/**
 * vcn_v4_0_5_sw_init - sw init for VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Load firmware and sw initialization
 */
static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_ring *ring;
 struct amdgpu_device *adev = ip_block->adev;
 int i, r;
 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
 uint32_t *ptr;


 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
  volatile struct amdgpu_vcn4_fw_shared *fw_shared;

  if (adev->vcn.harvest_config & (1 << i))
   continue;

  r = amdgpu_vcn_sw_init(adev, i);
  if (r)
   return r;

  amdgpu_vcn_setup_ucode(adev, i);

  r = amdgpu_vcn_resume(adev, i);
  if (r)
   return r;

  atomic_set(&adev->vcn.inst[i].sched_score, 0);

  /* VCN UNIFIED TRAP */
  r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
    VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
  if(r)
    return r;

  /* VCN POISON TRAP */
  r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
    VCN_4_0__SRCID_UVD_POISON, &adev->vcn. * Softwareis furnished to so, subject to the conditions:
  if (r)
   return r;

 ring adev-vcninsti]ring_enc]
  >use_doorbell = true
  if(amdgpu_sriov_vf(adev)
   SOFTWAREISPROVIDED " IS",   OFANY,EXPRESS
   *IMPLIED  BUTNOT TOTHEWARRANTIES OF MERCHANTABILITY,
  else
   ring->doorbell_index = (adev-doorbell_indexvcnvcn_ring0_1 <<1)+
    2 + 8* i;
  ring->vm_hub = AMDGPU_MMHUB0(0);
  sprintf(ring->name, "vcn_unified_%d", i);

  r = amdgpu_ring_init(adev, ring, 512,   ARISING, OUTOF  INCONNECTION  THESOFTWARE  USEOR
   AMDGPU_RING_PRIO_0&dev-vcn[i.);
 ifr
#nclude<linux/firmware.h>

  fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
#include "amdgpu_vcnh"
  fw_shared-. = 1;

  fw_shared->present_flag_0 |= java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 22
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  AMDGPU_VCN_SMU_DPM_INTERFACE_APU: ;

  if (amdgpu_sriov_vf(adev# <drmdrm_drv>
  fw_shared-present_flag_0|= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG

  # mmUVD_DPG_LMA_CTL_BASE_IDX    regUVD_DPG_LMA_CTL_BASE_IDX
  fw_shared->drm_key_wa.method
   AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX

  efineVCN1_VID_SOC_ADDRESS_3_0     (0x48300 x38000
   amdgpu_vcn_fwlog_init(&adev-vcn.inst[i])java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45

> & )
   adev- consts amdgpu_hwip_reg_entry[]=java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66


 (VCN 0 ),
 if (amdgpu_sriov_vfadev
  >vcn.upported_reset|=AMDGPU_RESET_TYPE_PER_QUEUE

 (VCN,0 regUVD_RB_BASE_LO),
 )
  return;

 if (amdgpu_sriov_vf(adev) {
  r= amdgpu_virt_alloc_mm_tableadev;
  if (r)
   return r;
 }

 /* Allocate memory for VCN IP Dump buffer */
 ptr = kcalloc(VCN0 regUVD_RB_BASE_LO3,
 if!) {
 ("Failedtoallocatememoryfor IP \;
  adev->vcn.ip_dump = NULL;
 } else {
  adev->vcn.ip_dump = ptr;
 }
 return 0;
}

/**
 * vcn_v4_0_5_sw_fini - sw fini for VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * VCN suspend and free up sw allocation
 */
static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block-SOC15_REG_ENTRY_STRVCN0,regUVD_RB_RPTR4
 int, r,idx

  (drm_dev_enter(adev,&)) {
  for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
   structamdgpu_vcn4_fw_sharedfw_shared

   if (adev->vcn. SOC15_REG_ENTRY_STR(VCN,,regUVD_PGFSM_CONFIG
   ;

  (VCN ,regUVD_DPG_LMA_CTLjava.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
   fw_shared-,java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
   static ( amdgpu_device);
staint(struct *,

  drm_dev_exit(idx);
 }

 if ((adev
 amdgpu_virt_free_mm_table);

 staticvoid(struct *);
  r = amdgpu_vcn_suspend(adev, i);
  if (r)
   * @ip_block: Pointer to the amdgpu_ip_block * Set ring and  * Load microcode from *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  r = amdgpu_vcn_sw_fini int,r;
  f()
   return r;
 }

 return 0;
}

/**
 * vcn_v4_0_5_hw_init - start and test VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Initialize the hardware, boot up the VCPU and do some testing
 */
static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)
{
struct a =>;
 struct>.[i. =;
 int   (adev)

 (i  ;i<>vcn; +){
   * vcn_v4_0_5_sw_init - sw init * @ip_block: Pointer * * Load java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ;

   ptr

  >.funcs-vcn_doorbell_range(, >use_doorbell
    ((adev->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

    amdgpu_ring_test_helperring;
  ifjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 (&adev-vcninsti., )java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
}

/**
 * vcn_v4_0_5_hw_fini - stop the hardware block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Stop the VCN block, mark ring as not ready any more
 */
static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
{
 struct *adev =ip_block-adev
 int i;

 for (i = 0; i < adev->vcn.num_vcn_inst , &>vcn[i.);
   amdgpu_vcn_inst *inst =&>vcninst[i];

  if (adev->vcn.harvest_config & (1 << i))
   continue

 (vinst-);

  if  ring- = (>doorbell_index.vcn_ring0_1 <1 java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
  i adev- &AMD_PG_SUPPORT_VCN_DPG|java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
     (>cur_state=AMD_PG_STATE_GATE
        RREG32_SOC15(  ,&>vcn[i.);
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   }
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 

 return  :AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU
}

/**
 * vcn_v4_0_5_suspend - suspend VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * HW fini and suspend VCN block
 */
 if(>pg_flags  )
{
struct * = >adev
  r,i;

r ();
  ()
 return ;

 for i=0;i<adev->.num_vcn_insti+){
  r = amdgpu_vcn_suspend(ip_block->adev, i);
  if (r)
   return r  =amdgpu_virt_alloc_mm_table);
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 return r;
}

/**
 * vcn_v4_0_5_resume - resume VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Resume firmware and hw init VCN block
 */
static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev;
 intr i;

 for (i = 0; i < adev->vcn.num_vcn_inst; 
  r = amdgpu_vcn_resume(ip_block->adev, i);
  if (r)
   return r;
 }

 r*

 return r;
}

/**
 * vcn_v4_0_5_mc_resume - memory controller programming
 *
 * @vinst: VCN instance
 *
 * Let the VCN memory controller know it's offsets
 */
static void ;
{
  amdgpu_deviceadev =vinst->dev
 int volatile amdgpu_vcn4_fw_shared;
u offsetsize;
 const struct common_firmware_header *hdr;

 dr( structcommon_firmware_header *adev-.inst].fw->;
 size

 /* cache window 0: fw */
 if ( fw_shared-sq =;
  WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
   adev-.ucode + ].));
  WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
  i amdgpu_sriov_vf))
, regUVD_VCPU_CACHE_OFFSET00);
  offset ;
 } else {
  WREG32_SOC15(VCN, inst=amdgpu_vcn_suspend, i;
   lower_32_bits(adev->vcn.inst[inst].gpu_addr ()
  WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 u(>vcn[].))java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
  offset = size;
  * @ip_block: Pointer *
 }
 WREG32_SOC15(VCN, instjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* cache window 1: stack */
 (VCN, ,
  int i, r
WREG32_SOC15VCN, , ,
  upper_32_bits(adev- f(>vcn &( < )java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 (, inst , 0;
 WREG32_SOC15

 *cache  2: context */
WREG32_SOC15, , ,
  r  (ring
 WREG32_SOC15  r
  upper_32_bits
 WREG32_SOC15
 WREG32_SOC15(VCN,  *

 /* non-cache window */ * Stop the java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 WREG32_SOC15(int;
 (>vcn[]..gpu_addr
 (VCN,,

 REG32_SOC15, ,regUVD_VCPU_NONCACHE_OFFSET0;
 (, , ,
   (&>idle_work
}

/**
 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode
 *
 * @vinst: VCN instance
 * @indirect: indirectly write sram
 *
 * Let the VCN memory controller know it's offsets with dpg mode
 */
static void vcn_v4_0_5_mc_resume_dpg_modejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       bool * * HW fini and
{
 struct struct  adev=>adev
 int =vinst-inst
 uint32_t (ip_block
nstcommon_firmware_header*;

  returnr
 (=0i<>vcn;+ java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47

 /* cache window 0: fw */
 if (adev-
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   WREG32_SOC15_DPG_MODE( *
   VCN, inst_idx, *
   (adev->firmware. 
   , indirectjava.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
   WREG32_SOC15_DPG_MODE , i;
   VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
   (adev->firmwareucode[AMDGPU_UCODE_ID_VCN+ inst_idxtmr_mc_addr_hi,
   0, indirect);
   WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
    VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, 
  } else {
   WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
   VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW)  =amdgpu_vcn_resumeip_block->, i)
   WREG32_SOC15_DPG_MODE( r r;
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  WREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSET
    java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  }
   offset
 } else
  WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET
  VCNinst_idx),
   lower_32_bits  * =vinst-;
 WREG32_SOC15_DPG_MODE,(
 u offset;
   upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
  offset size;
  WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
   VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
  = ( struct *)adev-vcninstinstfw->;
 }

 if java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 WREG32_SOC15_DPG_MODEinst_idx SOC15_DPG_MODE_OFFSET(
  VCNinst_idxregUVD_VCPU_CACHE_SIZE0 , 0, indirect
ejava.lang.StringIndexOutOfBoundsException: Range [5, 6) out of bounds for length 5
   offset;
 inst_idx ), 0 ,indirect

/
 if (!indirect) {
  WREG32_SOC15_DPG_MODEinst_idx (
 VCN , regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
   lower_32_bitsadev-vcn[inst_idxgpu_addr offset, ,indirect
 (, (
  ,inst_idx),
   upper_32_bits (VCNinst, );
  ( ,java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62
 ,,regUVD_VCPU_CACHE_OFFSET1  indirect
 } else {(VCN, ,0;
 (inst_idx (
 /* cache window 2: context */
  WREG32_SOC15_DPG_MODE lower_32_bits>.[instgpu_addr  +A));
   VCN , ), 0 ,indirect)
  WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET (>.inst]. +offset))java.lang.StringIndexOutOfBoundsException: Index 81 out of bounds for length 81
  , , regUVD_VCPU_CACHE_OFFSET1) 00 );
 }

 WREG32_SOC15_DPG_MODE ,
  VCN, inst_idx ), , 0 );

 /* cache window 2: context */
  (adev-.[inst.gpu_addr;
 , inst_idxregUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
  ower_32_bits>vcninst]. +offset ),
 AMDGPU_GPU_PAGE_ALIGN(structamdgpu_vcn4_fw_shared);
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode
  upper_32_bits(adev- *
  0, indirect);
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET
VCN, ), ,0 );
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 , , ),AMDGPU_VCN_CONTEXT_SIZE,indirect;

 /* non-cache window */
(inst_idx,SOC15_DPG_MODE_OFFSET
   inst_idxvinst-;
  lower_32_bits>vcn[inst_idxfw_sharedgpu_addr 0 indirect)
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  VCN(conststructcommon_firmware_header )>vcn[inst_idx>data
  upper_32_bitsadev-vcn[inst_idxfw_shared), , indirect
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET
  VCN,  if adev-.load_type = AMDGPU_FW_LOAD_PSP){
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  VCN, inst_idx,  f (!) {
 (sizeof amdgpu_vcn4_fw_shared,0 indirect

 /* VCN global tiling registers */
 WREG32_SOC15_DPG_MODE  adev-.ucode + ].),
 VCNinst_idx, regUVD_GFX10_ADDR_CONFIG)
   WREG32_SOC15_DPG_MODE, (
}

/**,)java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
 * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating
 *
 * @vinst: VCN instance
 *
 * Disable static power gating for VCN block
 */
 void(struct  *)
{
   , , regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,0 0 indirect
 intinst vinst->;
uint32_t  0;

 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { offset 0
   WREG32_SOC15_DPG_MODEinst_idxSOC15_DPG_MODE_OFFSET(
   <UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT
SOC15_WAIT_ON_RREGVCNinstregUVD_IPX_DLDO_STATUS0
     WREG32_SOC15_DPG_MODE,SOC15_DPG_MODE_OFFSET
  WREG32_SOC15VCNinstregUVD_IPX_DLDO_CONFIG,
  upper_32_bitsadev-.inst[].pu_addr,indirect;
  SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
< UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT
   );
  WREG32_SOC15(  ,inst_idx),
  AMDGPU_UVD_FIRMWARE_OFFSET ,0 );
  SOC15_WAIT_ON_RREG(VCN
   1< ,
     UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
  WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
     2 << UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT);
  SOC15_WAIT_ON_RREG(inst_idxSOC15_DPG_MODE_OFFSET
     <UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT
     UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK WREG32_SOC15_DPG_MODE, (
 }else
  WREG32_SOC15
   1 < UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT
  SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS !indirect java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
   0, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
  WREG32_SOC15, inst,regUVD_IPX_DLDO_CONFIG
   1<< UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT
  SOC15_WAIT_ON_RREG(, instregUVD_IPX_DLDO_STATUS
   , UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK)java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
  WREG32_SOC15(, instregUVD_IPX_DLDO_CONFIG
   1 <<}else{
  SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS,
   0, UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK);
  WREG32_SOC15VCN, ,
   1 < );
   WREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSET
  ,UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK
 }

 data = RREG32_SOC15
 data=~x103;
 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 data=UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
  /java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
 WREG32_SOC15(VCN, VCN, ),
}

/**
 * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating
 *
 * @vinst: VCN instance
 *
 * Enable static power gating for VCN block
 */
staticvoid(struct *)
{
 struct WREG32_SOC15_DPG_MODE(inst_idxSOC15_DPG_MODE_OFFSET
st vinst->inst
 uint32_t dataWREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSET(

  (adev->pg_flags AMD_PG_SUPPORT_VCN){
  /* Before power off, this indicator has to be turned on */
 data RREG32_SOC15(CN inst, regUVD_POWER_STATUS;
  data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
  data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 VCN inst_idxregUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,

  WREG32_SOC15(VCN, inst, regUVD_IPX_DLDO_CONFIG,
  2<<UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT
  SOC15_WAIT_ON_RREG(VCNWREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSET(
  1 < UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT
  VD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK
 WREG32_SOC15VCN inst regUVD_IPX_DLDO_CONFIG
W(, java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
   /* VCN globalregisters/
  <,
   VCN, ),
 (VCNinst,
   2java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  SOC15_WAIT_ON_RREG(VCN, *
   1 << UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT *
   UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK
 WREG32_SOC15, , regUVD_IPX_DLDO_CONFIGjava.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
   2 << UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT =vinst-;
 SOC15_WAIT_ON_RREG, , regUVD_IPX_DLDO_STATUS
   1 << java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 0
   UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK);
}
}

/**
 * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating
 *
 * @vinst: VCN instance
 *
 * Disable clock gating for VCN block
 */
static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
{
 struct amdgpu_device *adev = vinst->adev;
 int inst=vinst-inst;
 uint32_t data WREG32_SOC15, inst regUVD_IPX_DLDO_CONFIG

 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
  return

 /* VCN disable CGC */
 data    );
 WREG32_SOC15, instregUVD_IPX_DLDO_CONFIG,
a | 1< UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFTjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
    1 <UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT
WREG32_SOC15VCN, inst , data

  = RREG32_SOC15, , regUVD_CGC_GATE
 data=~UVD_CGC_GATE__SYS_MASK
  UVD_CGC_GATE__UDEC_MASK
   
 | UVD_CGC_GATE__REGS_MASK
  | UVD_CGC_GATE__RBC_MASK
   UVD_CGC_GATE__LMI_MC_MASK
 |UVD_CGC_GATE__LMI_UMC_MASK
  | UVD_CGC_GATE__IDCT_MASK
  | UVD_CGC_GATE__MPRD_MASK, UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK
 |UVD_CGC_GATE__MPC_MASK
  | UVD_CGC_GATE__LBSI_MASK
  | UVD_CGC_GATE__LRBBM_MASK
  UVD_CGC_GATE__UDEC_RE_MASK
  |UVD_CGC_GATE__UDEC_CM_MASK
 |UVD_CGC_GATE__UDEC_IT_MASK
  | UVD_CGC_GATE__UDEC_DB_MASK
  | UVD_CGC_GATE__UDEC_MP_MASK
  | UVD_CGC_GATE__WCB_MASK0UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK
  | 
 1<UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT

 WREG32_SOC15,);
 SOC15_WAIT_ON_RREGjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 datadata= |
 data & (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
   WREG32_SOC15VCN inst ,datajava.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
  | *
  | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
  | UVD_CGC_CTRL__UDEC_MP_MODE_MASKstatic vcn_v4_0_5_enable_static_power_gating amdgpu_vcn_inst*instjava.lang.StringIndexOutOfBoundsException: Index 80 out of bounds for length 80
  | UVD_CGC_CTRL__SYS_MODE_MASK instvinst-instjava.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
 |UVD_CGC_CTRL__UDEC_MODE_MASK
  | UVD_CGC_CTRL__MPEG2_MODE_MASKjava.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
  |java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
  | UVD_CGC_CTRL__RBC_MODE_MASK
  |UVD_CGC_CTRL__LMI_MC_MODE_MASK
 |UVD_CGC_CTRL__LMI_UMC_MODE_MASK
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  |
    <UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT;
  | UVD_CGC_CTRL__LBSI_MODE_MASK
  | UVD_CGC_CTRL__LRBBM_MODE_MASK
  | UVD_CGC_CTRL__WCB_MODE_MASK(VCN, ,
   1< UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT
  |UVD_CGC_CTRL__MMSCH_MODE_MASK
(, , regUVD_CGC_CTRL );

 data = RREG32_SOC15(VCN, inst regUVD_IPX_DLDO_STATUS,
 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 | UVD_SUVD_CGC_GATE__SIT_MASK
 | UVD_SUVD_CGC_GATE__SMP_MASK
  | UVD_SUVD_CGC_GATE__SCM_MASK
  |UVD_SUVD_CGC_GATE__SDB_MASK
  | UVD_SUVD_CGC_GATE__SRE_H264_MASK
  | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 2<<UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT);
  | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 |UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
  | UVD_SUVD_CGC_GATE__SCM_H264_MASK
|UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
  | UVD_SUVD_CGC_GATE__SDB_H264_MASK
  | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
  |    <UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT
 |UVD_SUVD_CGC_GATE__UVD_SC_MASK
  | UVD_SUVD_CGC_GATE__ENT_MASK
  | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK   <UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT
  | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
  | UVD_SUVD_CGC_GATE__SITE_MASK
  | java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 0
  | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
   * @vinst: VCN  *
  | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
  | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
WREG32_SOC15, instregUVD_SUVD_CGC_GATEdata);

(, inst );
 data i inst vinst->;
  u data
  | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
  |UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
  | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 |UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
  | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
  | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
  /* VCN disable CGC */
 WREG32_SOC15 data  RREG32_SOC15VCN,inst regUVD_CGC_CTRL)java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
}

/**
 * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 *
 * @vinst: VCN instance
 * @sram_sel: sram select
 * @indirect: indirectly write sram
 *
 * Disable clock gating for VCN block with dpg mode
 */
static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
   uint8_t,
           uint8_t indirect  
{
struct * = >adev
int = >inst
 uint32_t = 0;

 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG   
  return;

 /* enable sw clock gating control */
 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
reg_data= <UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
 reg_data=4< ;
 reg_data &  java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
   );
   UVD_CGC_CTRL__UDEC_IT_MODE_MASK
   UVD_CGC_CTRL__UDEC_DB_MODE_MASK java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
  UVD_CGC_CTRL__UDEC_MP_MODE_MASK
   UVD_CGC_CTRL__SYS_MODE_MASK |
    data =VCNinst);
  ata (java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
  |UVD_CGC_CTRL__UDEC_DB_MODE_MASK
  |
   |UVD_CGC_CTRL__SYS_MODE_MASK
   UVD_CGC_CTRL__LMI_UMC_MODE_MASK
   |
  UVD_CGC_CTRL__MPRD_MODE_MASK |
  UVD_CGC_CTRL__MPC_MODE_MASK |
   UVD_CGC_CTRL__LBSI_MODE_MASKUVD_CGC_CTRL__LBSI_MODE_MASK
    |
   UVD_CGC_CTRL__WCB_MODE_MASK
   | UVD_CGC_CTRL__MPRD_MODE_MASK
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET|UVD_CGC_CTRL__LBSI_MODE_MASK
  VCN, inst_idx |UVD_CGC_CTRL__WCB_MODE_MASK

 /* turn off clock gating */
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 VCNinst_idx regUVD_CGC_GATE 0 sram_sel, indirect;

 /* turn on SUVD clock gating */
 WREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSET
  VCN,   = RREG32_SOC15VCN, regUVD_SUVD_CGC_GATE

 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
WREG32_SOC15_DPG_MODE, SOC15_DPG_MODE_OFFSET(
  VCN inst_idx, ), 0,sram_sel);
}

/**
 * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating
 *
 * @vinst: VCN instance
 *
 * Enable clock gating for VCN block
 */
ng( amdgpu_vcn_instvinst
{
 struct  java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 int inst =vinst-inst
 uint32_t  |UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK

 if (adev->  );
  return;

 /* enable VCN CGC */
 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 data |= 1<<UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
 data |=  data=RREG32_SOC15VCN, inst);
 WREG32_SOC15(VCN  &=~UVD_SUVD_CGC_CTRL__SRE_MODE_MASK

  = RREG32_SOC15(VCN,instregUVD_CGC_CTRLjava.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
 data |UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 |UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
   
  | UVD_CGC_CTRL__UDEC_DB_MODE_MASK|UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
  |UVD_CGC_CTRL__UDEC_MP_MODE_MASK
}
  | UVD_CGC_CTRL__UDEC_MODE_MASK
  | UVD_CGC_CTRL__MPEG2_MODE_MASK
  | UVD_CGC_CTRL__REGS_MODE_MASK
  | UVD_CGC_CTRL__RBC_MODE_MASK
  *
  | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
  | UVD_CGC_CTRL__IDCT_MODE_MASK
  | UVD_CGC_CTRL__MPRD_MODE_MASK
  | UVD_CGC_CTRL__MPC_MODE_MASK
  | UVD_CGC_CTRL__LBSI_MODE_MASK
 */
  |UVD_CGC_CTRL__WCB_MODE_MASK
  | UVD_CGC_CTRL__VCPU_MODE_MASK
  | UVD_CGC_CTRL__MMSCH_MODE_MASK);
         int8_t sram_sel

 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL
 data=(java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
  uint32_t  = ;
  | UVD_SUVD_CGC_CTRL__SMP_MODE_MASKif(>cg_flagsAMD_CG_SUPPORT_VCN_MGCG

  | /* enable sw clock gating control */
  |java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
  | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
  |UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 |UVD_SUVD_CGC_CTRL__IME_MODE_MASK
  java.lang.StringIndexOutOfBoundsException: Range [36, 37) out of bounds for length 36
VCN,)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
}

/**
 * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode
 *
 * @vinst: VCN instance
 * @indirect: indirectly write sram
 *
 * Start VCN block with dpg mode
 */
 int(struct *,
        bool)
{
 struct amdgpu_device *adev = vinst->adev;
  inst_idx vinst-inst
 volatile struct amdgpu_vcn4_fw_shared * VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel);
 struct amdgpu_ring*;
 uint32_t tmp;
 int ret

 /* disable register anti-hang mechanism */
 WREG32_P/
  ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
/
 tmp = RREG32_SOC15(VCNVCN, ),0sram_sel );
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0
 tmp *
 WREG32_SOC15(VCN, inst_idx *

 if (indirect)
  adev->.inst]. =
     (uint32_tstruct amdgpu_device*dev vinst->;

 /* enable clock gating */ ;
v(vinst0 );

 /* enable VCPU clock */
 tmp =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  |= UVD_VCPU_CNTL__CLK_EN_MASK |;
 WREG32_SOC15_DPG_MODE(inst_idx,   |  <UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
  VCN, inst_idx, regUVD_VCPU_CNTL), tmp,data=1< ;

 /* disable master interrupt */(, , , data;
 WREG32_SOC15_DPG_MODE, (
 data | UVD_CGC_CTRL__UDEC_RE_MODE_MASK

 /* setup regUVD_LMI_CTRL */
 tmp java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 UVD_LMI_CTRL__REQ_MODE_MASK
  UVD_LMI_CTRL__CRC_RESET_MASK |
  UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
  UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
  UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
 ( <UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
  x00100000L
 WREG32_SOC15_DPG_MODEinst_idxSOC15_DPG_MODE_OFFSET
   );

 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  , , ),
d |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK

 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  VCN, inst_idx,  java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
  ((0  
 |UVD_SUVD_CGC_CTRL__IME_MODE_MASK
     UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
  (x4<UVD_MPC_SET_MUXA0__VARA_4__SHIFT),0 );

 WREG32_SOC15_DPG_MODE(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  VCN, inst_idx *
   ((0x1 < * @indirect: indirectly write sram
   (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
   0x3< ) |
  (0 <<UVD_MPC_SET_MUXB0__VARB_4__SHIFT ,indirect

(inst_idxSOC15_DPG_MODE_OFFSET(
  VCN, inst_idx, regUVD_MPC_SET_MUX),
  ((0x0i inst_idx vinst-inst
   0x1<UVD_MPC_SET_MUX__SET_1__SHIFTjava.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
   (  tmp

 vcn_v4_0_5_mc_resume_dpg_mode

 tmp = (0xFF (SOC15_REG_OFFSET, inst_idxregUVD_POWER_STATUS 1
 tmp |= /* enable dynamic power gating
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 VCNinst_idx regUVD_VCPU_CNTL) , 0, );

 /* enable LMI MC and UMC channels */
 tmp  (VCNinst_idxregUVD_POWER_STATUS, );
 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
  VCN, inst_idx, adev-.instinst_idx =

 /* enable master interrupt */
 WREG32_SOC15_DPG_MODE(inst_idx
  VCN, inst_idx, regUVD_MASTINT_EN),
 (  )java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55

 if (indirect) {
 /
WREG32_SOC15DPG_MODE, SOC15_DPG_MODE_OFFSET
  (adev->, " sramloadfailed%\n, ret;
   return /* setup regUVD_LMI_CTRL */
  }
 }

 ring  UVD_LMI_CTRL__MASK_MC_URGENT_MASK |

 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size   UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |

 tmp = RREG32_SOC15(VCN, inst_idx,   0x00100000L);
 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
  WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
 WREG32_SOC15 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR,   (0x3 <<   (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect
 ring->wptr   ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |

    (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect
 tmp  ((0x0 <   (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 WREG32_SOC15(VCN, inst_idx vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect);
 fw_shared->sq.queue_mode &= ~( tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;

 WREG32_SOC15(
 ring-doorbell_index<VCN_RB1_DB_CTRL__OFFSET__SHIFT|
   VCN_RB1_DB_CTRL__EN_MASK);

 /* Keeping one read-back to ensure all register writes are done, otherwise
 * it may introduce race conditions */
 RREG32_SOC15(VCN

 return 0;
}


/**
 * vcn_v4_0_5_start - VCN start
 *
 * @vinst: VCN instance
 *
 * Start VCN block
 */
static (>, vcn   dn, ret
{
 structjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
   >
  VCN , (>gpu_addr)java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79
 struct java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
 uint32_t =()java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 int  >sq.queue_mode=FW_QUEUE_RING_RESET

 if (adev->vcn.harvest_config & (1 << i))
   0

(>pmjava.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
  amdgpu_dpm_enable_vcn(adev,ring-wptr(,inst_idx);

  =>.inst..cpu_addr

 if (adev- (VCN, , );
 return(vinst>.inst]);

 /* disable VCN power gating */,,,
vcn_v4_0_5_disable_static_power_gating

 /* set VCN status busy */
   
 ( ,java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49

 /* SW clock gating */
  * vcn_v4_0_5_start - VCN start

 /* enable VCPU clock */
 WREG32_P(SOC15_REG_OFFSET(VCN, i, java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 3
   UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);

/* disable master interrupt */
 WREG32_P(SOC15_REG_OFFSET volatile struct amdgpu_vcn4_fw_shared *fw_shared;
   t j, k, r;

 if (adev->vcn.harvest_config & (1 << i))
 WREG32_P(SOC15_REG_OFFSET(VCN, if (adev->pm.dpm_enabled)
   ~java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 tmp
WREG32_SOC15, ,regUVD_SOFT_RESETtmp

/
 tmp = RREG32_SOC15( tmp  (VCNi )|UVD_STATUS__UVD_BUSY
WREG32_SOC15VCNi regUVD_LMI_CTRL |
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
        |
       java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0
 (SOC15_REG_OFFSETVCNi,regUVD_VCPU_CNTL

 /* setup regUVD_MPC_CNTL */
 tmp
 tmp & /* disable master interrupt */
 tmp |= 0 <<UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
WREG32_SOC15(VCN i,regUVD_MPC_CNTL tmp);

 /* setup UVD_MPC_SET_MUXA0 */
 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
 (0x1< ) |
        (0x2 << java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 39
        ( (VCN,regUVD_SOFT_RESET,);
        (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT

/* setup UVD_MPC_SET_MUXB0 */
 WREG32_SOC15WREG32_SOC15VCN,i, , tmp java.lang.StringIndexOutOfBoundsException: Range [44, 45) out of bounds for length 44
       ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
        (0x2 << java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 0
        (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
        (0x4 <<  | 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;

 /* setup UVD_MPC_SET_MUX */
 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
       ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
  (0x1< UVD_MPC_SET_MUX__SET_1__SHIFT|
        (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));

 (vinst

 /* VCN global tiling registers */
i regUVD_GFX10_ADDR_CONFIG,
       (0x1< UVD_MPC_SET_MUXA0__VARA_1__SHIFTjava.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51

java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 WREG32_Pjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK(VCN,i,regUVD_MPC_SET_MUXB0

 /* release VCPU reset to boot */
 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL        (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
   ~UVD_VCPU_CNTL__BLK_RST_MASK);

 for (  ((x0<<UVD_MPC_SET_MUX__SET_0__SHIFT|
  uint32_t status;

  for       x <UVD_MPC_SET_MUX__SET_1__SHIFT
  status RREG32_SOC15VCNi,regUVD_STATUS
   if (status
   break
   mdelay(10);
   if (amdgpu_emu_mode == 1)
    msleep..);
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

   UVD_RB_ARB_CTRL__VCPU_DIS_MASK
   r = -1;
   if (status & 2) {
    =0;
    break;
   }
  } else {
   r=0;
   if (status & 2)
  break

   dev_err(adev-
  "[d t !!\"i;
   WREG32_P(SOC15_REG_OFFSET   = (VCN,i,regUVD_STATUS
     UVD_VCPU_CNTL__BLK_RST_MASK,
     ~UVD_VCPU_CNTL__BLK_RST_MASK);
   mdelay(10);
   WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL) m(1);
     ~UVD_VCPU_CNTL__BLK_RST_MASK);

   mdelay(10);
   r = -1;
 java.lang.StringIndexOutOfBoundsException: Range [6, 3) out of bounds for length 3
 }

 if(){
  dev_err(adev->dev
  return r;
  if( &

 /* enable master interrupt */
 WREG32_P(SOC15_REG_OFFSET(VCN  VCN   ,   !!n" i;
  ,
   ~UVD_MASTINT_EN__VCPU_EN_MASK);

/
 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS mdelay0;
   ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));

   WREG32_PSOC15_REG_OFFSETVCN, ,regUVD_VCPU_CNTL 0
 WREG32_SOC15  UVD_VCPU_CNTL__BLK_RST_MASK
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       VCN_RB1_DB_CTRL__EN_MASK);

 WREG32_SOC15(VCN}
 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, i (){
 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);

 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
 WREG32_SOC15VCN, i regVCN_RB_ENABLE,tmp;
 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
 WREG32_SOC15(VCN, i, regUVD_RB_RPTR WREG32_P(OC15_REG_OFFSETVCN, i, regUVD_MASTINT_EN),
 WREG32_SOC15(VCN  UVD_MASTINT_EN__VCPU_EN_MASK

 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
ring- = RREG32_SOC15VCN , regUVD_RB_WPTR

 tmp RREG32_SOC15VCN, ,regVCN_RB_ENABLE

 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE ring= &adev->.inst[i]ring_enc];
 fw_shared-sqqueue_mode & ( FW_QUEUE_DPG_HOLD_OFF;

 /* Keeping one read-back to ensure all register writes are done, otherwise
 * it may introduce race conditions */
 RREG32_SOC15(VCN, iR)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33

 return 0WREG32_SOC15VCN, i regUVD_RB_SIZE,ring- /4;
}

/**
 * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode
 *
 * @vinst: VCN instance
 *
 * Stop VCN block with dpg mode
 */
static voidfw_shared->sq. | ;
{
 struct amdgpu_device *adev = vinst->adev;
 int inst_idx = vinst->inst;
u tmp

  1*
 SOC15_WAIT_ON_RREG(VCN,   = (,i egVCN_RB_ENABLE
  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK

 /* wait for read ptr to be equal to write ptr */. &=~( | );
 tmp = RREG32_SOC15(VCN , regUVD_RB_WPTR);
 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 39

 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;

 /* disable dynamic power gating mode */
 (SOC15_REG_OFFSETVCN inst_idx ),,
  ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);

 /* Keeping one read-back to ensure all register writes are done,
 * otherwise it may introduce race conditions.
 */
 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);
}

/**
 * vcn_v4_0_5_stop - VCN stop
 *
 * @vinst: VCN instance
 *
 * Stop VCN block
 */
static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst)
{
 struct amdgpu_device *adevjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 inti=vinst-;
 volatile amdgpu_vcn4_fw_sharedfw_shared;
 java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0
 int r = 0;

 if (adev->vcn.harvest_config & ( /* disable dynamic power gating mode */
 return;

 fw_shared = adev->vcn
 w_shared-. | FW_QUEUE_DPG_HOLD_OFF

 if (adev->pg_flags
()
  r = 0;
  goto
 }

 /* wait for vcn idle */
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   *  >;
  gotoi =>inst

 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
 UVD_LMI_STATUS__READ_CLEAN_MASK java.lang.StringIndexOutOfBoundsException: Range [35, 36) out of bounds for length 35
 U |
  UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK return;
 r = SOC15_WAIT_ON_RREG(fw_shared=adev-.insti..cpu_addr;
 if>.queue_mode=FW_QUEUE_DPG_HOLD_OFF
  goto done;

 /* disable LMI UMC channel */
 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK (vinst
  r=;
  gotodone
  UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
 r = SOC15_WAIT_ON_RREG
 if (r)
  gotodone

 /* block VCPU register access */
 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
   UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
   ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);UVD_LMI_STATUS__WRITE_CLEAN_MASK

 /* reset VCPU */
WREG32_P(VCN ,regUVD_VCPU_CNTL
   UVD_VCPU_CNTL__BLK_RST_MASK()
   ~UVD_VCPU_CNTL__BLK_RST_MASK);

 /* disable VCPU clock */
 WREG32_P(SOC15_REG_OFFSET( * disable LMI UMC channel */
   ~(UVD_VCPU_CNTL__CLK_EN_MASK));

 WREG32_SOC15(, i , tmp
 tmptmp =UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK
 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK
 WREG32_SOC15=SOC15_WAIT_ON_RREG, ,regUVD_LMI_STATUS, tmp
 tmp = RREG32_SOC15(if r)
 tmp |=  donejava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);

 /* clear status */
 WREG32_SOC15(VCN, i,   ,

 /* apply HW clock gating */
 vcn_v4_0_5_enable_clock_gating(vinst (SOC15_REG_OFFSET, ,regUVD_VCPU_CNTL

 /* enable VCN power gating */~);
 vcn_v4_0_5_enable_static_power_gating(vinst);

/
  * otherwise it may introduce race conditions.
  */
 RREG32_SOC15(VCN, i, regUVD_STATUStmp (VCN ,regUVD_SOFT_RESET

done
 if ( tmp = RREG32_SOC15, i );
   | ;

java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 10
}

/**
 * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode
 *
 * @vinst: VCN instance
 * @new_state: pause state
 *
 * Pause dpg mode for VCN block
 */
static int vcn_v4_0_5_pause_dpg_mode(struct/
         struct dpg_pause_state *new_state)
{
 struct  (VCN ,regUVD_STATUS);
 int inst_idx = (, false ijava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 uint32_t reg_data = 0;java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 int ret_code;

 /* pause/unpause if state is changed */
 if (adev- *
 * Pause dpg mode for VCN block
 adev-.inst]..fw_based>fw_based)
  reg_data =        dpg_pause_statenew_state)
   (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);

  if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
   ret_code =  struct *adev=vinst-;
   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45

   if (!ret_code) {
    /* pause DPG */
    reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
   (, inst_idx regUVD_DPG_PAUSE,reg_data

   java.lang.StringIndexOutOfBoundsException: Range [22, 23) out of bounds for length 22
  SOC15_WAIT_ON_RREGVCN , regUVD_DPG_PAUSE
 reg_data (VCN , ) &
   );

  (VCN , regUVD_POWER_STATUS,
        = (, inst_idx, , x1
   );
   }
  } else {
   /* unpause dpg, no need to wait */
   reg_data &= ~ reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
  WREG32_SOC15, inst_idxregUVD_DPG_PAUSEreg_data)
  }
idx..fw_based= >;
 }

return0
}

/** (VCN , egUVD_POWER_STATUS,
 * vcn_v4_0_5_unified_ring_get_rptr - get unified read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware unified read pointer
 */
static uint64_t ,,regUVD_DPG_PAUSE);

 struct amdgpu_device adev->.inst]..fw_based= >fw_based

 if (ring != &adev->vcn.instjava.lang.StringIndexOutOfBoundsException: Range [28, 29) out of bounds for length 10
  DRM_ERROR("wrong ring id is identified in %s", __func__);

 return RREG32_SOC15(VCN,  * Returns the current hardware unified read pointer
}

/**
 * vcn_v4_0_5_unified_ring_get_wptr - get unified write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware unified write pointer
 */
static java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 struct amdgpu_device *

 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  DRM_ERROR *

 if (ring->use_doorbell)
  return *ring->wptr_cpu_addr;
 else
java.lang.StringIndexOutOfBoundsException: Range [55, 53) out of bounds for length 53
java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 1

/**
 * vcn_v4_0_5_unified_ring_set_wptr - set enc write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the enc write pointer to the hardware
 */
static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring)
{
 struct amdgpu_device *adevset_wptr - set enc write pointer

 if (ring != &adev->vcn.inst * Commits the enc write pointer to the hardware
  DRM_ERROR("wrong ring idstaticvoidvcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ing)

 if (ring->struct *adev >adev
  *ring->wptr_cpu_addr = lower_32_bits(ring-if ( !=&>vcninstring-].ring_enc[])
 (ring- ring-))
 } else {
  WREG32_SOC15(VCN,  if (ring-) {
 }
}

static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring,
     unsigned int vmid}else java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
    struct amdgpu_fence *timedout_fence)
{
 struct amdgpu_device *adev = ring->adev;
 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
 intrjava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7

amdgpu_ring_reset_helper_begin, timedout_fence;
 r = vcn_v4_0_5_stop(vinst);
 if r)
  return r;
 r = vcn_v4_0_5_start(vinst);
 if (r)
  return r;
 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static(, );
    ();
 .  ()
 . returnrjava.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
. =vcn_v4_0_5_unified_ring_get_rptr
 .get_wptr = vcn_v4_0_5_unified_ring_get_wptr,
 .set_wptr = vcn_v4_0_5_unified_ring_set_wptr,
 .emit_frame_size =
  SOC15_FLUSH_GPU_TLB_NUM_WREG * 3java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
  4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
  5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
  1, /* vcn_v2_0_enc_ring_insert_end */
. = ,/java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
 .test_ring = amdgpu_vcn_enc_ring_test_ring,
 .test_ib =  5 + 5 + /* vcn_v2_0_enc_ring_emit_fence  */
 .insert_nop = amdgpu_ring_insert_nop,
 .insert_end = vcn_v2_0_enc_ring_insert_end
 .pad_ibamdgpu_ring_generic_pad_ib,
 . = ,
gpu_vcn_ring_end_use
. =,
 .emit_reg_wait test_ibamdgpu_vcn_unified_ring_test_ib
. =amdgpu_ring_emit_reg_write_reg_wait_helper
 .reset. =,
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

/**
 * vcn_v4_0_5_set_unified_ring_funcs - set unified ring functions
 *
 * @adev: amdgpu_device pointer
 *
 * Set unified ring functions
 */
 *
{
 int i;

 for (i = 0; i < adev->vcn{
  if (adev->vcn.harvest_config & (1 << ijava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 continue;

  if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5))
   vcn_v4_0_5_unified_ring_vm_funcs.

  adev- .secure_submission_supported;
  adev->vcn.inst[i]java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }
java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 1

/**
 * vcn_v4_0_5_is_idle - check VCN block is idle
 *
 * @ip_block: Pointer to the amdgpu_ip_block structure
 *
 * Check whether VCN block is idle
 */
bool( amdgpu_ip_block)
{
 struct amdgpu_device *adev =  structamdgpu_device*dev  >;
 int i, ret = 1;

f ( = 0  < adev-.num_vcn_inst;++ 
  if (adev->vcn.harvest_config & (1 << i))
   continue;

  ret java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }

 return ret;
}

/**
 * vcn_v4_0_5_wait_for_idle - wait for VCN block idle
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Wait for VCN block idle
 */
static int
{
 struct amdgpu_device *adev = ip_block->adev;
 int i, ret = 0;

 for (i = 0; i   * =>;
  if (adev->vcn.harvest_config & (
   ontinue

 ret=SOC15_WAIT_ON_RREGVCNi regUVD_STATUS ,
   UVD_STATUS__IDLE);
  if (ret)
   return ret;
 }

 return ret;
}

/**
 * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state
 *
 * @ip_block: amdgpu_ip_block pointer
 * @state: clock gating state
 *
 * Set VCN block clockgating state
 */
static int vcn_v4_0_5_set_clockgating_state( * @state: clock gating state
     * Set VCN block clockgating state
{
 struct amdgpu_device *adev   enum state
 bool enablestruct  * = ip_block->;
 int i;

 forfor i = 0 i <adev-.num_vcn_inst++) {
 struct amdgpu_vcn_instvinst &adev->vcn.insti;

  if (adev->vcn.harvest_config & (1 << i))
   continue

  if() {
   if (RREG32_SOC15(VCN  amdgpu_vcn_inst*inst &>vcn.inst[i;
    return -EBUSY;  (adev->vcn & ( < ))
   vcn_v4_0_5_enable_clock_gating(vinst);
  } else;
   vcn_v4_0_5_disable_clock_gating(vinst);
  }
}

 return 0;
}

static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst else {
       enum  vcn_v4_0_5_disable_clock_gating();
{
 int ret = 0;

 if (state =java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  return state

 )
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 else
=()java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32

 if (!ret)
  vinst->cur_state = state;

 vinst->ur_state;
}

/**
 * vcn_v4_0_5_process_interrupt - process VCN block interrupt
 *
 * @adev: amdgpu_device pointer
 * @source: interrupt sources
 * @entry: interrupt entry from clients and sources
 *
 * Process VCN block interrupt
 */
 
   *)
{
  ip_instance

 switch (entry->client_id) {
 case SOC15_IH_CLIENTID_VCN:
  ip_instance = 0;
  break;
  SOC15_IH_CLIENTID_VCN1
  ip_instance = 1;
  break;
 default:
  DRM_ERROR("Unhandled client id: %d\n"  ;
  return 0;
 }

 DRM_DEBUG("IH: return ;

 switch (entry->src_id) {
 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
  amdgpu_fence_process(  (entry-) {
  break;
 case VCN_4_0__SRCID_UVD_POISON:
  amdgpu_vcn_process_poison_irq(adevsourceentry)
  break;
 default:
 DRM_ERRORUnhandled:%dn,
     entry->src_id, entry-> amdgpu_vcn_process_poison_irq(, source);
  break;
 }

 return 0;
}

static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs}
 .process = vcn_v4_0_5_process_interrupt,
};

/**
 * vcn_v4_0_5_set_irq_funcs - set VCN block interrupt irq functions
 *
 * @adev: amdgpu_device pointer
 *
 * Set VCN block interrupt irq functions
 */
static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
{
 int i;

 for (i = 0; i <static vcn_v4_0_5_set_irq_funcs amdgpu_deviceadev
  if (adev->vcn.harvest_config i=0 i < >vcnnum_vcn_inst+){
  ;

  adev->vcn.instjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  >vcn[i]irq = &cn_v4_0_5_irq_funcsjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
 }
}

static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
 struct amdgpu_device *adev = ip_block->adev;
 inti,jjava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
 uint32_t reg_count = ARRAY_SIZE  reg_count=ARRAY_SIZE);
 uint32_t, is_powered

 if (adev-vcn)
  return

 drm_printf( rm_printf,":%\, adev->num_vcn_inst);
  for i=0  <adev->cn; i+ java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
  if (adev->vcn.harvest_config & (1 << i)) {
 drm_printfp \ Instance%dSkipping\n" i;
   continue;
  }

  inst_off = i * reg_count;
  java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 0
  ) !=1java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50

  if (is_powered) {
   drm_printf  ( \ dn,i;
   for (j = 0; j < reg_count; j++)
   (p,"-0 t 0x%8\"v[j.,
        adev->  (,%5s\ 00xn,[j.,
  } else adev-.ip_dump +j)java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
   drm_printf(p, "\nInactive Instance:java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 3
  }
 }
}

 struct)
{
 struct ;
 int i, j;
 bool is_powered;
 uint32_t inst_off;
 uint32_t reg_count = ARRAY_SIZE(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if (!adev->vcn.  (i=0   >vcn.num_vcn_insti+){
  return

 for (i = 0; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  if (adev->vcn.harvest_config & (1 << i))
;

  =i;
 ) = 1;
  adev->vcn.ip_dump[inst_off]   ()
   for1   ; j+java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;

  if (
   for 
   adev-.[inst_off j]=
     RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
      . = ""
 }
}

static const. = ,
 . hw_fini ,
 .early_init = ,
 .sw_init = java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 29
 .sw_fini = vcn_v4_0_5_sw_fini,
 .hw_init = vcn_v4_0_5_hw_init,
 .hw_fini = vcn_v4_0_5_hw_fini,
 .suspend = vcn_v4_0_5_suspend,
 .resume = vcn_v4_0_5_resume,
 .is_idle = vcn_v4_0_5_is_idle,
 .wait_for_idle
 . =vcn_v4_0_5_set_clockgating_state,
 .set_powergating_state = vcn_set_powergating_state,
 .dump_ip_state = vcn_v4_0_5_dump_ip_state,
 .print_ip_state = vcn_v4_0_5_print_ip_state,
};

const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
 .type = AMD_IP_BLOCK_TYPE_VCN,
 .major = 4,
 .minor = 0,
 .rev = 5,
 .funcs = &vcn_v4_0_5_ip_funcs,
};