// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2015-2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE.
*/
/* GPU Processor ID base for dGPUs for which VCRAT needs to be created. * GPU processor ID are expressed with Bit[31]=1. * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs * used in the CRAT.
*/ static uint32_t gpu_processor_id_low = 0x80001000;
/* Return the next available gpu_processor_id and increment it for next GPU * @total_cu_count - Total CUs present in the GPU including ones * masked off
*/ staticinlineunsignedint get_and_inc_gpu_processor_id( unsignedint total_cu_count)
{ int current_id = gpu_processor_id_low;
/* NOTE: L1 cache information has been updated and L2/L3 * cache information has been added for Vega10 and * newer ASICs. The unit for cache_size is KiB. * In future, check & update cache details * for every new ASIC is required.
*/
/* Multiple banks of the same type are aggregated into * one. User mode doesn't care about multiple physical * memory segments. It's managed as a single virtual * heap for user mode.
*/
props = find_subtype_mem(heap_type, flags, width, dev); if (props) {
props->size_in_bytes += size_in_bytes; break;
}
props = kfd_alloc_struct(props); if (!props) return -ENOMEM;
/* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct * topology device present in the device_list
*/ staticint kfd_parse_subtype_cache(struct crat_subtype_cache *cache, struct list_head *device_list)
{ struct kfd_cache_properties *props; struct kfd_topology_device *dev;
uint32_t id;
uint32_t total_num_of_cu;
id = cache->processor_id_low;
pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
list_for_each_entry(dev, device_list, list) {
total_num_of_cu = (dev->node_props.array_count *
dev->node_props.cu_per_simd_array);
/* Cache infomration in CRAT doesn't have proximity_domain * information as it is associated with a CPU core or GPU * Compute Unit. So map the cache using CPU core Id or SIMD * (GPU) ID. * TODO: This works because currently we can safely assume that * Compute Units are parsed before caches are parsed. In * future, remove this dependency
*/ if ((id >= dev->node_props.cpu_core_id_base &&
id <= dev->node_props.cpu_core_id_base +
dev->node_props.cpu_cores_count) ||
(id >= dev->node_props.simd_id_base &&
id < dev->node_props.simd_id_base +
total_num_of_cu)) {
props = kfd_alloc_struct(props); if (!props) return -ENOMEM;
/* CPU topology is created before GPUs are detected, so CPU->GPU * links are not built at that time. If a PCIe type is discovered, it * means a GPU is detected and we are adding GPU->CPU to the topology. * At this time, also add the corresponded CPU->GPU link if GPU * is large bar. * For xGMI, we only added the link with one direction in the crat * table, add corresponded reversed direction link now.
*/ if (props && (iolink->flags & CRAT_IOLINK_FLAGS_BI_DIRECTIONAL)) {
to_dev = kfd_topology_device_by_proximity_domain_no_lock(id_to); if (!to_dev) return -ENODEV; /* same everything but the other direction */
props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL); if (!props2) return -ENOMEM;
/* kfd_parse_subtype - parse subtypes and attach it to correct topology device * present in the device_list * @sub_type_hdr - subtype section of crat_image * @device_list - list of topology devices present in this crat_image
*/ staticint kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr, struct list_head *device_list)
{ struct crat_subtype_computeunit *cu; struct crat_subtype_memory *mem; struct crat_subtype_cache *cache; struct crat_subtype_iolink *iolink; int ret = 0;
switch (sub_type_hdr->type) { case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
cu = (struct crat_subtype_computeunit *)sub_type_hdr;
ret = kfd_parse_subtype_cu(cu, device_list); break; case CRAT_SUBTYPE_MEMORY_AFFINITY:
mem = (struct crat_subtype_memory *)sub_type_hdr;
ret = kfd_parse_subtype_mem(mem, device_list); break; case CRAT_SUBTYPE_CACHE_AFFINITY:
cache = (struct crat_subtype_cache *)sub_type_hdr;
ret = kfd_parse_subtype_cache(cache, device_list); break; case CRAT_SUBTYPE_TLB_AFFINITY: /* * For now, nothing to do here
*/
pr_debug("Found TLB entry in CRAT table (not processing)\n"); break; case CRAT_SUBTYPE_CCOMPUTE_AFFINITY: /* * For now, nothing to do here
*/
pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n"); break; case CRAT_SUBTYPE_IOLINK_AFFINITY:
iolink = (struct crat_subtype_iolink *)sub_type_hdr;
ret = kfd_parse_subtype_iolink(iolink, device_list); break; default:
pr_warn("Unknown subtype %d in CRAT\n",
sub_type_hdr->type);
}
return ret;
}
/* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT * create a kfd_topology_device and add in to device_list. Also parse * CRAT subtypes and attach it to appropriate kfd_topology_device * @crat_image - input image containing CRAT * @device_list - [OUT] list of kfd_topology_device generated after * parsing crat_image * @proximity_domain - Proximity domain of the first device in the table * * Return - 0 if successful else -ve value
*/ int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
uint32_t proximity_domain)
{ struct kfd_topology_device *top_dev = NULL; struct crat_subtype_generic *sub_type_hdr;
uint16_t node_id; int ret = 0; struct crat_header *crat_table = (struct crat_header *)crat_image;
uint16_t num_nodes;
uint32_t image_len;
if (!crat_image) return -EINVAL;
if (!list_empty(device_list)) {
pr_warn("Error device list should be empty\n"); return -EINVAL;
}
staticint kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev, struct kfd_gpu_cache_info *pcache_info)
{ struct amdgpu_device *adev = kdev->adev; int i = 0;
/* TCP L1 Cache per CU */ if (adev->gfx.config.gc_tcp_size_per_cu) {
pcache_info[i].cache_size = adev->gfx.config.gc_tcp_size_per_cu;
pcache_info[i].cache_level = 1; /* Cacheline size not available in IP discovery for gc943,gc944 */
pcache_info[i].cache_line_size = 128;
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE);
pcache_info[i].num_cu_shared = 1;
i++;
} /* Scalar L1 Instruction Cache per SQC */ if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {
pcache_info[i].cache_size =
adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
pcache_info[i].cache_level = 1;
pcache_info[i].cache_line_size = 64;
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE);
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;
i++;
} /* Scalar L1 Data Cache per SQC */ if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
pcache_info[i].cache_level = 1;
pcache_info[i].cache_line_size = 64;
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE);
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;
i++;
} /* L2 Data Cache per GPU (Total Tex Cache) */ if (adev->gfx.config.gc_tcc_size) {
pcache_info[i].cache_size = adev->gfx.config.gc_tcc_size;
pcache_info[i].cache_level = 2;
pcache_info[i].cache_line_size = 128;
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE);
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
i++;
} /* L3 Data Cache per GPU */ if (adev->gmc.mall_size) {
pcache_info[i].cache_size = adev->gmc.mall_size / 1024;
pcache_info[i].cache_level = 3;
pcache_info[i].cache_line_size = 64;
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE);
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
i++;
} return i;
}
int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info)
{ int num_of_cache_types = 0; bool cache_line_size_missing = false;
switch (kdev->adev->asic_type) { case CHIP_KAVERI:
*pcache_info = kaveri_cache_info;
num_of_cache_types = ARRAY_SIZE(kaveri_cache_info); break; case CHIP_HAWAII:
*pcache_info = hawaii_cache_info;
num_of_cache_types = ARRAY_SIZE(hawaii_cache_info); break; case CHIP_CARRIZO:
*pcache_info = carrizo_cache_info;
num_of_cache_types = ARRAY_SIZE(carrizo_cache_info); break; case CHIP_TONGA:
*pcache_info = tonga_cache_info;
num_of_cache_types = ARRAY_SIZE(tonga_cache_info); break; case CHIP_FIJI:
*pcache_info = fiji_cache_info;
num_of_cache_types = ARRAY_SIZE(fiji_cache_info); break; case CHIP_POLARIS10:
*pcache_info = polaris10_cache_info;
num_of_cache_types = ARRAY_SIZE(polaris10_cache_info); break; case CHIP_POLARIS11:
*pcache_info = polaris11_cache_info;
num_of_cache_types = ARRAY_SIZE(polaris11_cache_info); break; case CHIP_POLARIS12:
*pcache_info = polaris12_cache_info;
num_of_cache_types = ARRAY_SIZE(polaris12_cache_info); break; case CHIP_VEGAM:
*pcache_info = vegam_cache_info;
num_of_cache_types = ARRAY_SIZE(vegam_cache_info); break; default: switch (KFD_GC_VERSION(kdev)) { case IP_VERSION(9, 0, 1):
*pcache_info = vega10_cache_info;
num_of_cache_types = ARRAY_SIZE(vega10_cache_info); break; case IP_VERSION(9, 2, 1):
*pcache_info = vega12_cache_info;
num_of_cache_types = ARRAY_SIZE(vega12_cache_info); break; case IP_VERSION(9, 4, 0): case IP_VERSION(9, 4, 1):
*pcache_info = vega20_cache_info;
num_of_cache_types = ARRAY_SIZE(vega20_cache_info); break; case IP_VERSION(9, 4, 2):
*pcache_info = aldebaran_cache_info;
num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info); break; case IP_VERSION(9, 4, 3): case IP_VERSION(9, 4, 4): case IP_VERSION(9, 5, 0):
num_of_cache_types =
kfd_fill_gpu_cache_info_from_gfx_config_v2(kdev->kfd,
*pcache_info); break; case IP_VERSION(9, 1, 0): case IP_VERSION(9, 2, 2):
*pcache_info = raven_cache_info;
num_of_cache_types = ARRAY_SIZE(raven_cache_info); break; case IP_VERSION(9, 3, 0):
*pcache_info = renoir_cache_info;
num_of_cache_types = ARRAY_SIZE(renoir_cache_info); break; case IP_VERSION(10, 1, 10): case IP_VERSION(10, 1, 2): case IP_VERSION(10, 1, 3): case IP_VERSION(10, 1, 4):
*pcache_info = navi10_cache_info;
num_of_cache_types = ARRAY_SIZE(navi10_cache_info); break; case IP_VERSION(10, 1, 1):
*pcache_info = navi14_cache_info;
num_of_cache_types = ARRAY_SIZE(navi14_cache_info); break; case IP_VERSION(10, 3, 0):
*pcache_info = sienna_cichlid_cache_info;
num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info); break; case IP_VERSION(10, 3, 2):
*pcache_info = navy_flounder_cache_info;
num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info); break; case IP_VERSION(10, 3, 4):
*pcache_info = dimgrey_cavefish_cache_info;
num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info); break; case IP_VERSION(10, 3, 1):
*pcache_info = vangogh_cache_info;
num_of_cache_types = ARRAY_SIZE(vangogh_cache_info); break; case IP_VERSION(10, 3, 5):
*pcache_info = beige_goby_cache_info;
num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info); break; case IP_VERSION(10, 3, 3):
*pcache_info = yellow_carp_cache_info;
num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info); break; case IP_VERSION(10, 3, 6):
*pcache_info = gc_10_3_6_cache_info;
num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info); break; case IP_VERSION(10, 3, 7):
*pcache_info = gfx1037_cache_info;
num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info); break; case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 1): case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): case IP_VERSION(11, 0, 4): case IP_VERSION(11, 5, 0): case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): /* Cacheline size not available in IP discovery for gc11. * kfd_fill_gpu_cache_info_from_gfx_config to hard code it
*/
cache_line_size_missing = true;
fallthrough; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1):
num_of_cache_types =
kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd,
cache_line_size_missing,
*pcache_info); break; default:
*pcache_info = dummy_cache_info;
num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
pr_warn("dummy cache info is used temporarily and real cache info need update later.\n"); break;
}
} return num_of_cache_types;
}
/* Memory required to create Virtual CRAT. * Since there is no easy way to predict the amount of memory required, the * following amount is allocated for GPU Virtual CRAT. This is * expected to cover all known conditions. But to be safe additional check * is put in the code to ensure we don't overwrite.
*/ #define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE)
/* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node * * @numa_node_id: CPU NUMA node id * @avail_size: Available size in the memory * @sub_type_hdr: Memory into which compute info will be filled in * * Return 0 if successful else return -ve value
*/ staticint kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size, int proximity_domain, struct crat_subtype_computeunit *sub_type_hdr)
{ conststruct cpumask *cpumask;
*avail_size -= sizeof(struct crat_subtype_computeunit); if (*avail_size < 0) return -ENOMEM;
/* Fill in subtype header data */
sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
cpumask = cpumask_of_node(numa_node_id);
/* Fill in CU data */
sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
sub_type_hdr->proximity_domain = proximity_domain;
sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id); if (sub_type_hdr->processor_id_low == -1) return -EINVAL;
/* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node * * @numa_node_id: CPU NUMA node id * @avail_size: Available size in the memory * @sub_type_hdr: Memory into which compute info will be filled in * * Return 0 if successful else return -ve value
*/ staticint kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size, int proximity_domain, struct crat_subtype_memory *sub_type_hdr)
{
uint64_t mem_in_bytes = 0;
pg_data_t *pgdat; int zone_type;
*avail_size -= sizeof(struct crat_subtype_memory); if (*avail_size < 0) return -ENOMEM;
/* Fill in subtype header data */
sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
sub_type_hdr->length = sizeof(struct crat_subtype_memory);
sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
/* Fill in Memory Subunit data */
/* Unlike si_meminfo, si_meminfo_node is not exported. So * the following lines are duplicated from si_meminfo_node * function
*/
pgdat = NODE_DATA(numa_node_id); for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
mem_in_bytes += zone_managed_pages(&pgdat->node_zones[zone_type]);
mem_in_bytes <<= PAGE_SHIFT;
/* Fill in subtype header data */
sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
/* Fill in IO link data */
sub_type_hdr->proximity_domain_from = numa_node_id;
sub_type_hdr->proximity_domain_to = nid;
sub_type_hdr->io_interface_type = link_type;
(*num_entries)++;
sub_type_hdr++;
}
return 0;
} #endif
/* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU * * @pcrat_image: Fill in VCRAT for CPU * @size: [IN] allocated size of crat_image. * [OUT] actual size of data filled in crat_image
*/ staticint kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
{ struct crat_header *crat_table = (struct crat_header *)pcrat_image; struct acpi_table_header *acpi_table;
acpi_status status; struct crat_subtype_generic *sub_type_hdr; int avail_size = *size; int numa_node_id; #ifdef CONFIG_X86_64
uint32_t entries = 0; #endif int ret = 0;
if (!pcrat_image) return -EINVAL;
/* Fill in CRAT Header. * Modify length and total_entries as subunits are added.
*/
avail_size -= sizeof(struct crat_header); if (avail_size < 0) return -ENOMEM;
for_each_online_node(numa_node_id) { if (kfd_numa_node_to_apic_id(numa_node_id) == -1) continue;
/* Fill in Subtype: Compute Unit */
ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
crat_table->num_domains,
(struct crat_subtype_computeunit *)sub_type_hdr); if (ret < 0) return ret;
crat_table->length += sub_type_hdr->length;
crat_table->total_entries++;
/* Fill in Subtype: IO Link */ #ifdef CONFIG_X86_64
ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
&entries,
(struct crat_subtype_iolink *)sub_type_hdr); if (ret < 0) return ret;
sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
sub_type_hdr->length * entries);
} #else
pr_info("IO link not available for non x86 platforms\n"); #endif
crat_table->num_domains++;
}
/* TODO: Add cache Subtype for CPU. * Currently, CPU cache information is available in function * detect_cache_attributes(cpu) defined in the file * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not * exported and to get the same information the code needs to be * duplicated.
*/
*size = crat_table->length;
pr_info("Virtual CRAT table created for CPU\n");
/* Parse all entries looking for a match. */
sub_header = (struct acpi_subtable_header *)
((unsignedlong)table_header + sizeof(struct acpi_table_srat));
subtable_len = sub_header->length;
while (((unsignedlong)sub_header) + subtable_len < table_end) { /* * If length is 0, break from this loop to avoid * infinite loop.
*/ if (subtable_len == 0) {
pr_err("SRAT invalid zero length\n"); break;
}
switch (sub_header->type) { case ACPI_SRAT_TYPE_CPU_AFFINITY:
cpu = (struct acpi_srat_cpu_affinity *)sub_header;
pxm = *((u32 *)cpu->proximity_domain_hi) << 8 |
cpu->proximity_domain_lo; if (pxm > max_pxm)
max_pxm = pxm; break; case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
gpu = (struct acpi_srat_generic_affinity *)sub_header;
bdf = *((u16 *)(&gpu->device_handle[0])) << 16 |
*((u16 *)(&gpu->device_handle[2])); if (bdf == pci_id) {
found = true;
numa_node = pxm_to_node(gpu->proximity_domain);
} break; default: break;
}
/* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU * to its NUMA node * @avail_size: Available size in the memory * @kdev - [IN] GPU device * @sub_type_hdr: Memory into which io link info will be filled in * @proximity_domain - proximity domain of the GPU node * * Return 0 if successful else return -ve value
*/ staticint kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size, struct kfd_node *kdev, struct crat_subtype_iolink *sub_type_hdr,
uint32_t proximity_domain)
{
*avail_size -= sizeof(struct crat_subtype_iolink); if (*avail_size < 0) return -ENOMEM;
/* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU * * @pcrat_image: Fill in VCRAT for GPU * @size: [IN] allocated size of crat_image. * [OUT] actual size of data filled in crat_image
*/ staticint kfd_create_vcrat_image_gpu(void *pcrat_image,
size_t *size, struct kfd_node *kdev,
uint32_t proximity_domain)
{ struct crat_header *crat_table = (struct crat_header *)pcrat_image; struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config; struct amdgpu_cu_info *cu_info = &kdev->adev->gfx.cu_info; struct crat_subtype_generic *sub_type_hdr; struct kfd_local_mem_info local_mem_info; struct kfd_topology_device *peer_dev; struct crat_subtype_computeunit *cu; int avail_size = *size;
uint32_t total_num_of_cu;
uint32_t nid = 0; int ret = 0;
if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU) return -EINVAL;
/* Fill the CRAT Header. * Modify length and total_entries as subunits are added.
*/
avail_size -= sizeof(struct crat_header);
memset(crat_table, 0, sizeof(struct crat_header));
memcpy(&crat_table->signature, CRAT_SIGNATURE, sizeof(crat_table->signature)); /* Change length as we add more subtypes*/
crat_table->length = sizeof(struct crat_header);
crat_table->num_domains = 1;
crat_table->total_entries = 0;
/* Fill in Subtype: Compute Unit * First fill in the sub type header and then sub type data
*/
avail_size -= sizeof(struct crat_subtype_computeunit);
sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
/* Fill CU subtype data */
cu = (struct crat_subtype_computeunit *)sub_type_hdr;
cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
cu->proximity_domain = proximity_domain;
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