// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014-2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. *
*/
/* check if there is over subscription * Note: the arbitration between the number of VMIDs and * hws_max_conc_proc has been done in * kgd2kfd_device_init().
*/
*over_subscription = 0;
if (node->max_proc_per_quantum > 1)
max_proc_per_quantum = node->max_proc_per_quantum;
if (process_count > max_proc_per_quantum)
*over_subscription |= OVER_SUBSCRIPTION_PROCESS_COUNT; if (compute_queue_count > get_cp_queues_num(pm->dqm))
*over_subscription |= OVER_SUBSCRIPTION_COMPUTE_QUEUE_COUNT; if (gws_queue_count > 1)
*over_subscription |= OVER_SUBSCRIPTION_GWS_QUEUE_COUNT; if (xnack_conflict && (node->adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN))
*over_subscription |= OVER_SUBSCRIPTION_XNACK_CONFLICT;
if (*over_subscription)
dev_dbg(dev, "Over subscribed runlist\n");
map_queue_size = pm->pmf->map_queues_size; /* calculate run list ib allocation size */
*rlib_size = process_count * pm->pmf->map_process_size +
queue_count * map_queue_size;
/* * Increase the allocation size in case we need a chained run list * when over subscription
*/ if (*over_subscription)
*rlib_size += pm->pmf->runlist_size;
/* Check if processes set different xnack modes */
list_for_each_entry(cur, queues, list) {
qpd = cur->qpd; if (xnack_enabled < 0) /* First process */
xnack_enabled = qpd->pqm->process->xnack_enabled; elseif (qpd->pqm->process->xnack_enabled != xnack_enabled) { /* Found a process with a different xnack mode */
xnack_conflict = 1; break;
}
}
build_runlist_ib: /* build the run list ib packet */
list_for_each_entry(cur, queues, list) {
qpd = cur->qpd; /* group processes with the same xnack mode together */ if (qpd->pqm->process->xnack_enabled != xnack_enabled) continue; /* build map process packet */ if (processes_mapped >= pm->dqm->processes_count) {
dev_dbg(dev, "Not enough space left in runlist IB\n");
pm_release_ib(pm); return -ENOMEM;
}
retval = pm->pmf->map_process(pm, &rl_buffer[rl_wptr], qpd); if (retval) return retval;
for (i = 0; i < alloc_size_bytes / sizeof(uint32_t); i++)
pr_debug("0x%2X ", rl_buffer[i]);
pr_debug("\n");
return retval;
}
int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
{ switch (dqm->dev->adev->asic_type) { case CHIP_KAVERI: case CHIP_HAWAII: /* PM4 packet structures on CIK are the same as on VI */ case CHIP_CARRIZO: case CHIP_TONGA: case CHIP_FIJI: case CHIP_POLARIS10: case CHIP_POLARIS11: case CHIP_POLARIS12: case CHIP_VEGAM:
pm->pmf = &kfd_vi_pm_funcs; break; default: if (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 2) ||
KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3) ||
KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 4) ||
KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 5, 0))
pm->pmf = &kfd_aldebaran_pm_funcs; elseif (KFD_GC_VERSION(dqm->dev) >= IP_VERSION(9, 0, 1))
pm->pmf = &kfd_v9_pm_funcs; else {
WARN(1, "Unexpected ASIC family %u",
dqm->dev->adev->asic_type); return -EINVAL;
}
}
/* pm_config_dequeue_wait_counts: Configure dequeue timer Wait Counts * by writing to CP_IQ_WAIT_TIME2 registers. * * @cmd: See emum kfd_config_dequeue_wait_counts_cmd definition * @value: Depends on the cmd. This parameter is unused for * KFD_DEQUEUE_WAIT_INIT and KFD_DEQUEUE_WAIT_RESET. For * KFD_DEQUEUE_WAIT_SET_SCH_WAVE it holds value to be set *
*/ int pm_config_dequeue_wait_counts(struct packet_manager *pm, enum kfd_config_dequeue_wait_counts_cmd cmd,
uint32_t value)
{ struct kfd_node *node = pm->dqm->dev; struct device *dev = node->adev->dev; int retval = 0;
uint32_t *buffer, size;
if (!pm->pmf->config_dequeue_wait_counts ||
!pm->pmf->config_dequeue_wait_counts_size) return 0;
/* If default value is modified, cache that in dqm->wait_times */ if (!retval && cmd == KFD_DEQUEUE_WAIT_INIT)
update_dqm_wait_times(pm->dqm);
} else {
kq_rollback_packet(pm->priv_queue);
}
}
out:
mutex_unlock(&pm->lock); return retval;
}
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