/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD *
*/
/** * Flag from driver to indicate that ABM should be disabled gradually * by slowly reversing all backlight programming and pixel compensation.
*/ #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
/** * Flag from driver to indicate that ABM should be disabled immediately * and undo all backlight programming and pixel compensation.
*/ #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
/** * Flag from driver to indicate that ABM should be disabled immediately * and keep the current backlight programming and pixel compensation.
*/ #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
/** * Flag from driver to set the current ABM pipe index or ABM operating level.
*/ #define SET_ABM_PIPE_NORMAL 1
/** * Number of ambient light levels in ABM algorithm.
*/ #define NUM_AMBI_LEVEL 5
/** * Number of operating/aggression levels in ABM algorithm.
*/ #define NUM_AGGR_LEVEL 4
/** * Number of segments in the gamma curve.
*/ #define NUM_POWER_FN_SEGS 8
/** * Number of segments in the backlight curve.
*/ #define NUM_BL_CURVE_SEGS 16
/** * Maximum number of segments in ABM ACE curve.
*/ #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64
/** * Maximum number of bins in ABM histogram.
*/ #define ABM_MAX_NUM_OF_HG_BINS 64
/* Maximum number of SubVP streams */ #define DMUB_MAX_SUBVP_STREAMS 2
/* Define max FPO streams as 4 for now. Current implementation today * only supports 1, but could be more in the future. Reduce array * size to ensure the command size remains less than 64 bytes if * adding new fields.
*/ #define DMUB_MAX_FPO_STREAMS 4
/* Define to ensure that the "common" members always appear in the same * order in different structs for back compat purposes
*/ #define COMMON_STREAM_STATIC_SUB_STATE \ struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ struct dmub_fams2_cmd_drr_stream_static_state drr;
/* Maximum number of streams on any ASIC. */ #define DMUB_MAX_STREAMS 6
/* Maximum number of planes on any ASIC. */ #define DMUB_MAX_PLANES 6
/* Maximum number of phantom planes on any ASIC */ #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)
/* Trace buffer offset for entry */ #define TRACE_BUFFER_ENTRY_OFFSET 16
/** * Maximum number of dirty rects supported by FW.
*/ #define DMUB_MAX_DIRTY_RECTS 3
/** * * PSR control version legacy
*/ #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 /** * PSR control version with multi edp support
*/ #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
/** * ABM control version legacy
*/ #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
/** * ABM control version with multi edp support
*/ #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
/** * Debug FW state offset
*/ #define DMUB_DEBUG_FW_STATE_OFFSET 0x300
union abm_flags { struct { /** * @abm_enabled: Indicates if ABM is enabled.
*/ unsignedint abm_enabled : 1;
/** * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
*/ unsignedint disable_abm_requested : 1;
/** * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
*/ unsignedint disable_abm_immediately : 1;
/** * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM * to be disabled immediately and keep gain.
*/ unsignedint disable_abm_immediate_keep_gain : 1;
/** * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
*/ unsignedint fractional_pwm : 1;
/** * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment * of user backlight level.
*/ unsignedint abm_gradual_bl_change : 1;
/** * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady
*/ unsignedint abm_new_frame : 1;
/* Flattened structure containing SOC BB parameters stored in the VBIOS * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. * This also prevents alighment issues when new parameters are added to the SoC BB. * The following parameters should be added since these values can't be obtained elsewhere: * -dml2_soc_power_management_parameters * -dml2_soc_vmin_clock_limits
*/ struct dmub_soc_bb_params {
uint32_t dram_clk_change_blackout_ns;
uint32_t dram_clk_change_read_only_ns;
uint32_t dram_clk_change_write_only_ns;
uint32_t fclk_change_blackout_ns;
uint32_t g7_ppt_blackout_ns;
uint32_t stutter_enter_plus_exit_latency_ns;
uint32_t stutter_exit_latency_ns;
uint32_t z8_stutter_enter_plus_exit_latency_ns;
uint32_t z8_stutter_exit_latency_ns;
uint32_t z8_min_idle_time_ns;
uint32_t type_b_dram_clk_change_blackout_ns;
uint32_t type_b_ppt_blackout_ns;
uint32_t vmin_limit_dispclk_khz;
uint32_t vmin_limit_dcfclk_khz;
uint32_t g7_temperature_read_blackout_ns;
}; #pragmapack(pop)
/** * Dirty rect definition.
*/ struct dmub_rect { /** * Dirty rect x offset.
*/
uint32_t x;
/** * Dirty rect y offset.
*/
uint32_t y;
/** * Dirty rect width.
*/
uint32_t width;
/** * Dirty rect height.
*/
uint32_t height;
};
/** * Flags that can be set by driver to change some PSR behaviour.
*/ union dmub_psr_debug_flags { /** * Debug flags.
*/ struct { /** * Enable visual confirm in FW.
*/
uint32_t visual_confirm : 1;
/** * Force all selective updates to bw full frame updates.
*/
uint32_t force_full_frame_update : 1;
/** * Use HW Lock Mgr object to do HW locking in FW.
*/
uint32_t use_hw_lock_mgr : 1;
/** * Use TPS3 signal when restore main link.
*/
uint32_t force_wakeup_by_tps3 : 1;
/** * Back to back flip, therefore cannot power down PHY
*/
uint32_t back_to_back_flip : 1;
/** * Union for debug flags.
*/
uint32_t u32All;
};
/** * Flags that can be set by driver to change some Replay behaviour.
*/ union replay_debug_flags { struct { /** * 0x1 (bit 0) * Enable visual confirm in FW.
*/
uint32_t visual_confirm : 1;
/** * 0x2 (bit 1) * @skip_crc: Set if need to skip CRC.
*/
uint32_t skip_crc : 1;
/** * 0x4 (bit 2) * @force_link_power_on: Force disable ALPM control
*/
uint32_t force_link_power_on : 1;
/** * 0x8 (bit 3) * @force_phy_power_on: Force phy power on
*/
uint32_t force_phy_power_on : 1;
/** * 0x200 (bit 9) * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
*/
uint32_t force_self_update_when_abm_non_steady : 1;
/** * 0x400 (bit 10) * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS * If we enter IPS2, the Visual confirm bar will change to yellow
*/
uint32_t enable_ips_visual_confirm : 1;
/** * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. * Added new debug flag to control DPCD.
*/
uint32_t incorrect_vtotal_in_static_screen : 1;
union replay_hw_flags { struct { /** * @allow_alpm_fw_standby_mode: To indicate whether the * ALPM FW standby mode is allowed
*/
uint32_t allow_alpm_fw_standby_mode : 1;
/* * @dsc_enable_status: DSC enable status in driver
*/
uint32_t dsc_enable_status : 1;
/** * @fec_enable_status: receive fec enable/disable status from driver
*/
uint32_t fec_enable_status : 1;
/* * @smu_optimizations_en: SMU power optimization. * Only when active display is Replay capable and display enters Replay. * Trigger interrupt to SMU to powerup/down.
*/
uint32_t smu_optimizations_en : 1;
/** * @phy_power_state: Indicates current phy power state
*/
uint32_t phy_power_state : 1;
/** * @link_power_state: Indicates current link power state
*/
uint32_t link_power_state : 1; /** * Use TPS3 signal when restore main link.
*/
uint32_t force_wakeup_by_tps3 : 1; /** * @is_alpm_initialized: Indicates whether ALPM is initialized
*/
uint32_t is_alpm_initialized : 1;
/* Magic value for identifying dmub_fw_meta_info */ #define DMUB_FW_META_MAGIC 0x444D5542
/* Offset from the end of the file to the dmub_fw_meta_info */ #define DMUB_FW_META_OFFSET 0x24
/** * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
*/ union dmub_fw_meta_feature_bits { struct {
uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */
uint32_t reserved : 31;
} bits; /**< status bits */
uint32_t all; /**< 32-bit access to status bits */
};
/** * struct dmub_fw_meta_info - metadata associated with fw binary * * NOTE: This should be considered a stable API. Fields should * not be repurposed or reordered. New fields should be * added instead to extend the structure. * * @magic_value: magic value identifying DMUB firmware meta info * @fw_region_size: size of the firmware state region * @trace_buffer_size: size of the tracebuffer region * @fw_version: the firmware version information * @dal_fw: 1 if the firmware is DAL * @shared_state_size: size of the shared state region in bytes * @shared_state_features: number of shared state features
*/ struct dmub_fw_meta_info {
uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
uint32_t fw_region_size; /**< size of the firmware state region */
uint32_t trace_buffer_size; /**< size of the tracebuffer region */
uint32_t fw_version; /**< the firmware version information */
uint8_t dal_fw; /**< 1 if the firmware is DAL */
uint8_t reserved[3]; /**< padding bits */
uint32_t shared_state_size; /**< size of the shared state region in bytes */
uint16_t shared_state_features; /**< number of shared state features */
uint16_t reserved2; /**< padding bytes */ union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */
};
/** * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
*/ union dmub_fw_meta { struct dmub_fw_meta_info info; /**< metadata info */
uint8_t reserved[64]; /**< padding bits */
};
/** * DMCUB scratch registers can be used to determine firmware status. * Current scratch register usage is as follows: * * SCRATCH0: FW Boot Status register * SCRATCH5: LVTMA Status Register * SCRATCH15: FW Boot Options register
*/
/** * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
*/ union dmub_fw_boot_status { struct {
uint32_t dal_fw : 1; /**< 1 if DAL FW */
uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
uint32_t restore_required : 1; /**< 1 if driver should call restore */
uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
} bits; /**< status bits */
uint32_t all; /**< 32-bit access to status bits */
};
/** * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
*/ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
};
/* Register bit definition for SCRATCH5 */ union dmub_lvtma_status { struct {
uint32_t psp_ok : 1;
uint32_t edp_on : 1;
uint32_t reserved : 30;
} bits;
uint32_t all;
};
enum dmub_ips_comand_type { /** * Start/stop IPS residency measurements for a given IPS mode
*/
DMUB_CMD__IPS_RESIDENCY_CNTL = 0, /** * Query IPS residency information for a given IPS mode
*/
DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1,
};
/** * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
*/ union dmub_fw_boot_options { struct {
uint32_t pemu_env : 1; /**< 1 if PEMU */
uint32_t fpga_env : 1; /**< 1 if FPGA */
uint32_t optimized_init : 1; /**< 1 if optimized init */
uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
uint32_t z10_disable: 1; /**< 1 to disable z10 */
uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ /**< 1 if all root clock gating is enabled and low power memory is enabled*/
uint32_t power_optimization: 1;
uint32_t diag_env: 1; /* 1 if diagnostic environment */
uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
uint32_t usb4_cm_version: 1; /**< 1 CM support */
uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/
uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
uint32_t ips_disable: 3; /* options to disable ips support*/
uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */
uint32_t reserved : 6; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
};
/** * Shared firmware state between driver and firmware for lockless communication * in situations where the inbox/outbox may be unavailable. * * Each structure *must* be at most 256-bytes in size. The layout allocation is * described below: * * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...
*/
/** * enum dmub_shared_state_feature_id - List of shared state features.
*/ enum dmub_shared_state_feature_id {
DMUB_SHARED_SHARE_FEATURE__INVALID = 0,
DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,
DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,
DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3,
DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */
};
/** * struct dmub_shared_state_ips_fw - Firmware signals for IPS.
*/ union dmub_shared_state_ips_fw_signals { struct {
uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */
uint32_t ips2_commit : 1; /**< 1 if in IPS2 */
uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */
uint32_t detection_required : 1; /**< 1 if detection is required */
uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */
uint32_t reserved_bits : 27; /**< Reversed */
} bits;
uint32_t all;
};
/** * struct dmub_shared_state_ips_signals - Firmware signals for IPS.
*/ union dmub_shared_state_ips_driver_signals { struct {
uint32_t allow_pg : 1; /**< 1 if PG is allowed */
uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */
uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */
uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */
uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */
uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */
uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */
uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */
uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */
uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */
uint32_t reserved_bits : 22; /**< Reversed bits */
} bits;
uint32_t all;
};
/** * IPS FW Version
*/ #define DMUB_SHARED_STATE__IPS_FW_VERSION 1
/** * struct dmub_shared_state_ips_fw - Firmware state for IPS.
*/ struct dmub_shared_state_ips_fw { union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */
uint32_t rcg_entry_count; /**< Entry counter for RCG */
uint32_t rcg_exit_count; /**< Exit counter for RCG */
uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */
uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */
uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */
}; /* 248-bytes, fixed */
/** * IPS Driver Version
*/ #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1
/** * struct dmub_shared_state_ips_driver - Driver state for IPS.
*/ struct dmub_shared_state_ips_driver { union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */
uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */
}; /* 248-bytes, fixed */
/** * union dmub_gpint_data_register - Format for sending a command via the GPINT.
*/ union dmub_gpint_data_register { struct {
uint32_t param : 16; /**< 16-bit parameter */
uint32_t command_code : 12; /**< GPINT command */
uint32_t status : 4; /**< Command status bit */
} bits; /**< GPINT bit access */
uint32_t all; /**< GPINT 32-bit access */
};
/* * enum dmub_gpint_command - GPINT command to DMCUB FW * * Command IDs should be treated as stable ABI. * Do not reuse or modify IDs.
*/ enum dmub_gpint_command { /** * Invalid command, ignored.
*/
DMUB_GPINT__INVALID_COMMAND = 0, /** * DESC: Queries the firmware version. * RETURN: Firmware version.
*/
DMUB_GPINT__GET_FW_VERSION = 1, /** * DESC: Halts the firmware. * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
*/
DMUB_GPINT__STOP_FW = 2, /** * DESC: Get PSR state from FW. * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
*/
DMUB_GPINT__GET_PSR_STATE = 7, /** * DESC: Notifies DMCUB of the currently active streams. * ARGS: Stream mask, 1 bit per active stream index.
*/
DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, /** * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. * ARGS: We can measure residency from various points. The argument will specify the residency mode. * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. * RETURN: PSR residency in milli-percent.
*/
DMUB_GPINT__PSR_RESIDENCY = 9,
/** * DESC: Notifies DMCUB detection is done so detection required can be cleared.
*/
DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
/** * DESC: Get REPLAY state from FW. * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
*/
DMUB_GPINT__GET_REPLAY_STATE = 13,
/** * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. * ARGS: We can measure residency from various points. The argument will specify the residency mode. * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. * RETURN: REPLAY residency in milli-percent.
*/
DMUB_GPINT__REPLAY_RESIDENCY = 14,
/** * DESC: Copy bounding box to the host. * ARGS: Version of bounding box to copy * RETURN: Result of copying bounding box
*/
DMUB_GPINT__BB_COPY = 96,
/** * DESC: Updates the host addresses bit48~bit63 for bounding box. * ARGS: The word3 for the 64 bit address
*/
DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
/** * DESC: Updates the host addresses bit32~bit47 for bounding box. * ARGS: The word2 for the 64 bit address
*/
DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
/** * DESC: Updates the host addresses bit16~bit31 for bounding box. * ARGS: The word1 for the 64 bit address
*/
DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
/** * DESC: Updates the host addresses bit0~bit15 for bounding box. * ARGS: The word0 for the 64 bit address
*/
DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
/** * DESC: Updates the trace buffer lower 32-bit mask. * ARGS: The new mask * RETURN: Lower 32-bit mask.
*/
DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
/** * DESC: Updates the trace buffer mask bit0~bit15. * ARGS: The new mask * RETURN: Lower 32-bit mask.
*/
DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
/** * DESC: Updates the trace buffer mask bit16~bit31. * ARGS: The new mask * RETURN: Lower 32-bit mask.
*/
DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
/** * DESC: Updates the trace buffer mask bit32~bit47. * ARGS: The new mask * RETURN: Lower 32-bit mask.
*/
DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
/** * DESC: Updates the trace buffer mask bit48~bit63. * ARGS: The new mask * RETURN: Lower 32-bit mask.
*/
DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
/* * enum dmub_cmd_type - DMUB inbox command. * * Command IDs should be treated as stable ABI. * Do not reuse or modify IDs.
*/ enum dmub_cmd_type { /** * Invalid command.
*/
DMUB_CMD__NULL = 0, /** * Read modify write register sequence offload.
*/
DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, /** * Field update register sequence offload.
*/
DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, /** * Burst write sequence offload.
*/
DMUB_CMD__REG_SEQ_BURST_WRITE = 3, /** * Reg wait sequence offload.
*/
DMUB_CMD__REG_REG_WAIT = 4, /** * Workaround to avoid HUBP underflow during NV12 playback.
*/
DMUB_CMD__PLAT_54186_WA = 5, /** * Command type used to query FW feature caps.
*/
DMUB_CMD__QUERY_FEATURE_CAPS = 6, /** * Command type used to get visual confirm color.
*/
DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, /** * Command type used for all PSR commands.
*/
DMUB_CMD__PSR = 64, /** * Command type used for all MALL commands.
*/
DMUB_CMD__MALL = 65, /** * Command type used for all ABM commands.
*/
DMUB_CMD__ABM = 66, /** * Command type used to update dirty rects in FW.
*/
DMUB_CMD__UPDATE_DIRTY_RECT = 67, /** * Command type used to update cursor info in FW.
*/
DMUB_CMD__UPDATE_CURSOR_INFO = 68, /** * Command type used for HW locking in FW.
*/
DMUB_CMD__HW_LOCK = 69, /** * Command type used to access DP AUX.
*/
DMUB_CMD__DP_AUX_ACCESS = 70, /** * Command type used for OUTBOX1 notification enable
*/
DMUB_CMD__OUTBOX1_ENABLE = 71,
/** * Command type used for all idle optimization commands.
*/
DMUB_CMD__IDLE_OPT = 72, /** * Command type used for all clock manager commands.
*/
DMUB_CMD__CLK_MGR = 73, /** * Command type used for all panel control commands.
*/
DMUB_CMD__PANEL_CNTL = 74,
/** * Command type used for all CAB commands.
*/
DMUB_CMD__CAB_FOR_SS = 75,
DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
/** * Command type used for interfacing with DPIA.
*/
DMUB_CMD__DPIA = 77, /** * Command type used for EDID CEA parsing
*/
DMUB_CMD__EDID_CEA = 79, /** * Command type used for getting usbc cable ID
*/
DMUB_CMD_GET_USBC_CABLE_ID = 81, /** * Command type used to query HPD state.
*/
DMUB_CMD__QUERY_HPD_STATE = 82, /** * Command type used for all VBIOS interface commands.
*/ /** * Command type used for all REPLAY commands.
*/
DMUB_CMD__REPLAY = 83,
/** * Command type used for all SECURE_DISPLAY commands.
*/
DMUB_CMD__SECURE_DISPLAY = 85,
/** * Command type used to set DPIA HPD interrupt state
*/
DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
/** * Command type used for all PSP commands.
*/
DMUB_CMD__PSP = 88,
/** * Command type used for all Fused IO commands.
*/
DMUB_CMD__FUSED_IO = 89,
/** * Command type used for all LSDMA commands.
*/
DMUB_CMD__LSDMA = 90,
/** * Command type use for all IPS commands.
*/
DMUB_CMD__IPS = 91,
DMUB_CMD__VBIOS = 128,
};
/** * enum dmub_out_cmd_type - DMUB outbox commands.
*/ enum dmub_out_cmd_type { /** * Invalid outbox command, ignored.
*/
DMUB_OUT_CMD__NULL = 0, /** * Command type used for DP AUX Reply data notification
*/
DMUB_OUT_CMD__DP_AUX_REPLY = 1, /** * Command type used for DP HPD event notification
*/
DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, /** * Command type used for SET_CONFIG Reply notification
*/
DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, /** * Command type used for USB4 DPIA notification
*/
DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, /** * Command type used for HPD redetect notification
*/
DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, /** * Command type used for Fused IO notification
*/
DMUB_OUT_CMD__FUSED_IO = 7,
};
/* DMUB_CMD__DPIA command sub-types. */ enum dmub_cmd_dpia_type {
DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST
DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,
DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4,
};
/** * struct dmub_cmd_header - Common command header fields.
*/ struct dmub_cmd_header { unsignedint type : 8; /**< command type */ unsignedint sub_type : 8; /**< command sub type */ unsignedint ret_status : 1; /**< 1 if returned data, 0 otherwise */ unsignedint multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ unsignedint is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ unsignedint reserved0 : 5; /**< reserved bits */ unsignedint payload_bytes : 6; /* payload excluding header - up to 60 bytes */ unsignedint reserved1 : 2; /**< reserved bits */
};
/* * struct dmub_cmd_read_modify_write_sequence - Read modify write * * 60 payload bytes can hold up to 5 sets of read modify writes, * each take 3 dwords. * * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) * * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
*/ struct dmub_cmd_read_modify_write_sequence {
uint32_t addr; /**< register address */
uint32_t modify_mask; /**< modify mask */
uint32_t modify_value; /**< modify value */
};
/** * Maximum number of ops in read modify write sequence.
*/ #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
/* * Update a register with specified masks and values sequeunce * * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword * * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) * * * USE CASE: * 1. auto-increment register where additional read would update pointer and produce wrong result * 2. toggle a bit without read in the middle
*/
struct dmub_cmd_reg_field_update_sequence {
uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
uint32_t modify_value; /**< value to update with */
};
/** * Maximum number of ops in field update sequence.
*/ #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
/** * Maximum number of burst write values.
*/ #define DMUB_BURST_WRITE_VALUES__MAX 14
/* * struct dmub_rb_cmd_burst_write - Burst write * * support use case such as writing out LUTs. * * 60 payload bytes can hold up to 14 values to write to given address * * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
*/ struct dmub_rb_cmd_burst_write { struct dmub_cmd_header header; /**< command header */
uint32_t addr; /**< register start address */ /** * Burst write register values.
*/
uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
};
/** * enum dmub_cmd_cab_type - CAB command data.
*/ enum dmub_cmd_cab_type { /** * No idle optimizations (i.e. no CAB)
*/
DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, /** * No DCN requests for memory
*/
DMUB_CMD__CAB_NO_DCN_REQ = 1, /** * Fit surfaces in CAB (i.e. CAB enable)
*/
DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, /** * Do not fit surfaces in CAB (i.e. no CAB)
*/
DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
};
/** * struct dmub_rb_cmd_cab - CAB command data.
*/ struct dmub_rb_cmd_cab_for_ss { struct dmub_cmd_header header;
uint8_t cab_alloc_ways; /* total number of ways */
uint8_t debug_bits; /* debug bits */
};
/** * Enum for indicating which MCLK switch mode per pipe
*/ enum mclk_switch_mode {
NONE = 0,
FPO = 1,
SUBVP = 2,
VBLANK = 3,
};
/* Per pipe struct which stores the MCLK switch mode * data to be sent to DMUB. * Named "v2" for now -- once FPO and SUBVP are fully merged * the type name can be updated
*/ struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { union { struct {
uint32_t pix_clk_100hz;
uint16_t main_vblank_start;
uint16_t main_vblank_end;
uint16_t mall_region_lines;
uint16_t prefetch_lines;
uint16_t prefetch_to_mall_start_lines;
uint16_t processing_delay_lines;
uint16_t htotal; // required to calculate line time for multi-display cases
uint16_t vtotal;
uint8_t main_pipe_index;
uint8_t phantom_pipe_index; /* Since the microschedule is calculated in terms of OTG lines, * include any scaling factors to make sure when we get accurate * conversion when programming MALL_START_LINE (which is in terms * of HUBP lines). If 4K is being downscaled to 1080p, scale factor * is 1/2 (numerator = 1, denominator = 2).
*/
uint8_t scale_factor_numerator;
uint8_t scale_factor_denominator;
uint8_t is_drr;
uint8_t main_split_pipe_index;
uint8_t phantom_split_pipe_index;
} subvp_data;
struct {
uint32_t pix_clk_100hz;
uint16_t vblank_start;
uint16_t vblank_end;
uint16_t vstartup_start;
uint16_t vtotal;
uint16_t htotal;
uint8_t vblank_pipe_index;
uint8_t padding[1]; struct {
uint8_t drr_in_use;
uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
uint8_t use_ramping; // Use ramping or not
uint8_t drr_vblank_start_margin;
} drr_info; // DRR considered as part of SubVP + VBLANK case
} vblank_data;
} pipe_config;
/* - subvp_data in the union (pipe_config) takes up 27 bytes. * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
*/
uint8_t mode; // enum mclk_switch_mode
};
/** * Config data for Sub-VP and FPO * Named "v2" for now -- once FPO and SUBVP are fully merged * the type name can be updated
*/ struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
uint16_t watermark_a_cache;
uint8_t vertical_int_margin_us;
uint8_t pstate_allow_width_us; struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
};
/** * DMUB rb command definition for Sub-VP and FPO * Named "v2" for now -- once FPO and SUBVP are fully merged * the type name can be updated
*/ struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { struct dmub_cmd_header header; struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
};
union dmub_fams2_cmd_stream_static_sub_state {
COMMON_STREAM_STATIC_SUB_STATE
}; //v1
union dmub_fams2_stream_static_sub_state_v2 {
COMMON_STREAM_STATIC_SUB_STATE
}; //v2
struct dmub_fams2_stream_static_state { enum fams2_stream_type type;
uint32_t otg_vline_time_ns;
uint32_t otg_vline_time_ticks;
uint16_t htotal;
uint16_t vtotal; // nominal vtotal
uint16_t vblank_start;
uint16_t vblank_end;
uint16_t max_vtotal;
uint16_t allow_start_otg_vline;
uint16_t allow_end_otg_vline;
uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline union { struct {
uint8_t is_drr: 1; // stream is DRR enabled
uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal
uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank
} bits;
uint8_t all;
} config;
uint8_t otg_inst;
uint8_t pipe_mask; // pipe mask for the whole config
uint8_t num_planes;
uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; union dmub_fams2_stream_static_sub_state sub_state;
}; //v0
struct dmub_fams2_cmd_stream_static_base_state { enum fams2_stream_type type;
uint32_t otg_vline_time_ns;
uint32_t otg_vline_time_ticks;
uint16_t htotal;
uint16_t vtotal; // nominal vtotal
uint16_t vblank_start;
uint16_t vblank_end;
uint16_t max_vtotal;
uint16_t allow_start_otg_vline;
uint16_t allow_end_otg_vline;
uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
uint16_t contention_delay_otg_vlines; // time to budget for contention on execution
uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline union { struct {
uint8_t is_drr : 1; // stream is DRR enabled
uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
} bits;
uint8_t all;
} config;
uint8_t otg_inst;
uint8_t pipe_mask; // pipe mask for the whole config
uint8_t num_planes;
uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
}; //v1
struct dmub_cmd_fams2_global_config {
uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
uint32_t lock_wait_time_us; // time to forecast acquisition of lock
uint32_t num_streams; union dmub_fams2_global_feature_config features;
uint32_t recovery_timeout_us;
uint32_t hwfq_flip_programming_delay_us;
};
union dmub_cmd_fams2_config { struct dmub_cmd_fams2_global_config global; struct dmub_fams2_stream_static_state stream; //v0 union { struct dmub_fams2_cmd_stream_static_base_state base; union dmub_fams2_cmd_stream_static_sub_state sub_state;
} stream_v1; //v1
};
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.
