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/*
 * BIF_5_1 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */


 * AN * CONNECTION WITH java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define

#define mmMM_INDEX                                                              0x0
mmMM_INDEX_HI0x6
mmMM_DATA0x1
#efinemmBIF_MM_INDACCESS_CNTL0java.lang.StringIndexOutOfBoundsException: Range [86, 87) out of bounds for length 86
#define mmBUS_CNTL                                                              0x1508
#define mmCONFIG_CNTL                                                           0x1509
#efine                                                         
#define mmCONFIG_F0_BASE                                                        define                                                      
#define mmCONFIG_APER_SIZE#define mmBX_RESET_EN                                                                                                                  
#define mmCONFIG_REG_APER_SIZE                                                  0x150d                                                          define                                                        
#define mmBIF_SCRATCH0                                                          0x151e
#define mmBIF_SCRATCH1                                          
#define mmBX_RESET_EN                                                                                                                  
#define mmMM_CFGREGS_CNTL                                                       
#define mmHW_DEBUG                                                              0x14c4
#define mmMASTER_CREDIT_CNTL                                                    0x1516                                                      
define                                                 
#define mmBX_RESET_CNTL                                                         0x152c
define                                                        
#define mmINTERRUPT_CNTL2                                                       0x151b
##define                                                    
#define mmBIF_DEBUG_MUX                                                                                                            
#define                                                        
#define mmHDP_REG_COHERENCY_FLUSH_CNTL                                                     
#define mmHDP_MEM_COHERENCY_FLUSH_CNTL                                                                                              0x14f0
#define mmCLKREQB_PAD_CNTL                                                      
mmSMBDAT_PAD_CNTL                                                       
#define mmSMBCLK_PAD_CNTL                                                       0x1523
#define mmBIF_XDMA_LO                                                           0x14c0                                                     
mmBIF_XDMA_HI0x14c1
#define mmBIF_FEATURES_CONTROL_MISC                                             0x14c2
#define mmBIF_DOORBELL_CNTL                                                     0x14c3
#define mmBIF_SLVARB_MODE                                                       0x14c4
#definemmBIF_FB_EN0x1524
#define mmBIF_BUSNUM_CNTL1                                                      0x1525
#define mmBIF_BUSNUM_LIST0                                                      0x1526
#define mmBIF_BUSNUM_LIST1                                                      0x1527
#define mmBIF_BUSNUM_CNTL2                                                      0x152b
define                                                   
#define mmBIF_PERFMON_CNTL                                                      0x152c
#define mmBIF_PERFCOUNTER0_RESULT                                               0x152d
#define mmBIF_PERFCOUNTER1_RESULT0x152e
#define mmSLAVE_HANG_PROTECTION_CNTL                                            0x1536
#define mmGPU_HDP_FLUSH_REQ                                                     0x1537
#define mmGPU_HDP_FLUSH_DONE                                                    0x1538
#definedefine                                                 
#define mmCAPTURE_HOST_BUSNUM                                                   0x153c
#define mmHOST_BUSNUM                                                           0x153d
#define mmPEER_REG_RANGE0                                                       0x153e
#define mmPEER_REG_RANGE1                                                       0x153f
#define mmPEER0_FB_OFFSET_HI                                                    define                                                 
#define mmPEER0_FB_OFFSET_LO                                                    0x14f2
#definemmPEER1_FB_OFFSET_HI0x14f1
#define mmPEER1_FB_OFFSET_LO                                                    0x14f0
#define mmPEER2_FB_OFFSET_HI mmBIF_VDDGFX_RSV1_LOWER                                                 
#define mmPEER2_FB_OFFSET_LO                                                    x14ee
#define mmPEER3_FB_OFFSET_HI                                                    0x14ed
#define mmPEER3_FB_OFFSET_LO                                                    0x14ec
#define mmDBG_BYPASS_SRBM_ACCESS                                                0x14eb
#define mmSMBUS_BACO_DUMMY                                                      0x14c6
#define mmBIF_DEVFUNCNUM_LIST0                                                  0x14e8
#definemmBIF_DEVFUNCNUM_LIST10x14e7
#define mmBACO_CNTL                                                             0x14e5
#define mmBIF_VDDGFX_RSV2_UPPER                                                 
#define mmMEM_TYPE_CNTL                                                         0x14e4
#define mmBIF_BACO_DEBUG                                                        0x14df
#define mmBIF_BACO_DEBUG_LATCH                                                  0x14dc
mmBACO_CNTL_MISC                                                        
#define mmSMU_BIF_VDDGFX_PWR_STATUS                                             0x14f8
#mmBIF_VDDGFX_GFX0_LOWER0x1428
#define mmBIF_VDDGFX_GFX0_UPPER                                                 0x1429
#define mmBIF_VDDGFX_GFX1_LOWER                                                 0x142a
definemmBIF_VDDGFX_GFX1_UPPER                                                 
#define mmBIF_VDDGFX_GFX2_LOWER                                                 0x142c
#define mmBIF_VDDGFX_GFX2_UPPER                                                 0x142d
#definemmBIF_VDDGFX_GFX3_LOWER0x142e
#define mmBIF_VDDGFX_GFX3_UPPER                                                 0x142f
#define mmBIF_VDDGFX_GFX4_LOWER                                                 0x1430
#define mmBIF_VDDGFX_GFX4_UPPER0x1431
#define mmBIF_VDDGFX_GFX5_LOWER                                                 0x1432
#define mmBIF_VDDGFX_GFX5_UPPER                                                 0x1433                                                      
define                                                 
#define mmBIF_VDDGFX_RSV1_UPPER                                                 0x1435
#define mmBIF_VDDGFX_RSV2_LOWER                                                 0x1436
#define mmBIF_VDDGFX_RSV2_UPPER0x1437
#define mmBIF_VDDGFX_RSV3_LOWER                                                 0x1438
#define mmBIF_VDDGFX_RSV3_UPPER                                                 0x1439
#define                                             
#define mmBIF_VDDGFX_RSV4_UPPER                                             
#define mmBIF_VDDGFX_FB_CMP                                                                                                    
#                                               
#define #define mmGARLIC_FLUSH_ADDR_END_5010java.lang.StringIndexOutOfBoundsException: Index 86 out of bounds for length 86
#define mmBIF_DOORBELL_GBLAPER2_LOWERmmGARLIC_FLUSH_REQ0x1412
#define mmBIF_DOORBELL_GBLAPER2_UPPER                                                   
mmBIF_SMU_INDEX0x143d
#define mmBIF_SMU_DATA                                                          0x143e
#define mmIMPCTL_RESET                                               
#define mmGARLIC_FLUSH_CNTL                                         
#define mmGARLIC_FLUSH_ADDR_START_0                                          
#definemmGARLIC_FLUSH_ADDR_START_10java.lang.StringIndexOutOfBoundsException: Index 86 out of bounds for length 86
#define mmGARLIC_FLUSH_ADDR_START_2                                             define                                          0
#define mmGARLIC_FLUSH_ADDR_START_3                                             0x1408
#define mmGARLIC_FLUSH_ADDR_START_4                                             x140a
#define mmGARLIC_FLUSH_ADDR_START_50x140c
#define mmGARLIC_FLUSH_ADDR_START_6                                             0x140e
#define mmGARLIC_FLUSH_ADDR_START_7                                             0x1410
define                                               
#define mmGARLIC_FLUSH_ADDR_END_10x1405
#define mmGARLIC_FLUSH_ADDR_END_2                                               0x1407
#define mmGARLIC_FLUSH_ADDR_END_3                                               #definemmGARLIC_COHE_SDMA3_GFX_RB_WPTR0x1423
#definemmGARLIC_FLUSH_ADDR_END_40x140b
#define mmGARLIC_FLUSH_ADDR_END_5                                               0x140d
#define mmGARLIC_FLUSH_ADDR_END_60x140f
#define mmGARLIC_FLUSH_ADDR_END_7                                               0x1411
#define mmGARLIC_FLUSH_REQ                                                      
#define mmGPU_GARLIC_FLUSH_REQ                                                  0x1413
#define mmGPU_GARLIC_FLUSH_DONE                                                 0x1414
#definemmGARLIC_COHE_CP_RB0_WPTR0x1415
#define mmGARLIC_COHE_CP_RB1_WPTR                                               0x1416
#define mmGARLIC_COHE_CP_RB2_WPTR                                               0x1417
#define mmGARLIC_COHE_UVD_RBC_RB_WPTR                                           0x1418
#define                                          
#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR                                                        
#definemmBIOS_SCRATCH_40x5cd
#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND0x5ce
#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR                                          #efinemmBIOS_SCRATCH_60x5cf
                                           
#define mmGARLIC_COHE_VCE_OUT_RB_WPTR                                           0x141f
#define mmGARLIC_COHE_VCE_RB_WPTR2                                              0x1420
#define mmGARLIC_COHE_VCE_RB_WPTR                                               0x1421
#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR0x5d3
#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR                                         0x1423
#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND0x1424
#define mmGARLIC_COHE_GARLIC_FLUSH_REQ                                          0x1425
#define mmREMAP_HDP_MEM_FLUSH_CNTL                                              0x1426
#define mmREMAP_HDP_REG_FLUSH_CNTL                                              0x1427
#define mmBIOS_SCRATCH_0                                                        0x5c9
#define mmBIOS_SCRATCH_10x5ca
#define mmBIOS_SCRATCH_2                                                        0x5cb
#define mmBIOS_SCRATCH_3                                                        0x5cc
#define mmBIOS_SCRATCH_4                                                        0x5cd
#define mmBIOS_SCRATCH_5#efine                                                       
#define mmBIOS_SCRATCH_6define                                                           
#define mmBIOS_SCRATCH_7                                                        0x5d0
#define mmBIOS_SCRATCH_8                                                        0x5d1
#define mmBIOS_SCRATCH_9                                                        0x5d2
define                                                       
#define mmBIOS_SCRATCH_11                                                       0x5d4
#define mmBIOS_SCRATCH_12                                                       0x5d5
#define mmBIOS_SCRATCH_13                                                       0x5d6
#define mmBIOS_SCRATCH_14                                                       0x5d7
#define mmBIOS_SCRATCH_15                                                       0x5d8
#define mmBIF_RB_CNTL                                                           #definemmREVISION_ID0x2
#define mmBIF_RB_BASE                                                           0x1531
#define mmBIF_RB_RPTR                                                           0x1532
define                                                           
#define mmBIF_RB_WPTR_ADDR_HI                                                   
#define mmBIF_RB_WPTR_ADDR_LO                                                   0x1535
#definemmVENDOR_ID0x0
define                                                               
#define mmCOMMAND                                                               0x1
#define mmSTATUS                                                                0x1
#define mmREVISION_ID                                                           
#define mmPROG_INTERFACE                                                        0x2
#define mmSUB_CLASS                                                             0x2
#define mmBASE_CLASS                                                                                                                       
#define mmCACHE_LINE                                                            0x3
#define mmLATENCY                                                               0x3
#define mmHEADER                                                                0xc
#define mmBIST                                                                  0x3
define0x4
#define mmBASE_ADDR_2                                                           0x5
#define mmBASE_ADDR_3                                                           0x6
#define mmBASE_ADDR_4                                                           
#define mmBASE_ADDR_5                                                           0x8
#define mmBASE_ADDR_6                                                           0x9
#define mmROM_BASE_ADDR                                                         0xc
#define mmCAP_PTR                                                               0xd
#define mmINTERRUPT_LINE                                                        0xf
#define mmINTERRUPT_PIN                                                         0xf
#define mmADAPTER_ID0xb
#define mmMIN_GRANT                                                             0xf
#define mmMAX_LATENCY                                                           0xf
#define mmVENDOR_CAP_LIST                                                       0x12
#efinemmADAPTER_ID_W                                                          
#define mmPMI_CAP_LIST                                                          0x14                                                             
#define mmPMI_CAP                                                               0x14
#define mmPMI_STATUS_CNTL                                                       0x15
#define mmPCIE_CAP_LIST                                                         0x16
#define mmPCIE_CAP                                                              0x16
#define mmDEVICE_CAP                                                            0x17
#define mmDEVICE_CNTL                                                           0x18
#define mmDEVICE_STATUS                                                         0#efinemmLINK_CAP20x21
#define mmLINK_CAP                                                              0x22
#define mmLINK_STATUS2                                                          0x22
#define mmLINK_STATUS                                                           
#define mmDEVICE_CAP2                                                           0x1f
#define mmDEVICE_CNTL2                                                          0x20define0x28
#define mmDEVICE_STATUS2#define mmMSI_MSG_ADDR_LO                                                       
#define mmLINK_CAP2                                                             0x21
#definemmMSI_MSG_DATA_640x2b
#define mmLINK_STATUS2                                                          0x22
#define mmMSI_CAP_LIST                                                          0x28
#define mmMSI_MSG_CNTL                                                          0x28
#define mmMSI_MSG_ADDR_LO                                                       0x29
#define mmMSI_MSG_ADDR_HI                                                       0x2a
#define mmMSI_MSG_DATA_64                                                       0x2b
#define mmMSI_MSG_DATA0x2a
#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                     0x40
#define mmPCIE_VENDOR_SPECIFIC_HDR                                              0x41
#define mmPCIE_VENDOR_SPECIFIC10x42
#define mmPCIE_VENDOR_SPECIFIC2                                                 0x43
#define mmPCIE_VC_ENH_CAP_LIST                                                  0x44
                                                 0x45
#define mmPCIE_PORT_VC_CAP_REG2                                                 0x46
#define mmPCIE_PORT_VC_CNTL                                                     0x47
#define mmPCIE_PORT_VC_STATUS0x47
#define mmPCIE_VC0_RESOURCE_CAP                                                 0x48
#define mmPCIE_VC0_RESOURCE_CNTL                                                0x49
#define mmPCIE_VC0_RESOURCE_STATUS#define mmPCIE_PORT_VC_CAP_REG1                                                 
#define mmPCIE_VC1_RESOURCE_CAP                                                 #definemmPCIE_PORT_VC_CAP_REG20x46
#define mmPCIE_VC1_RESOURCE_CNTL                                                0x4c
#define #define mmPCIE_PORT_VC_CNTL0x47
#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                      0x50
 mmPCIE_DEV_SERIAL_NUM_DW10x51
#define mmPCIE_DEV_SERIAL_NUM_DW2                                               0x52
#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LISTdefinemmPCIE_VC0_RESOURCE_CAP                                                 x48
#efine mmPCIE_UNCORR_ERR_STATUS0x55
#define mmPCIE_UNCORR_ERR_MASK                                                  0x56
#define mmPCIE_UNCORR_ERR_SEVERITY                                              0x57
#define mmPCIE_CORR_ERR_STATUS0x58
#define mmPCIE_CORR_ERR_MASK                                                    0x59
#define mmPCIE_ADV_ERR_CAP_CNTL                                                 0x5a
#define mmPCIE_HDR_LOG0                                                         0x5b
#define mmPCIE_HDR_LOG1                                                         0x5c
#define mmPCIE_HDR_LOG2                                                         0x5d mmPCIE_DEV_SERIAL_NUM_DW1                                               0x51
#define mmPCIE_HDR_LOG3                                                         0x5e
#define mmPCIE_TLP_PREFIX_LOG0                                                  0x62
#define mmPCIE_UNCORR_ERR_MASK0x56
#define mmPCIE_TLP_PREFIX_LOG2                                                  0x64
#define mmPCIE_TLP_PREFIX_LOG3                                                  0x65
#define mmPCIE_BAR_ENH_CAP_LIST                                                 0x80
#define mmPCIE_BAR1_CAP0x81
#define mmPCIE_BAR1_CNTL                                                        0x82
#define mmPCIE_BAR2_CAP0x83
#define mmPCIE_BAR2_CNTL                                                        0x84
#define mmPCIE_BAR3_CAP                                                         0x85
#efine mmPCIE_BAR3_CNTL                                                        
#define mmPCIE_BAR4_CAP                                                         0x87
#define mmPCIE_BAR4_CNTL#efinemmPCIE_HDR_LOG20x5d
#define mmPCIE_BAR5_CAP                                                         0x89
#define mmPCIE_BAR5_CNTL                                                        0x8a
#define mmPCIE_BAR6_CAP                                                         
## mmPCIE_TLP_PREFIX_LOG10x63
#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST                                          0x90
#define mmPCIE_PWR_BUDGET_DATA_SELECT                                           0x91
#define mmPCIE_PWR_BUDGET_DATA                                                  0x92
#define mmPCIE_PWR_BUDGET_CAP                                                   0x93
#define mmPCIE_DPA_ENH_CAP_LIST                                                 0x94
#define mmPCIE_DPA_CAP                                                          0x95
#define mmPCIE_DPA_LATENCY_INDICATOR                                            0x96
#define mmPCIE_DPA_STATUS                                                       0x97
#define mmPCIE_DPA_CNTL                                                         0x97
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                         0x98
#definemmPCIE_DPA_SUBSTATE_PWR_ALLOC_10x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                         0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                         0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                         0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                         0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                         
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                         0x99
#define mmPCIE_SECONDARY_ENH_CAP_LIST                                           0x9c
#define mmPCIE_LINK_CNTL3                                                       0x9d
#define mmPCIE_LANE_ERROR_STATUS                                                0x9e
#define mmPCIE_LANE_0_EQUALIZATION_CNTL                                         0x9f
define                                         x9f
#define mmPCIE_LANE_2_EQUALIZATION_CNTL                                         
#define mmPCIE_LANE_3_EQUALIZATION_CNTL                                         0xa0
#define mmPCIE_LANE_4_EQUALIZATION_CNTL                                         0xa1
#define mmPCIE_LANE_5_EQUALIZATION_CNTL                                         0xa1
#define mmPCIE_LANE_6_EQUALIZATION_CNTL                                         0xa2
#define mmPCIE_LANE_7_EQUALIZATION_CNTL                                         0xa2
mmPCIE_LANE_8_EQUALIZATION_CNTL0xa3
#define mmPCIE_LANE_9_EQUALIZATION_CNTL                                         0xa3
#define mmPCIE_LANE_10_EQUALIZATION_CNTL                                        0xa4
#define mmPCIE_LANE_11_EQUALIZATION_CNTL                                        0xa4
#define mmPCIE_LANE_12_EQUALIZATION_CNTL                                        0xa5
#define mmPCIE_LANE_13_EQUALIZATION_CNTL                                        0xa5
#define                                         java.lang.StringIndexOutOfBoundsException: Index 84 out of bounds for length 84
#define mmPCIE_LANE_15_EQUALIZATION_CNTL                                        0xa6
#definemmPCIE_ACS_ENH_CAP_LIST0xa8
#define mmPCIE_ACS_CAP                                                          0xa9
#define mmPCIE_ACS_CNTL                                                         0xa9
#define mmPCIE_ATS_ENH_CAP_LIST                                                 0xac
#define mmPCIE_ATS_CAP                                                                                                     
                                                         
#define mmPCIE_PAGE_REQ_ENH_CAP_LIST                                            0xb0
#define mmPCIE_PAGE_REQ_CNTL                                                                                             
#define mmPCIE_PAGE_REQ_STATUS                                                  0xb1
#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                       0xb2
#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC                                          0mmPCIE_LANE_7_EQUALIZATION_CNTL0xa2
#definemmPCIE_PASID_ENH_CAP_LIST0xb4
#define mmPCIE_PASID_CAP                                                        0xb5
#define mmPCIE_PASID_CNTL                                                       0xb5
#define mmPCIE_TPH_REQR_ENH_CAP_LIST                                            0xb8
#define mmPCIE_TPH_REQR_CAP                                        
#define#define                                         
#define mmPCIE_MC_ENH_CAP_LIST                                                  0xbc
#define mmPCIE_MC_CAP                                                                                                                     
#define#define mmPCIE_ATS_ENH_CAP_LIST0xac
#define mmPCIE_MC_ADDR0                                                         0xbe
#define mmPCIE_MC_ADDR1                                                         0xbf
#define mmPCIE_MC_RCV0                                                          0xc0
#define mmPCIE_MC_RCV1                                                          0xc1
#define mmPCIE_MC_BLOCK_ALL0                                                    0xc2
#define mmPCIE_MC_BLOCK_ALL1                                                    0xc3
#define mmPCIE_MC_BLOCK_UNTRANSLATED_0                                                                                     java.lang.StringIndexOutOfBoundsException: Index 84 out of bounds for length 84
#definemmPCIE_MC_BLOCK_UNTRANSLATED_10
#define mmPCIE_LTR_ENH_CAP_LIST                                                 0xc8
#define mmPCIE_LTR_CAP                                                          0xc9
#define ixMM_INDEX_IND                                                          0x1090000
#define ixMM_INDEX_HI_IND                                                       0x1090006
#define ixMM_DATA_IND                                                           0x1090001
#define ixBIF_MM_INDACCESS_CNTL_IND                                             0x1091500
#define ixBUS_CNTL_IND                                                          0x1091508
#define ixCONFIG_CNTL_IND                                                       0x1091509
#define ixCONFIG_MEMSIZE_IND                                                    0x109150a
#define ixCONFIG_F0_BASE_IND                                                    0x109150b
#define ixCONFIG_APER_SIZE_IND                                                  0x109150c
#define ixCONFIG_REG_APER_SIZE_IND                                              0x109150d
#define ixBIF_SCRATCH0_IND                                                      0x109150e
#define ixBIF_SCRATCH1_IND                                                      0x109150f
defineixBX_RESET_EN_IND0x1091514
#define ixMM_CFGREGS_CNTL_IND                                                   0x1091513
#define ixHW_DEBUG_IND                                                          0x1091515
#define ixMASTER_CREDIT_CNTL_IND                                                0x1091516
#defineixSLAVE_REQ_CREDIT_CNTL_IND0x1091517
#define ixBX_RESET_CNTL_IND                                                     0x1091518
#define ixINTERRUPT_CNTL_IND                                                    0x109151a
#define ixINTERRUPT_CNTL2_IND                                                   0x109151b
#define ixBIF_DEBUG_CNTL_IND0x109151c
#define ixBIF_DEBUG_MUX_IND                                                     0x109151d
#define ixBIF_DEBUG_OUT_IND                                                     0x109151e
#define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND                                      0x1091528
#define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND                                      
#define ixCLKREQB_PAD_CNTL_IND                                                  0x1091521
#define ixSMBDAT_PAD_CNTL_IND                                                   0x1091522
#define ixSMBCLK_PAD_CNTL_IND                                                   0x1091523
#define ixBIF_XDMA_LO_IND                                                       
#define ixBIF_XDMA_HI_IND                                                       0x10914c1
#define ixBIF_FEATURES_CONTROL_MISC_IND                                         0x10914c2
                                                 
#define ixBIF_SLVARB_MODE_IND                                                   0x10914c4
#define #define ixCONFIG_REG_APER_SIZE_IND
#define ixBIF_BUSNUM_CNTL1_IND                                                  0x1091525
#define ixBIF_BUSNUM_LIST0_IND                                                                                                         
#define ixBIF_BUSNUM_LIST1_IND                                                  0x1091527
#define ixBIF_BUSNUM_CNTL2_IND                                                  0x109152b
#define ixBIF_BUSY_DELAY_CNTR_IND                                               0x1091529
#define ixBIF_PERFMON_CNTL_IND                                                  0x109152c
#define ixBIF_PERFCOUNTER0_RESULT_IND                                           0x109152d
#define ixBIF_PERFCOUNTER1_RESULT_IND ixBIF_DEBUG_CNTL_IND0x109151c
#define                                         
                                                  
#define ixGPU_HDP_FLUSH_DONE_IND                                                0x1091538
#define ixSLAVE_HANG_ERROR_IND                                                                                                      
#define ixCAPTURE_HOST_BUSNUM_IND                                               0x109153c
#define ixHOST_BUSNUM_IND                                                       0x109153d
#define ixPEER_REG_RANGE0_IND                                                                                                    
#define ixPEER_REG_RANGE1_IND                                                   0x1091524
#define ixPEER0_FB_OFFSET_HI_IND                                                0x10914f3
#define ixPEER0_FB_OFFSET_LO_IND                                                0x10914f2
#define ixPEER1_FB_OFFSET_HI_IND0x10914f1
#define ixPEER1_FB_OFFSET_LO_IND                                                0x10914f0
#define ixPEER2_FB_OFFSET_HI_IND ixBIF_BUSNUM_CNTL2_IND0x109152b
#define ixPEER2_FB_OFFSET_LO_IND                                                0x10914eeixBIF_BUSY_DELAY_CNTR_IND0x1091529
#defineixPEER3_FB_OFFSET_HI_IND0x10914ed
#define ixPEER3_FB_OFFSET_LO_IND                                                0x10914ec
#define#efine ixBIF_PERFCOUNTER0_RESULT_IND                                           
#defineixSMBUS_BACO_DUMMY_IND0x10914c6
#define ixBIF_DEVFUNCNUM_LIST0_IND                                              0x10914e8
#define ixBIF_DEVFUNCNUM_LIST1_IND                                              0x10914e7
#define ixBACO_CNTL_IND0x10914e5
#define ixBF_ANA_ISO_CNTL_IND                                                   0x10914c7
#define ixMEM_TYPE_CNTL_IND                                                     0x10914e4
#define ixBIF_BACO_DEBUG_IND                                                    0x10914df
#define ixBIF_BACO_DEBUG_LATCH_IND                                              0x10914dc
define                                                    
#define ixSMU_BIF_VDDGFX_PWR_STATUS_IND                                         0x10914f8#define ixCAPTURE_HOST_BUSNUM_IND                                               0x109153c
#define ixBIF_VDDGFX_GFX0_LOWER_IND                                             0x1091428
#define ixBIF_VDDGFX_GFX0_UPPER_IND                                             0x1091429
#define ixBIF_VDDGFX_GFX1_LOWER_IND                                                                                                
#define ixBIF_VDDGFX_GFX1_UPPER_IND                                             0x109142b
#define ixBIF_VDDGFX_GFX2_LOWER_IND                                             0x109142c
#define                                                 
define                                             
#define ixBIF_VDDGFX_GFX3_UPPER_IND                                             0x109142f
#define ixBIF_VDDGFX_GFX4_LOWER_IND                                             0x1091430
#define ixBIF_VDDGFX_GFX4_UPPER_IND                                             0x1091431
defineixBIF_VDDGFX_GFX5_LOWER_IND0x1091432
#define ixBIF_VDDGFX_GFX5_UPPER_IND                                             0x1091433
#define ixBIF_VDDGFX_RSV1_LOWER_IND                                             0x1091434
#define ixBIF_VDDGFX_RSV1_UPPER_IND                                             0x1091435
#define ixBIF_VDDGFX_RSV2_LOWER_IND                                             0x1091436
#define ixBIF_VDDGFX_RSV2_UPPER_IND                                             0x1091437
#define ixBIF_VDDGFX_RSV3_LOWER_IND                                             0x1091438
#define ixBIF_VDDGFX_RSV3_UPPER_IND                                             ixMEM_TYPE_CNTL_IND0x10914e4
#define ixBIF_VDDGFX_RSV4_LOWER_IND                                             0x109143a
#define ixBIF_VDDGFX_RSV4_UPPER_IND                                             0x109143b
#define ixBIF_VDDGFX_FB_CMP_IND                                                 0x109143c
#define ixBIF_DOORBELL_GBLAPER1_LOWER_IND                                       0x10914fc
define                                       
define                                       
#define ixBIF_VDDGFX_GFX1_UPPER_IND0x109142b
#define ixBIF_SMU_INDEX_IND                                                     0x109143d
#define ixBIF_SMU_DATA_IND                                                      
ixIMPCTL_RESET_IND                                                      
##defineixBIF_VDDGFX_GFX3_LOWER_IND                                             0x109142e
#define ixGARLIC_FLUSH_REQ_IND                                                  0x1091412
#define ixGPU_GARLIC_FLUSH_REQ_IND                                              0x1091413
#define ixGPU_GARLIC_FLUSH_DONE_IND                                             0x1091414
#define ixGARLIC_COHE_CP_RB0_WPTR_IND                                           0x1091415
#define #define ixBIF_VDDGFX_GFX5_UPPER_IND                                             java.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
#define ixGARLIC_COHE_CP_RB2_WPTR_IND                                           0x1091417
#define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND                                       0x1091418
#define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND                                     0x1091419                                              
#define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND                                     0x109141a
#define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND                                     0x109141b
#define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND                                    0x109141c
#define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND                                      0x109141d
#define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND0x109141e
#define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND                                       0x109141f
0x1091420
#define ixGARLIC_COHE_VCE_RB_WPTR_IND                                           0x1091421
#define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND                                     0x1091422
#define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND                                     0x1091423
#define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND                                    0x1091424
#define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND                                                                                             
#define ixREMAP_HDP_MEM_FLUSH_CNTL_IND                                          0x1091426
#define ixREMAP_HDP_REG_FLUSH_CNTL_IND                                          
#defineixBIOS_SCRATCH_0_IND0x10905c9
#define ixBIOS_SCRATCH_1_IND                                                    0x10905ca
#define ixBIOS_SCRATCH_2_IND                                                    
#define ixBIOS_SCRATCH_3_IND                                                    0x10905cc
#define ixBIOS_SCRATCH_4_IND                                                    0x10905cd
#define ixBIOS_SCRATCH_5_IND                                                    0x10905ce
#define ixBIOS_SCRATCH_6_IND0x10905cf
#define ixBIOS_SCRATCH_7_IND                                                    0x10905d0
#define ixBIOS_SCRATCH_8_IND                                                    0x10905d1
#define ixBIOS_SCRATCH_9_IND                                                    define                                       0011java.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89

#define ixBIOS_SCRATCH_11_IND                                                   0x10905d4
#define ixBIOS_SCRATCH_12_IND                                                   0x10905d5
#define ixBIOS_SCRATCH_13_IND                                                   0x10905d6
#define ixBIOS_SCRATCH_14_IND                                                   0x10905d7
#defineixBIOS_SCRATCH_15_IND0x10905d8
#define ixBIF_RB_CNTL_IND                                                       0x1091530
#define ixBIF_RB_BASE_IND                                                       0x1091531
define                                                       java.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
#definedefine                                     
ixBIF_RB_WPTR_ADDR_HI_IND0
#define ixBIF_RB_WPTR_ADDR_LO_IND                                               0x1091535
#define mmNB_GBIF_INDEX                                                         0x34
#define mmNB_GBIF_DATA                                                          0x35
#define mmPCIE_INDEX                                                            0xe
#define mmPCIE_DATA                                                             0xf
#define mmPCIE_INDEX_2                                                          0xc
#efine mmPCIE_DATA_20xd
#define ixPCIE_RESERVED                                                         0x1400000
#define ixPCIE_SCRATCH                                                          0x1400001
#define ixPCIE_HW_DEBUG                                                         0x1400002
#define ixPCIE_RX_NUM_NAK                                                       0x140000e
#define ixPCIE_RX_NUM_NAK_GENERATED                                             0x140000f
#define ixPCIE_CNTL                                                             0x1400010
#define ixPCIE_CONFIG_CNTL                                                      0x1400011
#define ixPCIE_DEBUG_CNTL                                                       0x1400012
#define ixPCIE_INT_CNTL                                                         0x140001a
#define ixPCIE_INT_STATUS                                                       0x140001b
#define ixPCIE_CNTL2                                                            0x140001c
#define ixPCIE_RX_CNTL2                                                         0x140001d
#define ixPCIE_TX_F0_ATTR_CNTL                                                  0x140001e
#define ixPCIE_TX_F1_F2_ATTR_CNTL                                               0x140001f
#define ixPCIE_CI_CNTL                                                          0x1400020
#define ixPCIE_BUS_CNTLdefine                                                       
#define ixPCIE_LC_STATE6                                                        0x1400022
#define ixPCIE_LC_STATE7                                                        0x1400023
#define ixPCIE_LC_STATE8                                                        0x1400024
#define ixPCIE_LC_STATE9                                                        0x1400025
#define ixPCIE_LC_STATE10                                                       0x1400026
#define ixPCIE_LC_STATE11                                                       0x1400027
#define ixPCIE_LC_STATUS1                                                       0x1400028
#define ixPCIE_LC_STATUS2                                                       0x1400029
#define ixPCIE_WPR_CNTL0x1400030
#define ixPCIE_RX_LAST_TLP0                                                     0x1400031
#define ixPCIE_RX_LAST_TLP1                                                     0x1400032
#define ixPCIE_RX_LAST_TLP2                                                             
#define ixPCIE_RX_LAST_TLP3                                                     0x1400034
#define ixPCIE_TX_LAST_TLP0                                                     0x1400035
#define ixPCIE_TX_LAST_TLP1                                                     0x1400036
#define ixPCIE_TX_LAST_TLP20x1400037
#define ixPCIE_TX_LAST_TLP3                                                     0x1400038
#define ixPCIE_I2C_REG_ADDR_EXPAND                                              0x140003a
#define ixPCIE_I2C_REG_DATA                                                     0x140003b
#define ixPCIE_CFG_CNTL                                                         0x140003c
#define ixPCIE_P_CNTL                                                           0x1400040
#define ixPCIE_P_BUF_STATUS                                                     0x1400041
#define ixPCIE_P_DECODER_STATUS                                                 0x1400042
#define ixPCIE_P_MISC_STATUS                                                    0x1400043
#define ixPCIE_P_RCV_L0S_FTS_DET                                                0x1400050
#define ixPCIE_OBFF_CNTL                                                        0x1400061
#define ixPCIE_TX_LTR_CNTL                                                      0x1400060
#define ixPCIE_PERF_COUNT_CNTL                                                  0x1400080
#define ixPCIE_PERF_CNTL_TXCLK                                                  0x1400081
#define ixPCIE_PERF_COUNT0_TXCLK                                                0x1400082
#define ixPCIE_PERF_COUNT1_TXCLK                                                0x1400083
#define ixPCIE_PERF_CNTL_MST_R_CLK                                              0x1400084
#define ixPCIE_PERF_COUNT0_MST_R_CLK                                            0x1400085
# ixPCIE_PERF_COUNT1_MST_R_CLK0x1400086
#define ixPCIE_PERF_CNTL_MST_C_CLK                                              0x1400087
#defineixPCIE_PERF_COUNT0_MST_C_CLK0x1400088
#define ixPCIE_PERF_COUNT1_MST_C_CLK                                            0x1400089
#define ixPCIE_PERF_CNTL_SLV_R_CLK                                              0x140008a
#define ixPCIE_PERF_COUNT0_SLV_R_CLK                                            0x140008b
#define ixPCIE_PERF_COUNT1_SLV_R_CLK                                            0x140008c
#define ixPCIE_PERF_CNTL_SLV_S_C_CLK                                            0x140008d
#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK                                          0x140008e
#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK0x140008f
#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK                                           0x1400090
#defineixPCIE_PERF_COUNT0_SLV_NS_C_CLK0x1400091
#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK                                         0x1400092
#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL                                        0x1400093
#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL                                        0x1400094
define                                                 
#define ixPCIE_PERF_COUNT0_TXCLK2                                               0x1400096
#define ixPCIE_PERF_COUNT1_TXCLK2                                               0x1400097
#define ixPCIE_STRAP_F0                                                         0x14000b0
#define ixPCIE_STRAP_F1                                                         0x14000b1
#define ixPCIE_STRAP_F2                                                         0x14000b2
#define ixPCIE_STRAP_F3                                                         0x14000b3
#define ixPCIE_STRAP_F4                                                         0x14000b4
#define ixPCIE_STRAP_F5                                                         0x14000b5
#define ixPCIE_STRAP_F6                                                         0x14000b6
#define ixPCIE_STRAP_F7                                                         0x14000b7
#define ixPCIE_STRAP_MISC                                                       0x14000c0
#define ixPCIE_STRAP_MISC2                                                      0x14000c1
#define ixPCIE_STRAP_PI                                                         0x14000c2
#define ixPCIE_STRAP_I2C_BD                                                     0x14000c4
#define ixPCIE_PRBS_CLR                                                         0x14000c8
#define ixPCIE_PRBS_STATUS1                                                     0x14000c9                                                   
#define ixPCIE_PRBS_STATUS2                                                                                                     
#define ixPCIE_PRBS_FREERUN                                                     0x14000cb
#define ixPCIE_PRBS_MISC                                                        0x14000cc
#define ixPCIE_PRBS_USER_PATTERN                                                                                              
#define ixPCIE_PRBS_LO_BITCNT                                                   0x14000ce
#define ixPCIE_PRBS_HI_BITCNT                                                   0x14000cf                                              
#define ixPCIE_PRBS_ERRCNT_0                                                    00x140008d
#define ixPCIE_PRBS_ERRCNT_1                                                    0x14000d1
#define ixPCIE_PRBS_ERRCNT_2                                                    0x14000d2
#define ixPCIE_PRBS_ERRCNT_3                                                    0x14000d3
#define ixPCIE_PRBS_ERRCNT_4                                                    0x14000d4
#define ixPCIE_PRBS_ERRCNT_5                                                    0x14000d5
#define ixPCIE_PRBS_ERRCNT_6                                                    0x14000d6
#define ixPCIE_PRBS_ERRCNT_7                                                    0x14000d7
#define ixPCIE_PRBS_ERRCNT_8                                                    0x14000d8
#define ixPCIE_PRBS_ERRCNT_9                                                    0x14000d9
define                                                   
#define ixPCIE_PRBS_ERRCNT_110x14000db
#define ixPCIE_PRBS_ERRCNT_12                                                   0x14000dc
#define ixPCIE_PRBS_ERRCNT_13                                                   0x14000dd
#define ixPCIE_PRBS_ERRCNT_14                                                   
#define ixPCIE_PRBS_ERRCNT_15                                                   0x14000df
#define ixPCIE_F0_DPA_CAP                                                       0x14000e0
#define ixPCIE_F0_DPA_LATENCY_INDICATOR                                         0x14000e4
define                                                      
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                      0x14000e7
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                      0x14000e8
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                      0x14000e9
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                      0java.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                      0x14000eb
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                      0x14000ec
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                      0x14000ed
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_70x14000ee
#define ixPCIEP_RESERVED                                                        0x10010000
#define ixPCIEP_SCRATCH                                                         0x10010001
#define ixPCIEP_HW_DEBUG                                                        0x10010002
#define ixPCIEP_PORT_CNTL                                                       0x10010010
#define ixPCIE_TX_CNTL                                                                                                                
#define ixPCIE_TX_REQUESTER_ID                                                  0x10010021
#define ixPCIE_TX_VENDOR_SPECIFIC                                               0x10010022
#define ixPCIE_TX_REQUEST_NUM_CNTL                                              x10010023
#define ixPCIE_TX_SEQ                                                           0x10010024
ixPCIE_TX_REPLAY                                                        
defineixPCIE_TX_ACK_LATENCY_LIMIT0x10010026
#define ixPCIE_TX_CREDITS_ADVT_P                                                0x10010030
#define ixPCIE_TX_CREDITS_ADVT_NP                                               #0x14000d2
#define ixPCIE_TX_CREDITS_ADVT_CPL                                              0x10010032
#define ixPCIE_TX_CREDITS_INIT_P                                                0x10010033
#definedefine                                                    
#define ixPCIE_TX_CREDITS_INIT_CPL                                              0x10010035
#define ixPCIE_TX_CREDITS_STATUS                                                0x10010036
#define ixPCIE_TX_CREDITS_FCU_THRESHOLD                                         0x10010037
#define ixPCIE_P_PORT_LANE_STATUS                                               0x10010050                                                   
#define ixPCIE_FC_P                                                             0x10010060
#define ixPCIE_FC_NP                                                            0
#define ixPCIE_FC_CPL                                                           0x10010062
##defineixPCIE_F0_DPA_CAP0x14000e0
#define ixPCIE_RX_CNTL                                                          0x10010070
#define ixPCIE_RX_EXPECTED_SEQNUM                                               0x10010071
#define ixPCIE_RX_VENDOR_SPECIFIC                                               0x10010072
#define ixPCIE_RX_CNTL3                                                         0x10010074
#define ixPCIE_RX_CREDITS_ALLOCATED_P                                           0x10010080
#define ixPCIE_RX_CREDITS_ALLOCATED_NP                                          0x10010081
#define ixPCIE_RX_CREDITS_ALLOCATED_CPL                                         0x10010082
#define ixPCIE_LC_CNTL                                                          0x100100a0
#define ixPCIE_LC_CNTL2                                                         0x100100b1
#define ixPCIE_LC_CNTL3                                                         0x100100b5
#define ixPCIE_LC_CNTL4                                                         0x100100b6
#define ixPCIE_LC_CNTL5                                                         0x100100b7
#define ixPCIE_LC_BW_CHANGE_CNTL                                                0x100100b2
ixPCIE_LC_TRAINING_CNTL0x100100a1
#define ixPCIE_LC_LINK_WIDTH_CNTL                                               0x100100a2
#define ixPCIE_LC_N_FTS_CNTL                                                    0x100100a3
#define ixPCIE_LC_SPEED_CNTL                                                    0x100100a4
#define ixPCIE_LC_CDR_CNTL                                                      x100100b3
#define ixPCIE_LC_LANE_CNTL                                                     0x100100b4
                                                   
define                                               
#define ixPCIE_LC_FORCE_EQ_REQ_COEFF                                            
#define ixPCIE_LC_STATE0define                                                           
#define ixPCIE_LC_STATE1                                                        0x100100a6
#define ixPCIE_LC_STATE2                                                        0x100100a7
#define ixPCIE_LC_STATE3                                                        0#defineixPCIE_TX_CREDITS_ADVT_NP0x10010031
#define ixPCIE_LC_STATE4                                                        0x100100a9
#define ixPCIE_LC_STATE50x100100aa
#define ixPCIEP_STRAP_LC                                                        0x100100c0
#define ixPCIEP_STRAP_MISC                                                      0x100100c1
#define ixPCIEP_BCH_ECC_CNTL                                                    0x100100d0#define ixPCIE_TX_CREDITS_INIT_P                                                x10010033
#define mmBIF_RFE_SNOOP_REG                                                
define                                                  
define0x1441
#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER                                                                                                     
#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER                                        0x1443
#define mmBIF_PWDN_COMMAND                                                      0x1444
#define mmBIF_PWDN_STATUS                                                       0x1445
#define mmBIF_RFE_MST_FBU_CMDSTATUS                                             0x1446                                               
#define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS                                  0x1447
mmBIF_RFE_MST_BX_CMDSTATUS0x1448
#define mmBIF_RFE_MST_TMOUT_STATUS                                              0x144b
#define mmBIF_RFE_MMCFG_CNTL0x144c
#define ixBIF_CLOCKS_BITS_IND                                                   0x1301489
#define ixBIF_LNCNT_RESET_IND                                                   0x1301488
#define ixLNCNT_CONTROL_IND                                                     0x1301487
#define ixNEW_REFCLKB_TIMER_IND                                                 ixPCIE_LC_CNTL20x100100b1
#define ixNEW_REFCLKB_TIMER_1_IND                                               0x1301484
#define ixBIF_CLK_PDWN_DELAY_TIMER_IND                                          0x1301483
#define ixBIF_RESET_EN_IND                                                      0x1301482
#define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND                                        0x1301481ixPCIE_LC_CNTL50x100100b7
#define ixBIF_BACO_MSIC_IND                                                     0x1301480
#define ixBIF_RESET_CNTL_IND                                                    0x1301486
#define ixBIF_RFE_CNTL_MISC_IND                                                 0x130148c
#define ixBIF_MEM_PG_CNTL_IND                                                   
#define mmNB_GBIF_INDEXixPCIE_LC_N_FTS_CNTL0x100100a3
#define mmNB_GBIF_DATA                                                          0x35
#define mmBIF_CLOCKS_BITS                                                       0x1489
#define mmBIF_LNCNT_RESET                                                       0x1488
#define mmLNCNT_CONTROL                                                         0x1487ixPCIE_LC_LANE_CNTL0x100100b4
#define ixPCIE_LC_FORCE_COEFF0x100100b8
#define mmNEW_REFCLKB_TIMER_1                                                   0x1484
#define mmBIF_CLK_PDWN_DELAY_TIMER0x1483
#define mmBIF_RESET_EN                                                          0x1482
                                             
#define mmBIF_BACO_MSIC                                                         0#defineixPCIE_LC_STATE00x100100a5
#define#efineixPCIE_LC_STATE10x100100a6
#define mmBIF_RFE_CNTL_MISC                                                     0x148c
#define mmBIF_MEM_PG_CNTL                                                       0x148a
#define mmC_PCIE_P_INDEX                                                        0x38
mmC_PCIE_P_DATA                                                         
define                                                  
#define ixD2F1_PCIE_PORT_DATA                                                   0x2000039
#define ixD2F1_PCIEP_RESERVED                                                   0x0
#define ixD2F1_PCIEP_SCRATCH                                                    0x1
#define ixD2F1_PCIEP_HW_DEBUGdefine                                                      
#define ixD2F1_PCIEP_PORT_CNTL                                                  0x10
#define ixD2F1_PCIE_TX_CNTL                                                     0x20
#define ixD2F1_PCIE_TX_REQUESTER_ID                                             0x21
#define ixD2F1_PCIE_TX_VENDOR_SPECIFIC                                          0x22
#define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
#define ixD2F1_PCIE_TX_SEQ                                                      0x24
#define ixD2F1_PCIE_TX_REPLAY                                                   0x25
#define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
#define ixD2F1_PCIE_TX_CREDITS_ADVT_P                                           0x30
#define ixD2F1_PCIE_TX_CREDITS_ADVT_NP                                          0x31
#define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL0x32
#define ixD2F1_PCIE_TX_CREDITS_INIT_P                                           0x33
#define ixD2F1_PCIE_TX_CREDITS_INIT_NP                                          0x34
#define ixD2F1_PCIE_TX_CREDITS_INIT_CPL                                         0x35
## mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS0
#define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
#define ixD2F1_PCIE_P_PORT_LANE_STATUS                                          0x50
#define ixD2F1_PCIE_FC_P                                                        0x60
#definemmBIF_RFE_MST_BX_CMDSTATUS0x1448
#define ixD2F1_PCIE_FC_CPL                                                      0x62
#define ixD2F1_PCIE_ERR_CNTL                                                    0x6a
#define ixD2F1_PCIE_RX_CNTL                                                     0x70
#define ixD2F1_PCIE_RX_EXPECTED_SEQNUM0x71
#define ixD2F1_PCIE_RX_VENDOR_SPECIFIC                                          0x72
#define ixD2F1_PCIE_RX_CNTL3                                                                                                          
#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P                                      ixNEW_REFCLKB_TIMER_1_IND0x1301484
#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
#define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
#define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
#define ixD2F1_PCIE_LC_CNTL                                                     0xa0
#define ixD2F1_PCIE_LC_CNTL2                                                    0xb1
#define ixD2F1_PCIE_LC_CNTL30xb5
#define ixD2F1_PCIE_LC_CNTL4                                                    0xb6
#define ixD2F1_PCIE_LC_CNTL5                                                   
#define ixD2F1_PCIE_LC_CNTL6                                                    0xbb
#define                                            0
#define ixD2F1_PCIE_LC_TRAINING_CNTL                                            0xa1
# mmBIF_CLOCKS_BITS0x1489
#definedefine                                                       
#define ixD2F1_PCIE_LC_SPEED_CNTL                                               0xa4
#define ixD2F1_PCIE_LC_CDR_CNTL                                                 0xb3
#define ixD2F1_PCIE_LC_LANE_CNTL                                                0xb4
#define ixD2F1_PCIE_LC_FORCE_COEFF                                              0xb8
#define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
#define                                        
ixD2F1_PCIE_LC_STATE0                                                   
#define ixD2F1_PCIE_LC_STATE1                                                   0xa6
#define ixD2F1_PCIE_LC_STATE2                                                   0xa7define                                                         
#define ixD2F1_PCIE_LC_STATE3                                                   0xa8
#define ixD2F1_PCIE_LC_STATE4                                                   0xa9
--> --------------------

--> maximum size reached

--> --------------------

Messung V0.5
C=93 H=91 G=91

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Beweissystem der NASA

Beweissystem Isabelle

NIST Cobol Testsuite

Cephes Mathematical Library

Wiener Entwicklungsmethode

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