/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef _dcn_1_0_OFFSET_HEADER#define _dcn_1_0_OFFSET_HEADER// addressBlock: dce_dc_hda_azcontroller_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azendpoint_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azinputendpoint_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azroot_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azstream0_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azstream1_azdec // base address: 0x1300020 // addressBlock: dce_dc_hda_azstream2_azdec // base address: 0x1300040 // addressBlock: dce_dc_hda_azstream3_azdec // base address: 0x1300060 // addressBlock: dce_dc_hda_azstream4_azdec // base address: 0x1300080 // addressBlock: dce_dc_hda_azstream5_azdec // base address: 0x13000a0 // addressBlock: dce_dc_hda_azstream6_azdec // base address: 0x13000c0 // addressBlock: dce_dc_hda_azstream7_azdec // base address: 0x13000e0 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] // base address: 0x48 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0#define mmVGA_MEM_READ_PAGE_ADDR 0x0001#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] // base address: 0x3b4 #define mmCRTC8_IDX 0x002d#define mmCRTC8_IDX_BASE_IDX 1#define mmCRTC8_DATA 0x002d#define mmCRTC8_DATA_BASE_IDX 1#define mmGENFC_WT 0x002e#define mmGENFC_WT_BASE_IDX 1#define mmGENS1 0x002e#define mmGENS1_BASE_IDX 1#define mmATTRDW 0x0030#define mmATTRDW_BASE_IDX 1#define mmATTRX 0x0030#define mmATTRX_BASE_IDX 1#define mmATTRDR 0x0030#define mmATTRDR_BASE_IDX 1#define mmGENMO_WT 0x0030#define mmGENMO_WT_BASE_IDX 1#define mmGENS0 0x0030#define mmGENS0_BASE_IDX 1#define mmGENENB 0x0030#define mmGENENB_BASE_IDX 1#define mmSEQ8_IDX 0x0031#define mmSEQ8_IDX_BASE_IDX 1#define mmSEQ8_DATA 0x0031#define mmSEQ8_DATA_BASE_IDX 1#define mmDAC_MASK 0x0031#define mmDAC_MASK_BASE_IDX 1#define mmDAC_R_INDEX 0x0031#define mmDAC_R_INDEX_BASE_IDX 1#define mmDAC_W_INDEX 0x0032#define mmDAC_W_INDEX_BASE_IDX 1#define mmDAC_DATA 0x0032#define mmDAC_DATA_BASE_IDX 1#define mmGENFC_RD 0x0032#define mmGENFC_RD_BASE_IDX 1#define mmGENMO_RD 0x0033#define mmGENMO_RD_BASE_IDX 1#define mmGRPH8_IDX 0x0033#define mmGRPH8_IDX_BASE_IDX 1#define mmGRPH8_DATA 0x0033#define mmGRPH8_DATA_BASE_IDX 1#define mmCRTC8_IDX_1 0x0035#define mmCRTC8_IDX_1_BASE_IDX 1#define mmCRTC8_DATA_1 0x0035#define mmCRTC8_DATA_1_BASE_IDX 1#define mmGENFC_WT_1 0x0036#define mmGENFC_WT_1_BASE_IDX 1#define mmGENS1_1 0x0036#define mmGENS1_1_BASE_IDX 1// addressBlock: dce_dc_hda_azcontroller_azdec // base address: 0x0 #define mmCORB_WRITE_POINTER 0x0000#define mmCORB_WRITE_POINTER_BASE_IDX 0#define mmCORB_READ_POINTER 0x0000#define mmCORB_READ_POINTER_BASE_IDX 0#define mmCORB_CONTROL 0x0001#define mmCORB_CONTROL_BASE_IDX 0#define mmCORB_STATUS 0x0001#define mmCORB_STATUS_BASE_IDX 0#define mmCORB_SIZE 0x0001#define mmCORB_SIZE_BASE_IDX 0#define mmRIRB_LOWER_BASE_ADDRESS 0x0002#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmRIRB_UPPER_BASE_ADDRESS 0x0003#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmRIRB_WRITE_POINTER 0x0004#define mmRIRB_WRITE_POINTER_BASE_IDX 0#define mmRESPONSE_INTERRUPT_COUNT 0x0004#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0#define mmRIRB_CONTROL 0x0005#define mmRIRB_CONTROL_BASE_IDX 0#define mmRIRB_STATUS 0x0005#define mmRIRB_STATUS_BASE_IDX 0#define mmRIRB_SIZE 0x0005#define mmRIRB_SIZE_BASE_IDX 0#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0#define mmIMMEDIATE_COMMAND_STATUS 0x0008#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azendpoint_azdec // base address: 0x0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0// addressBlock: dce_dc_hda_azinputendpoint_azdec // base address: 0x0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0// addressBlock: dce_dc_hda_azroot_azdec // base address: 0x0 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0// addressBlock: dce_dc_hda_azstream0_azdec // base address: 0x0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream1_azdec // base address: 0x20 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream2_azdec // base address: 0x40 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream3_azdec // base address: 0x60 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream4_azdec // base address: 0x80 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream5_azdec // base address: 0xa0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream6_azdec // base address: 0xc0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_hda_azstream7_azdec // base address: 0xe0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] // base address: 0x48 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 // addressBlock: dce_dc_mmhubbub_vga_dispdec // base address: 0x0 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 #define mmVGA_RENDER_CONTROL 0x0000#define mmVGA_RENDER_CONTROL_BASE_IDX 1#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1#define mmVGA_MODE_CONTROL 0x0002#define mmVGA_MODE_CONTROL_BASE_IDX 1#define mmVGA_SURFACE_PITCH_SELECT 0x0003#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1#define mmVGA_MEMORY_BASE_ADDRESS 0x0004#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1#define mmVGA_HDP_CONTROL 0x000a#define mmVGA_HDP_CONTROL_BASE_IDX 1#define mmVGA_CACHE_CONTROL 0x000b#define mmVGA_CACHE_CONTROL_BASE_IDX 1#define mmD1VGA_CONTROL 0x000c#define mmD1VGA_CONTROL_BASE_IDX 1#define mmD2VGA_CONTROL 0x000e#define mmD2VGA_CONTROL_BASE_IDX 1#define mmVGA_STATUS 0x0010#define mmVGA_STATUS_BASE_IDX 1#define mmVGA_INTERRUPT_CONTROL 0x0011#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1#define mmVGA_STATUS_CLEAR 0x0012#define mmVGA_STATUS_CLEAR_BASE_IDX 1#define mmVGA_INTERRUPT_STATUS 0x0013#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1#define mmVGA_MAIN_CONTROL 0x0014#define mmVGA_MAIN_CONTROL_BASE_IDX 1#define mmVGA_TEST_CONTROL 0x0015#define mmVGA_TEST_CONTROL_BASE_IDX 1#define mmVGA_QOS_CTRL 0x0018#define mmVGA_QOS_CTRL_BASE_IDX 1//#define mmVGA_CRTC8_IDX 0x002d //#define mmVGA_CRTC8_DATA 0x002d //#define mmVGA_GENFC_WT 0x002e //#define mmVGA_GENS1 0x002e //#define mmVGA_ATTRDW 0x0030 //#define mmVGA_ATTRX 0x0030 //#define mmVGA_ATTRDR 0x0030 //#define mmVGA_GENMO_WT 0x0030 //#define mmVGA_GENS0 0x0030 //#define mmVGA_GENENB 0x0030 //#define mmVGA_SEQ8_IDX 0x0031 //#define mmVGA_SEQ8_DATA 0x0031 //#define mmVGA_DAC_MASK 0x0031 //#define mmVGA_DAC_R_INDEX 0x0031 //#define mmVGA_DAC_W_INDEX 0x0032 //#define mmVGA_DAC_DATA 0x0032 //#define mmVGA_GENFC_RD 0x0032 //#define mmVGA_GENMO_RD 0x0033 //#define mmVGA_GRPH8_IDX 0x0033 //#define mmVGA_GRPH8_DATA 0x0033 //#define mmVGA_CRTC8_IDX_1 0x0035 //#define mmVGA_CRTC8_DATA_1 0x0035 //#define mmVGA_GENFC_WT_1 0x0036 //#define mmVGA_GENS1_1 0x0036 #define mmD3VGA_CONTROL 0x0038#define mmD3VGA_CONTROL_BASE_IDX 1#define mmD4VGA_CONTROL 0x0039#define mmD4VGA_CONTROL_BASE_IDX 1#define mmD5VGA_CONTROL 0x003a#define mmD5VGA_CONTROL_BASE_IDX 1#define mmD6VGA_CONTROL 0x003b#define mmD6VGA_CONTROL_BASE_IDX 1#define mmVGA_SOURCE_SELECT 0x003c#define mmVGA_SOURCE_SELECT_BASE_IDX 1// addressBlock: dce_dc_dccg_dccg_dispdec // base address: 0x0 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmDP_DTO_DBUF_EN 0x0044#define mmDP_DTO_DBUF_EN_BASE_IDX 1#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmREFCLK_CNTL 0x0049#define mmREFCLK_CNTL_BASE_IDX 1#define mmMIPI_CLK_CNTL 0x004a#define mmMIPI_CLK_CNTL_BASE_IDX 1#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmDCCG_PERFMON_CNTL2 0x004e#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmDCCG_CBUS_WRCMD_DELAY 0x0050#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1#define mmDCCG_DS_DTO_INCR 0x0053#define mmDCCG_DS_DTO_INCR_BASE_IDX 1#define mmDCCG_DS_DTO_MODULO 0x0054#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1#define mmDCCG_DS_CNTL 0x0055#define mmDCCG_DS_CNTL_BASE_IDX 1#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1#define mmSYMCLKG_CLOCK_ENABLE 0x0057#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1#define mmDPREFCLK_CNTL 0x0058#define mmDPREFCLK_CNTL_BASE_IDX 1#define mmAOMCLK0_CNTL 0x0059#define mmAOMCLK0_CNTL_BASE_IDX 1#define mmAOMCLK1_CNTL 0x005a#define mmAOMCLK1_CNTL_BASE_IDX 1#define mmAOMCLK2_CNTL 0x005b#define mmAOMCLK2_CNTL_BASE_IDX 1#define mmDCCG_AUDIO_DTO2_PHASE 0x005c#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1#define mmDCCG_AUDIO_DTO2_MODULO 0x005d#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1#define mmDCE_VERSION 0x005e#define mmDCE_VERSION_BASE_IDX 1#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmDCCG_GTC_CNTL 0x0060#define mmDCCG_GTC_CNTL_BASE_IDX 1#define mmDCCG_GTC_DTO_INCR 0x0061#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1#define mmDCCG_GTC_DTO_MODULO 0x0062#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1#define mmDCCG_GTC_CURRENT 0x0063#define mmDCCG_GTC_CURRENT_BASE_IDX 1#define mmMIPI_DTO_CNTL 0x0065#define mmMIPI_DTO_CNTL_BASE_IDX 1#define mmMIPI_DTO_PHASE 0x0066#define mmMIPI_DTO_PHASE_BASE_IDX 1#define mmMIPI_DTO_MODULO 0x0067#define mmMIPI_DTO_MODULO_BASE_IDX 1#define mmDAC_CLK_ENABLE 0x0068#define mmDAC_CLK_ENABLE_BASE_IDX 1#define mmDVO_CLK_ENABLE 0x0069#define mmDVO_CLK_ENABLE_BASE_IDX 1#define mmAVSYNC_COUNTER_WRITE 0x006a#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1#define mmAVSYNC_COUNTER_CONTROL 0x006b#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1#define mmAVSYNC_COUNTER_READ 0x006f#define mmAVSYNC_COUNTER_READ_BASE_IDX 1#define mmMILLISECOND_TIME_BASE_DIV 0x0070#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1#define mmDCCG_PERFMON_CNTL 0x0073#define mmDCCG_PERFMON_CNTL_BASE_IDX 1#define mmDCCG_GATE_DISABLE_CNTL 0x0074#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmDCCG_CAC_STATUS 0x0077#define mmDCCG_CAC_STATUS_BASE_IDX 1#define mmPIXCLK1_RESYNC_CNTL 0x0078#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1#define mmPIXCLK2_RESYNC_CNTL 0x0079#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1#define mmPIXCLK0_RESYNC_CNTL 0x007a#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1#define mmMICROSECOND_TIME_BASE_DIV 0x007b#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1#define mmDCCG_GATE_DISABLE_CNTL2 0x007c#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1#define mmDCCG_DISP_CNTL_REG 0x007f#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1#define mmOTG0_PIXEL_RATE_CNTL 0x0080#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDP_DTO0_PHASE 0x0081#define mmDP_DTO0_PHASE_BASE_IDX 1#define mmDP_DTO0_MODULO 0x0082#define mmDP_DTO0_MODULO_BASE_IDX 1#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1#define mmOTG1_PIXEL_RATE_CNTL 0x0084#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDP_DTO1_PHASE 0x0085#define mmDP_DTO1_PHASE_BASE_IDX 1#define mmDP_DTO1_MODULO 0x0086#define mmDP_DTO1_MODULO_BASE_IDX 1#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1#define mmOTG2_PIXEL_RATE_CNTL 0x0088#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDP_DTO2_PHASE 0x0089#define mmDP_DTO2_PHASE_BASE_IDX 1#define mmDP_DTO2_MODULO 0x008a#define mmDP_DTO2_MODULO_BASE_IDX 1#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1#define mmOTG3_PIXEL_RATE_CNTL 0x008c#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDP_DTO3_PHASE 0x008d#define mmDP_DTO3_PHASE_BASE_IDX 1#define mmDP_DTO3_MODULO 0x008e#define mmDP_DTO3_MODULO_BASE_IDX 1#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1#define mmOTG4_PIXEL_RATE_CNTL 0x0090#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDP_DTO4_PHASE 0x0091#define mmDP_DTO4_PHASE_BASE_IDX 1#define mmDP_DTO4_MODULO 0x0092#define mmDP_DTO4_MODULO_BASE_IDX 1#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1#define mmOTG5_PIXEL_RATE_CNTL 0x0094#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDP_DTO5_PHASE 0x0095#define mmDP_DTO5_PHASE_BASE_IDX 1#define mmDP_DTO5_MODULO 0x0096#define mmDP_DTO5_MODULO_BASE_IDX 1#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1#define mmSYMCLKA_CLOCK_ENABLE 0x00a0#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1#define mmSYMCLKB_CLOCK_ENABLE 0x00a1#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1#define mmSYMCLKC_CLOCK_ENABLE 0x00a2#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1#define mmSYMCLKD_CLOCK_ENABLE 0x00a3#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1#define mmSYMCLKE_CLOCK_ENABLE 0x00a4#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1#define mmSYMCLKF_CLOCK_ENABLE 0x00a5#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1#define mmDCCG_SOFT_RESET 0x00a6#define mmDCCG_SOFT_RESET_BASE_IDX 1#define mmDVOACLKD_CNTL 0x00a8#define mmDVOACLKD_CNTL_BASE_IDX 1#define mmDVOACLKC_MVP_CNTL 0x00a9#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1#define mmDVOACLKC_CNTL 0x00aa#define mmDVOACLKC_CNTL_BASE_IDX 1#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1#define mmDCCG_AUDIO_DTO1_MODULE 0x00af#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1#define mmDCCG_VSYNC_CNT_CTRL 0x00b8#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1#define mmDCCG_TEST_CLK_SEL 0x00be#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1// addressBlock: dce_dc_dccg_dccg_dfs_dispdec // base address: 0x0 #define mmDENTIST_DISPCLK_CNTL 0x0064#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec // base address: 0x0 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2#define mmDC_PERFMON0_PERFMON_CNTL 0x0003#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2#define mmDC_PERFMON0_PERFMON_HI 0x0007#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2#define mmDC_PERFMON0_PERFMON_LOW 0x0008#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec // base address: 0x30 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2#define mmDC_PERFMON1_PERFMON_CNTL 0x000f#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2#define mmDC_PERFMON1_PERFMON_HI 0x0013#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2#define mmDC_PERFMON1_PERFMON_LOW 0x0014#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2// addressBlock: dce_dc_dccg_dccg_pll_dispdec // base address: 0x0 #define mmPLL_MACRO_CNTL_RESERVED0 0x0018#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2#define mmPLL_MACRO_CNTL_RESERVED1 0x0019#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2#define mmPLL_MACRO_CNTL_RESERVED2 0x001a#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2#define mmPLL_MACRO_CNTL_RESERVED3 0x001b
Messung V0.5 C=91 H=100 G=95
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