Quelle  gfx_8_0_enum.h   Sprache: C

/*
 * GFX_8_0 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef GFX_8_0_ENUM_H
#define GFX_8_0_ENUM_H

typedef enum SurfaceNumber {
 NUMBER_UNORM                                     = 0x0,
 NUMBER_SNORM                                     = 0x1,
 NUMBER_USCALED                                   = 0x2,
 NUMBER_SSCALED                                   = 0x3,
 NUMBER_UINT                                      = 0x4,
 NUMBER_SINT                                      = 0x5,
 NUMBER_SRGB                                      = 0x6,
 NUMBER_FLOAT                                     = 0x7,
} SurfaceNumber;
typedef enum SurfaceSwap {
 SWAP_STD                                         = 0x0,
 SWAP_ALT                                         = 0x1,
 SWAP_STD_REV                                     = 0x2,
 SWAP_ALT_REV                                     = 0x3,
} SurfaceSwap;
typedef enum CBMode {
 CB_DISABLE                                       = 0x0,
 CB_NORMAL                                        = 0x1,
 CB_ELIMINATE_FAST_CLEAR                          = 0x2,
 CB_RESOLVE                                       = 0x3,
 CB_DECOMPRESS                                    = 0x4,
 CB_FMASK_DECOMPRESS                              = 0x5,
 CB_DCC_DECOMPRESS                                = 0x6,
} CBMode;
typedef enum RoundMode {
 ROUND_BY_HALF                                    = 0x0,
 ROUND_TRUNCATE                                   = 0x1,
} RoundMode;
typedef enum SourceFormat {
 EXPORT_4C_32BPC                                  = 0x0,
 EXPORT_4C_16BPC                                  = 0x1,
 EXPORT_2C_32BPC_GR                               = 0x2,
 EXPORT_2C_32BPC_AR                               = 0x3,
} SourceFormat;
typedef enum BlendOp {
 BLEND_ZERO                                       = 0x0,
 BLEND_ONE                                        = 0x1,
 BLEND_SRC_COLOR                                  = 0x2,
 BLEND_ONE_MINUS_SRC_COLOR                        = 0x3,
 BLEND_SRC_ALPHA                                  = 0x4,
 BLEND_ONE_MINUS_SRC_ALPHA                        = 0x5,
 BLEND_DST_ALPHA                                  = 0x6,
 BLEND_ONE_MINUS_DST_ALPHA                        = 0x7,
 BLEND_DST_COLOR                                  = 0x8,
 BLEND_ONE_MINUS_DST_COLOR                        = 0x9,
 BLEND_SRC_ALPHA_SATURATE                         = 0xa,
 BLEND_BOTH_SRC_ALPHA                             = 0xb,
 BLEND_BOTH_INV_SRC_ALPHA                         = 0xc,
 BLEND_CONSTANT_COLOR                             = 0xd,
 BLEND_ONE_MINUS_CONSTANT_COLOR                   = 0xe,
 BLEND_SRC1_COLOR                                 = 0xf,
 BLEND_INV_SRC1_COLOR                             = 0x10,
 BLEND_SRC1_ALPHA                                 = 0x11,
 BLEND_INV_SRC1_ALPHA                             = 0x12,
 BLEND_CONSTANT_ALPHA                             = 0x13,
 BLEND_ONE_MINUS_CONSTANT_ALPHA                   = 0x14,
} BlendOp;
typedef enum CombFunc {
 COMB_DST_PLUS_SRC                                = 0x0,
 COMB_SRC_MINUS_DST                               = 0x1,
 COMB_MIN_DST_SRC                                 = 0x2,
 COMB_MAX_DST_SRC                                 = 0x3,
 COMB_DST_MINUS_SRC                               = 0x4,
} CombFunc;
typedef enum BlendOpt {
 FORCE_OPT_AUTO                                   = 0x0,
 FORCE_OPT_DISABLE                                = 0x1,
 FORCE_OPT_ENABLE_IF_SRC_A_0                      = 0x2,
 FORCE_OPT_ENABLE_IF_SRC_RGB_0                    = 0x3,
 FORCE_OPT_ENABLE_IF_SRC_ARGB_0                   = 0x4,
 FORCE_OPT_ENABLE_IF_SRC_A_1                      = 0x5,
 FORCE_OPT_ENABLE_IF_SRC_RGB_1                    = 0x6,
 FORCE_OPT_ENABLE_IF_SRC_ARGB_1                   = 0x7,
} BlendOpt;
typedef enum CmaskCode {
 CMASK_CLR00_F0                                   = 0x0,
 CMASK_CLR00_F1                                   = 0x1,
 CMASK_CLR00_F2                                   = 0x2,
 CMASK_CLR00_FX                                   = 0x3,
 CMASK_CLR01_F0                                   = 0x4,
 CMASK_CLR01_F1                                   = 0x5,
 CMASK_CLR01_F2                                   = 0x6,
 CMASK_CLR01_FX                                   = 0x7,
 CMASK_CLR10_F0                                   = 0x8,
 CMASK_CLR10_F1                                   = 0x9,
 CMASK_CLR10_F2                                   = 0xa,
 CMASK_CLR10_FX                                   = 0xb,
 CMASK_CLR11_F0                                   = 0xc,
 CMASK_CLR11_F1                                   = 0xd,
 CMASK_CLR11_F2                                   = 0xe,
 CMASK_CLR11_FX                                   = 0xf,
} CmaskCode;
typedef enum CmaskAddr {
 CMASK_ADDR_TILED                                 = 0x0,
 CMASK_ADDR_LINEAR                                = 0x1,
 CMASK_ADDR_COMPATIBLE                            = 0x2,
} CmaskAddr;
typedef enum CBPerfSel {
 CB_PERF_SEL_NONE                                 = 0x0,
 CB_PERF_SEL_BUSY                                 = 0x1,
 CB_PERF_SEL_CORE_SCLK_VLD                        = 0x2,
 CB_PERF_SEL_REG_SCLK0_VLD                        = 0x3,
 CB_PERF_SEL_REG_SCLK1_VLD                        = 0x4,
 CB_PERF_SEL_DRAWN_QUAD                           = 0x5,
 CB_PERF_SEL_DRAWN_PIXEL                          = 0x6,
 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT                  = 0x7,
 CB_PERF_SEL_DRAWN_TILE                           = 0x8,
 CB_PERF_SEL_DB_CB_TILE_VALID_READY               = 0x9,
 CB_PERF_SEL_DB_CB_TILE_VALID_READYB              = 0xa,
 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY              = 0xb,
 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB             = 0xc,
 CB_PERF_SEL_CM_FC_TILE_VALID_READY               = 0xd,
 CB_PERF_SEL_CM_FC_TILE_VALID_READYB              = 0xe,
 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY              = 0xf,
 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB             = 0x10,
 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY          = 0x11,
 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB         = 0x12,
 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY              = 0x13,
 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB             = 0x14,
 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY             = 0x15,
 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB            = 0x16,
 CB_PERF_SEL_LQUAD_NO_TILE                        = 0x17,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R          = 0x18,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR         = 0x19,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR         = 0x1a,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR       = 0x1b,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR     = 0x1c,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT    = 0x1f,
 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID         = 0x20,
 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK      = 0x22,
 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL         = 0x23,
 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY            = 0x24,
 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB           = 0x25,
 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY           = 0x26,
 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB          = 0x27,
 CB_PERF_SEL_FOP_IN_VALID_READY                   = 0x28,
 CB_PERF_SEL_FOP_IN_VALID_READYB                  = 0x29,
 CB_PERF_SEL_FOP_IN_VALIDB_READY                  = 0x2a,
 CB_PERF_SEL_FOP_IN_VALIDB_READYB                 = 0x2b,
 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY           = 0x2c,
 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB          = 0x2d,
 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY          = 0x2e,
 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB         = 0x2f,
 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY            = 0x30,
 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB           = 0x31,
 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY           = 0x32,
 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB          = 0x33,
 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY            = 0x34,
 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB           = 0x35,
 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY           = 0x36,
 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB          = 0x37,
 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY        = 0x38,
 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB       = 0x39,
 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY       = 0x3a,
 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB      = 0x3b,
 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY         = 0x3c,
 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB        = 0x3d,
 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY        = 0x3e,
 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB       = 0x3f,
 CB_PERF_SEL_CC_BC_CS_FRAG_VALID                  = 0x40,
 CB_PERF_SEL_CM_CACHE_HIT                         = 0x41,
 CB_PERF_SEL_CM_CACHE_TAG_MISS                    = 0x42,
 CB_PERF_SEL_CM_CACHE_SECTOR_MISS                 = 0x43,
 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL            = 0x44,
 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL           = 0x48,
 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL          = 0x49,
 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL            = 0x4a,
 CB_PERF_SEL_CM_CACHE_STALL                       = 0x4b,
 CB_PERF_SEL_CM_CACHE_FLUSH                       = 0x4c,
 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED                = 0x4d,
 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED             = 0x4e,
 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED       = 0x4f,
 CB_PERF_SEL_FC_CACHE_HIT                         = 0x50,
 CB_PERF_SEL_FC_CACHE_TAG_MISS                    = 0x51,
 CB_PERF_SEL_FC_CACHE_SECTOR_MISS                 = 0x52,
 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL            = 0x53,
 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL           = 0x57,
 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL          = 0x58,
 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL            = 0x59,
 CB_PERF_SEL_FC_CACHE_STALL                       = 0x5a,
 CB_PERF_SEL_FC_CACHE_FLUSH                       = 0x5b,
 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED                = 0x5c,
 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED             = 0x5d,
 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x5e,
 CB_PERF_SEL_CC_CACHE_HIT                         = 0x5f,
 CB_PERF_SEL_CC_CACHE_TAG_MISS                    = 0x60,
 CB_PERF_SEL_CC_CACHE_SECTOR_MISS                 = 0x61,
 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL            = 0x62,
 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL           = 0x66,
 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL          = 0x67,
 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL            = 0x68,
 CB_PERF_SEL_CC_CACHE_STALL                       = 0x69,
 CB_PERF_SEL_CC_CACHE_FLUSH                       = 0x6a,
 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED                = 0x6b,
 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED             = 0x6c,
 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x6d,
 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION        = 0x6e,
 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC      = 0x6f,
 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY             = 0x70,
 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB            = 0x71,
 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY            = 0x72,
 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB           = 0x73,
 CB_PERF_SEL_CM_MC_WRITE_REQUEST                  = 0x74,
 CB_PERF_SEL_FC_MC_WRITE_REQUEST                  = 0x75,
 CB_PERF_SEL_CC_MC_WRITE_REQUEST                  = 0x76,
 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x77,
 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x78,
 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x79,
 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY             = 0x7a,
 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB            = 0x7b,
 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY            = 0x7c,
 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB           = 0x7d,
 CB_PERF_SEL_CM_MC_READ_REQUEST                   = 0x7e,
 CB_PERF_SEL_FC_MC_READ_REQUEST                   = 0x7f,
 CB_PERF_SEL_CC_MC_READ_REQUEST                   = 0x80,
 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT        = 0x81,
 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT        = 0x82,
 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT        = 0x83,
 CB_PERF_SEL_CM_TQ_FULL                           = 0x84,
 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL      = 0x85,
 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL              = 0x86,
 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL              = 0x87,
 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL   = 0x88,
 CB_PERF_SEL_FOP_FMASK_RAW_STALL                  = 0x89,
 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL               = 0x8a,
 CB_PERF_SEL_CC_SF_FULL                           = 0x8b,
 CB_PERF_SEL_CC_RB_FULL                           = 0x8c,
 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL     = 0x8d,
 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL      = 0x8e,
 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL             = 0x8f,
 CB_PERF_SEL_EVENT                                = 0x90,
 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS                 = 0x91,
 CB_PERF_SEL_EVENT_CONTEXT_DONE                   = 0x92,
 CB_PERF_SEL_EVENT_CACHE_FLUSH                    = 0x93,
 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT   = 0x94,
 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT      = 0x95,
 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS       = 0x96,
 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META          = 0x97,
 CB_PERF_SEL_CC_SURFACE_SYNC                      = 0x98,
 CB_PERF_SEL_CMASK_READ_DATA_0xC                  = 0x99,
 CB_PERF_SEL_CMASK_READ_DATA_0xD                  = 0x9a,
 CB_PERF_SEL_CMASK_READ_DATA_0xE                  = 0x9b,
 CB_PERF_SEL_CMASK_READ_DATA_0xF                  = 0x9c,
 CB_PERF_SEL_CMASK_WRITE_DATA_0xC                 = 0x9d,
 CB_PERF_SEL_CMASK_WRITE_DATA_0xD                 = 0x9e,
 CB_PERF_SEL_CMASK_WRITE_DATA_0xE                 = 0x9f,
 CB_PERF_SEL_CMASK_WRITE_DATA_0xF                 = 0xa0,
 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT              = 0xa1,
 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT         = 0xa2,
 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT      = 0xa3,
 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE    = 0xa4,
 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE   = 0xa5,
 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE   = 0xa6,
 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE   = 0xa7,
 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE   = 0xa8,
 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE   = 0xa9,
 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE   = 0xaa,
 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE   = 0xab,
 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE     = 0xac,
 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE    = 0xad,
 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE    = 0xae,
 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE    = 0xaf,
 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE    = 0xb0,
 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE    = 0xb1,
 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE    = 0xb2,
 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE    = 0xb3,
 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT                = 0xb4,
 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS               = 0xb5,
 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS               = 0xb6,
 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS               = 0xb7,
 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS               = 0xb8,
 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS               = 0xb9,
 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS               = 0xba,
 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT              = 0xbb,
 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS             = 0xbc,
 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS             = 0xbd,
 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS             = 0xbe,
 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS             = 0xbf,
 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS             = 0xc0,
 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS             = 0xc1,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_0                = 0xc2,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_1                = 0xc3,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_2                = 0xc4,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_3                = 0xc5,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_4                = 0xc6,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_5                = 0xc7,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_6                = 0xc8,
 CB_PERF_SEL_QUAD_READS_FRAGMENT_7                = 0xc9,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0               = 0xca,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1               = 0xcb,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2               = 0xcc,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3               = 0xcd,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4               = 0xce,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5               = 0xcf,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6               = 0xd0,
 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7               = 0xd1,
 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST         = 0xd2,
 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS          = 0xd3,
 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS        = 0xd4,
 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED       = 0xd7,
 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST      = 0xd8,
 CB_PERF_SEL_DRAWN_BUSY                           = 0xd9,
 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY              = 0xda,
 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY               = 0xdb,
 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY               = 0xdc,
 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY               = 0xdd,
 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
 CB_PERF_SEL_FC_SEQUENCER_CLEAR                   = 0xdf,
 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR    = 0xe0,
 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS        = 0xe1,
 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL             = 0xe3,
 CB_PERF_SEL_FC_DOC_IS_STALLED                    = 0xe4,
 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED             = 0xe5,
 CB_PERF_SEL_FC_DOC_MRTS_COMBINED                 = 0xe6,
 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS                = 0xe7,
 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT                 = 0xe8,
 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS                = 0xe9,
 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT                 = 0xea,
 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL         = 0xeb,
 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR            = 0xec,
 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS           = 0xed,
 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS           = 0xee,
 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS           = 0xef,
 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS     = 0xf0,
 CB_PERF_SEL_FC_DCC_CACHE_HIT                     = 0xf1,
 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS                = 0xf2,
 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS             = 0xf3,
 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL        = 0xf4,
 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL       = 0xf8,
 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL      = 0xf9,
 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL        = 0xfa,
 CB_PERF_SEL_FC_DCC_CACHE_STALL                   = 0xfb,
 CB_PERF_SEL_FC_DCC_CACHE_FLUSH                   = 0xfc,
 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED            = 0xfd,
 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED         = 0xfe,
 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED   = 0xff,
 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT             = 0x100,
 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST              = 0x101,
 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT   = 0x102,
 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST               = 0x103,
 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT    = 0x104,
 CB_PERF_SEL_CC_DCC_RDREQ_STALL                   = 0x105,
 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN            = 0x106,
 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT           = 0x107,
 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN              = 0x108,
 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT             = 0x109,
 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR              = 0x10a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1     = 0x10b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1       = 0x11a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2       = 0x11f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3       = 0x124,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x15c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x15d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x163,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x164,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x16b,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x16c,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x172,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x173,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1        = 0x174,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2        = 0x175,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3        = 0x176,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4        = 0x177,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5        = 0x178,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6        = 0x179,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7        = 0x17a,
 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED       = 0x17b,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1           = 0x17c,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1           = 0x17d,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2           = 0x17e,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3           = 0x17f,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1           = 0x180,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2           = 0x181,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3           = 0x182,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4           = 0x183,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5           = 0x184,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1           = 0x185,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2           = 0x186,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3           = 0x187,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4           = 0x188,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5           = 0x189,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6           = 0x18a,
 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7           = 0x18b,
} CBPerfSel;
typedef enum CBPerfOpFilterSel {
 CB_PERF_OP_FILTER_SEL_WRITE_ONLY                 = 0x0,
 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION          = 0x1,
 CB_PERF_OP_FILTER_SEL_RESOLVE                    = 0x2,
 CB_PERF_OP_FILTER_SEL_DECOMPRESS                 = 0x3,
 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS           = 0x4,
 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR       = 0x5,
} CBPerfOpFilterSel;
typedef enum CBPerfClearFilterSel {
 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR                = 0x0,
 CB_PERF_CLEAR_FILTER_SEL_CLEAR                   = 0x1,
} CBPerfClearFilterSel;
typedef enum CP_RING_ID {
 RINGID0                                          = 0x0,
 RINGID1                                          = 0x1,
 RINGID2                                          = 0x2,
 RINGID3                                          = 0x3,
} CP_RING_ID;
typedef enum CP_PIPE_ID {
 PIPE_ID0                                         = 0x0,
 PIPE_ID1                                         = 0x1,
 PIPE_ID2                                         = 0x2,
 PIPE_ID3                                         = 0x3,
} CP_PIPE_ID;
typedef enum CP_ME_ID {
 ME_ID0                                           = 0x0,
 ME_ID1                                           = 0x1,
 ME_ID2                                           = 0x2,
 ME_ID3                                           = 0x3,
} CP_ME_ID;
typedef enum SPM_PERFMON_STATE {
 STRM_PERFMON_STATE_DISABLE_AND_RESET             = 0x0,
 STRM_PERFMON_STATE_START_COUNTING                = 0x1,
 STRM_PERFMON_STATE_STOP_COUNTING                 = 0x2,
 STRM_PERFMON_STATE_RESERVED_3                    = 0x3,
 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM     = 0x4,
 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM        = 0x5,
} SPM_PERFMON_STATE;
typedef enum CP_PERFMON_STATE {
 CP_PERFMON_STATE_DISABLE_AND_RESET               = 0x0,
 CP_PERFMON_STATE_START_COUNTING                  = 0x1,
 CP_PERFMON_STATE_STOP_COUNTING                   = 0x2,
 CP_PERFMON_STATE_RESERVED_3                      = 0x3,
 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM       = 0x4,
 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM          = 0x5,
} CP_PERFMON_STATE;
typedef enum CP_PERFMON_ENABLE_MODE {
 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT              = 0x0,
 CP_PERFMON_ENABLE_MODE_RESERVED_1                = 0x1,
 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE        = 0x2,
 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE       = 0x3,
} CP_PERFMON_ENABLE_MODE;
typedef enum CPG_PERFCOUNT_SEL {
 CPG_PERF_SEL_ALWAYS_COUNT                        = 0x0,
 CPG_PERF_SEL_RBIU_FIFO_FULL                      = 0x1,
 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR             = 0x2,
 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL          = 0x3,
 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT                 = 0x4,
 CPG_PERF_SEL_ME_PARSER_BUSY                      = 0x5,
 CPG_PERF_SEL_COUNT_TYPE0_PACKETS                 = 0x6,
 CPG_PERF_SEL_COUNT_TYPE3_PACKETS                 = 0x7,
 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0x8,
 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS              = 0x9,
 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS          = 0xa,
 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS          = 0xb,
 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ             = 0xc,
 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ            = 0xd,
 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX          = 0xe,
 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS        = 0xf,
 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE        = 0x10,
 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM   = 0x11,
 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY            = 0x12,
 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY            = 0x13,
 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY           = 0x14,
 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ       = 0x15,
 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP        = 0x16,
 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ        = 0x17,
 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX     = 0x18,
 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU          = 0x19,
 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS        = 0x1a,
 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH         = 0x1b,
 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER               = 0x1c,
 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER             = 0x1d,
 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS     = 0x1e,
 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY       = 0x1f,
 CPG_PERF_SEL_DYNAMIC_CLK_VALID                   = 0x20,
 CPG_PERF_SEL_REGISTER_CLK_VALID                  = 0x21,
 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT              = 0x22,
 CPG_PERF_SEL_MIU_READ_REQUEST_SENT               = 0x23,
 CPG_PERF_SEL_CE_STALL_RAM_DUMP                   = 0x24,
 CPG_PERF_SEL_CE_STALL_RAM_WRITE                  = 0x25,
 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO                = 0x26,
 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO             = 0x27,
 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU           = 0x28,
 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ           = 0x29,
 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG          = 0x2a,
 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER              = 0x2b,
 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x2c,
 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS             = 0x2d,
 CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x2e,
 CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x2f,
 CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x30,
} CPG_PERFCOUNT_SEL;
typedef enum CPF_PERFCOUNT_SEL {
 CPF_PERF_SEL_ALWAYS_COUNT                        = 0x0,
 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE      = 0x1,
 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE        = 0x2,
 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS        = 0x3,
 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING          = 0x4,
 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1           = 0x5,
 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2           = 0x6,
 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE         = 0x7,
 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS       = 0x8,
 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR                 = 0x9,
 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR              = 0xa,
 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0xb,
 CPF_PERF_SEL_GRBM_DWORDS_SENT                    = 0xc,
 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID                 = 0xd,
 CPF_PERF_SEL_REGISTER_CLOCK_VALID                = 0xe,
 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND              = 0xf,
 CPF_PERF_SEL_MIU_READ_REQUEST_SEND               = 0x10,
 CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x11,
 CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x12,
 CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x13,
} CPF_PERFCOUNT_SEL;
typedef enum CPC_PERFCOUNT_SEL {
 CPC_PERF_SEL_ALWAYS_COUNT                        = 0x0,
 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE             = 0x1,
 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION           = 0x2,
 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE             = 0x3,
 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE             = 0x4,
 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x5,
 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY        = 0x6,
 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF   = 0x7,
 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ         = 0x8,
 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ          = 0x9,
 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE         = 0xa,
 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ          = 0xb,
 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF     = 0xc,
 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE          = 0xd,
 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY        = 0xe,
 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF   = 0xf,
 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ         = 0x10,
 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ          = 0x11,
 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE         = 0x12,
 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ          = 0x13,
 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF     = 0x14,
 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE          = 0x15,
 CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x16,
 CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x17,
 CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x18,
} CPC_PERFCOUNT_SEL;
typedef enum CP_ALPHA_TAG_RAM_SEL {
 CPG_TAG_RAM                                      = 0x0,
 CPC_TAG_RAM                                      = 0x1,
 CPF_TAG_RAM                                      = 0x2,
 RSV_TAG_RAM                                      = 0x3,
} CP_ALPHA_TAG_RAM_SEL;
#define SEM_ECC_ERROR                             0x0
#define SEM_RESERVED                              0x1
#define SEM_FAILED                                0x2
#define SEM_PASSED                                0x3
#define IQ_QUEUE_SLEEP                            0x0
#define IQ_OFFLOAD_RETRY                          0x1
#define IQ_SCH_WAVE_MSG                           0x2
#define IQ_SEM_REARM                              0x3
#define IQ_DEQUEUE_RETRY                          0x4
#define IQ_INTR_TYPE_PQ                           0x0
#define IQ_INTR_TYPE_IB                           0x1
#define IQ_INTR_TYPE_MQD                          0x2
#define VMID_SZ                                   0x4
#define CONFIG_SPACE_START                        0x2000
#define CONFIG_SPACE_END                          0x9fff
#define CONFIG_SPACE1_START                       0x2000
#define CONFIG_SPACE1_END                         0x2bff
#define CONFIG_SPACE2_START                       0x3000
#define CONFIG_SPACE2_END                         0x9fff
#define UCONFIG_SPACE_START                       0xc000
#define UCONFIG_SPACE_END                         0xffff
#define PERSISTENT_SPACE_START                    0x2c00
#define PERSISTENT_SPACE_END                      0x2fff
#define CONTEXT_SPACE_START                       0xa000
#define CONTEXT_SPACE_END                         0xbfff
typedef enum ForceControl {
 FORCE_OFF                                        = 0x0,
 FORCE_ENABLE                                     = 0x1,
 FORCE_DISABLE                                    = 0x2,
 FORCE_RESERVED                                   = 0x3,
} ForceControl;
typedef enum ZSamplePosition {
 Z_SAMPLE_CENTER                                  = 0x0,
 Z_SAMPLE_CENTROID                                = 0x1,
} ZSamplePosition;
typedef enum ZOrder {
 LATE_Z                                           = 0x0,
 EARLY_Z_THEN_LATE_Z                              = 0x1,
 RE_Z                                             = 0x2,
 EARLY_Z_THEN_RE_Z                                = 0x3,
} ZOrder;
typedef enum ZpassControl {
 ZPASS_DISABLE                                    = 0x0,
 ZPASS_SAMPLES                                    = 0x1,
 ZPASS_PIXELS                                     = 0x2,
} ZpassControl;
typedef enum ZModeForce {
 NO_FORCE                                         = 0x0,
 FORCE_EARLY_Z                                    = 0x1,
 FORCE_LATE_Z                                     = 0x2,
 FORCE_RE_Z                                       = 0x3,
} ZModeForce;
typedef enum ZLimitSumm {
 FORCE_SUMM_OFF                                   = 0x0,
 FORCE_SUMM_MINZ                                  = 0x1,
 FORCE_SUMM_MAXZ                                  = 0x2,
 FORCE_SUMM_BOTH                                  = 0x3,
} ZLimitSumm;
typedef enum CompareFrag {
 FRAG_NEVER                                       = 0x0,
 FRAG_LESS                                        = 0x1,
 FRAG_EQUAL                                       = 0x2,
 FRAG_LEQUAL                                      = 0x3,
 FRAG_GREATER                                     = 0x4,
 FRAG_NOTEQUAL                                    = 0x5,
 FRAG_GEQUAL                                      = 0x6,
 FRAG_ALWAYS                                      = 0x7,
} CompareFrag;
typedef enum StencilOp {
 STENCIL_KEEP                                     = 0x0,
 STENCIL_ZERO                                     = 0x1,
 STENCIL_ONES                                     = 0x2,
 STENCIL_REPLACE_TEST                             = 0x3,
 STENCIL_REPLACE_OP                               = 0x4,
 STENCIL_ADD_CLAMP                                = 0x5,
 STENCIL_SUB_CLAMP                                = 0x6,
 STENCIL_INVERT                                   = 0x7,
 STENCIL_ADD_WRAP                                 = 0x8,
 STENCIL_SUB_WRAP                                 = 0x9,
 STENCIL_AND                                      = 0xa,
 STENCIL_OR                                       = 0xb,
 STENCIL_XOR                                      = 0xc,
 STENCIL_NAND                                     = 0xd,
 STENCIL_NOR                                      = 0xe,
 STENCIL_XNOR                                     = 0xf,
} StencilOp;
typedef enum ConservativeZExport {
 EXPORT_ANY_Z                                     = 0x0,
 EXPORT_LESS_THAN_Z                               = 0x1,
 EXPORT_GREATER_THAN_Z                            = 0x2,
 EXPORT_RESERVED                                  = 0x3,
} ConservativeZExport;
typedef enum DbPSLControl {
 PSLC_AUTO                                        = 0x0,
 PSLC_ON_HANG_ONLY                                = 0x1,
 PSLC_ASAP                                        = 0x2,
 PSLC_COUNTDOWN                                   = 0x3,
} DbPSLControl;
typedef enum PerfCounter_Vals {
 DB_PERF_SEL_SC_DB_tile_sends                     = 0x0,
 DB_PERF_SEL_SC_DB_tile_busy                      = 0x1,
 DB_PERF_SEL_SC_DB_tile_stalls                    = 0x2,
 DB_PERF_SEL_SC_DB_tile_events                    = 0x3,
 DB_PERF_SEL_SC_DB_tile_tiles                     = 0x4,
 DB_PERF_SEL_SC_DB_tile_covered                   = 0x5,
 DB_PERF_SEL_hiz_tc_read_starved                  = 0x6,
 DB_PERF_SEL_hiz_tc_write_stall                   = 0x7,
 DB_PERF_SEL_hiz_qtiles_culled                    = 0x8,
 DB_PERF_SEL_his_qtiles_culled                    = 0x9,
 DB_PERF_SEL_DB_SC_tile_sends                     = 0xa,
 DB_PERF_SEL_DB_SC_tile_busy                      = 0xb,
 DB_PERF_SEL_DB_SC_tile_stalls                    = 0xc,
 DB_PERF_SEL_DB_SC_tile_df_stalls                 = 0xd,
 DB_PERF_SEL_DB_SC_tile_tiles                     = 0xe,
 DB_PERF_SEL_DB_SC_tile_culled                    = 0xf,
 DB_PERF_SEL_DB_SC_tile_hier_kill                 = 0x10,
 DB_PERF_SEL_DB_SC_tile_fast_ops                  = 0x11,
 DB_PERF_SEL_DB_SC_tile_no_ops                    = 0x12,
 DB_PERF_SEL_DB_SC_tile_tile_rate                 = 0x13,
 DB_PERF_SEL_DB_SC_tile_ssaa_kill                 = 0x14,
 DB_PERF_SEL_DB_SC_tile_fast_z_ops                = 0x15,
 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops          = 0x16,
 DB_PERF_SEL_SC_DB_quad_sends                     = 0x17,
 DB_PERF_SEL_SC_DB_quad_busy                      = 0x18,
 DB_PERF_SEL_SC_DB_quad_squads                    = 0x19,
 DB_PERF_SEL_SC_DB_quad_tiles                     = 0x1a,
 DB_PERF_SEL_SC_DB_quad_pixels                    = 0x1b,
 DB_PERF_SEL_SC_DB_quad_killed_tiles              = 0x1c,
 DB_PERF_SEL_DB_SC_quad_sends                     = 0x1d,
 DB_PERF_SEL_DB_SC_quad_busy                      = 0x1e,
 DB_PERF_SEL_DB_SC_quad_stalls                    = 0x1f,
 DB_PERF_SEL_DB_SC_quad_tiles                     = 0x20,
 DB_PERF_SEL_DB_SC_quad_lit_quad                  = 0x21,
 DB_PERF_SEL_DB_CB_tile_sends                     = 0x22,
 DB_PERF_SEL_DB_CB_tile_busy                      = 0x23,
 DB_PERF_SEL_DB_CB_tile_stalls                    = 0x24,
 DB_PERF_SEL_SX_DB_quad_sends                     = 0x25,
 DB_PERF_SEL_SX_DB_quad_busy                      = 0x26,
 DB_PERF_SEL_SX_DB_quad_stalls                    = 0x27,
 DB_PERF_SEL_SX_DB_quad_quads                     = 0x28,
 DB_PERF_SEL_SX_DB_quad_pixels                    = 0x29,
 DB_PERF_SEL_SX_DB_quad_exports                   = 0x2a,
 DB_PERF_SEL_SH_quads_outstanding_sum             = 0x2b,
 DB_PERF_SEL_DB_CB_lquad_sends                    = 0x2c,
 DB_PERF_SEL_DB_CB_lquad_busy                     = 0x2d,
 DB_PERF_SEL_DB_CB_lquad_stalls                   = 0x2e,
 DB_PERF_SEL_DB_CB_lquad_quads                    = 0x2f,
 DB_PERF_SEL_tile_rd_sends                        = 0x30,
 DB_PERF_SEL_mi_tile_rd_outstanding_sum           = 0x31,
 DB_PERF_SEL_quad_rd_sends                        = 0x32,
 DB_PERF_SEL_quad_rd_busy                         = 0x33,
 DB_PERF_SEL_quad_rd_mi_stall                     = 0x34,
 DB_PERF_SEL_quad_rd_rw_collision                 = 0x35,
 DB_PERF_SEL_quad_rd_tag_stall                    = 0x36,
 DB_PERF_SEL_quad_rd_32byte_reqs                  = 0x37,
 DB_PERF_SEL_quad_rd_panic                        = 0x38,
 DB_PERF_SEL_mi_quad_rd_outstanding_sum           = 0x39,
 DB_PERF_SEL_quad_rdret_sends                     = 0x3a,
 DB_PERF_SEL_quad_rdret_busy                      = 0x3b,
 DB_PERF_SEL_tile_wr_sends                        = 0x3c,
 DB_PERF_SEL_tile_wr_acks                         = 0x3d,
 DB_PERF_SEL_mi_tile_wr_outstanding_sum           = 0x3e,
 DB_PERF_SEL_quad_wr_sends                        = 0x3f,
 DB_PERF_SEL_quad_wr_busy                         = 0x40,
 DB_PERF_SEL_quad_wr_mi_stall                     = 0x41,
 DB_PERF_SEL_quad_wr_coherency_stall              = 0x42,
 DB_PERF_SEL_quad_wr_acks                         = 0x43,
 DB_PERF_SEL_mi_quad_wr_outstanding_sum           = 0x44,
 DB_PERF_SEL_Tile_Cache_misses                    = 0x45,
 DB_PERF_SEL_Tile_Cache_hits                      = 0x46,
 DB_PERF_SEL_Tile_Cache_flushes                   = 0x47,
 DB_PERF_SEL_Tile_Cache_surface_stall             = 0x48,
 DB_PERF_SEL_Tile_Cache_starves                   = 0x49,
 DB_PERF_SEL_Tile_Cache_mem_return_starve         = 0x4a,
 DB_PERF_SEL_tcp_dispatcher_reads                 = 0x4b,
 DB_PERF_SEL_tcp_prefetcher_reads                 = 0x4c,
 DB_PERF_SEL_tcp_preloader_reads                  = 0x4d,
 DB_PERF_SEL_tcp_dispatcher_flushes               = 0x4e,
 DB_PERF_SEL_tcp_prefetcher_flushes               = 0x4f,
 DB_PERF_SEL_tcp_preloader_flushes                = 0x50,
 DB_PERF_SEL_Depth_Tile_Cache_sends               = 0x51,
 DB_PERF_SEL_Depth_Tile_Cache_busy                = 0x52,
 DB_PERF_SEL_Depth_Tile_Cache_starves             = 0x53,
 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked        = 0x54,
 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall         = 0x55,
 DB_PERF_SEL_Depth_Tile_Cache_misses              = 0x56,
 DB_PERF_SEL_Depth_Tile_Cache_hits                = 0x57,
 DB_PERF_SEL_Depth_Tile_Cache_flushes             = 0x58,
 DB_PERF_SEL_Depth_Tile_Cache_noop_tile           = 0x59,
 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop       = 0x5a,
 DB_PERF_SEL_Depth_Tile_Cache_event               = 0x5b,
 DB_PERF_SEL_Depth_Tile_Cache_tile_frees          = 0x5c,
 DB_PERF_SEL_Depth_Tile_Cache_data_frees          = 0x5d,
 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve   = 0x5e,
 DB_PERF_SEL_Stencil_Cache_misses                 = 0x5f,
 DB_PERF_SEL_Stencil_Cache_hits                   = 0x60,
 DB_PERF_SEL_Stencil_Cache_flushes                = 0x61,
 DB_PERF_SEL_Stencil_Cache_starves                = 0x62,
 DB_PERF_SEL_Stencil_Cache_frees                  = 0x63,
 DB_PERF_SEL_Z_Cache_separate_Z_misses            = 0x64,
 DB_PERF_SEL_Z_Cache_separate_Z_hits              = 0x65,
 DB_PERF_SEL_Z_Cache_separate_Z_flushes           = 0x66,
 DB_PERF_SEL_Z_Cache_separate_Z_starves           = 0x67,
 DB_PERF_SEL_Z_Cache_pmask_misses                 = 0x68,
 DB_PERF_SEL_Z_Cache_pmask_hits                   = 0x69,
 DB_PERF_SEL_Z_Cache_pmask_flushes                = 0x6a,
 DB_PERF_SEL_Z_Cache_pmask_starves                = 0x6b,
 DB_PERF_SEL_Z_Cache_frees                        = 0x6c,
 DB_PERF_SEL_Plane_Cache_misses                   = 0x6d,
 DB_PERF_SEL_Plane_Cache_hits                     = 0x6e,
 DB_PERF_SEL_Plane_Cache_flushes                  = 0x6f,
 DB_PERF_SEL_Plane_Cache_starves                  = 0x70,
 DB_PERF_SEL_Plane_Cache_frees                    = 0x71,
 DB_PERF_SEL_flush_expanded_stencil               = 0x72,
 DB_PERF_SEL_flush_compressed_stencil             = 0x73,
 DB_PERF_SEL_flush_single_stencil                 = 0x74,
 DB_PERF_SEL_planes_flushed                       = 0x75,
 DB_PERF_SEL_flush_1plane                         = 0x76,
 DB_PERF_SEL_flush_2plane                         = 0x77,
 DB_PERF_SEL_flush_3plane                         = 0x78,
 DB_PERF_SEL_flush_4plane                         = 0x79,
 DB_PERF_SEL_flush_5plane                         = 0x7a,
 DB_PERF_SEL_flush_6plane                         = 0x7b,
 DB_PERF_SEL_flush_7plane                         = 0x7c,
 DB_PERF_SEL_flush_8plane                         = 0x7d,
 DB_PERF_SEL_flush_9plane                         = 0x7e,
 DB_PERF_SEL_flush_10plane                        = 0x7f,
 DB_PERF_SEL_flush_11plane                        = 0x80,
 DB_PERF_SEL_flush_12plane                        = 0x81,
 DB_PERF_SEL_flush_13plane                        = 0x82,
 DB_PERF_SEL_flush_14plane                        = 0x83,
 DB_PERF_SEL_flush_15plane                        = 0x84,
 DB_PERF_SEL_flush_16plane                        = 0x85,
 DB_PERF_SEL_flush_expanded_z                     = 0x86,
 DB_PERF_SEL_earlyZ_waiting_for_postZ_done        = 0x87,
 DB_PERF_SEL_reZ_waiting_for_postZ_done           = 0x88,
 DB_PERF_SEL_dk_tile_sends                        = 0x89,
 DB_PERF_SEL_dk_tile_busy                         = 0x8a,
 DB_PERF_SEL_dk_tile_quad_starves                 = 0x8b,
 DB_PERF_SEL_dk_tile_stalls                       = 0x8c,
 DB_PERF_SEL_dk_squad_sends                       = 0x8d,
 DB_PERF_SEL_dk_squad_busy                        = 0x8e,
 DB_PERF_SEL_dk_squad_stalls                      = 0x8f,
 DB_PERF_SEL_Op_Pipe_Busy                         = 0x90,
 DB_PERF_SEL_Op_Pipe_MC_Read_stall                = 0x91,
 DB_PERF_SEL_qc_busy                              = 0x92,
 DB_PERF_SEL_qc_xfc                               = 0x93,
 DB_PERF_SEL_qc_conflicts                         = 0x94,
 DB_PERF_SEL_qc_full_stall                        = 0x95,
 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ         = 0x96,
 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ         = 0x97,
 DB_PERF_SEL_tsc_insert_summarize_stall           = 0x98,
 DB_PERF_SEL_tl_busy                              = 0x99,
 DB_PERF_SEL_tl_dtc_read_starved                  = 0x9a,
 DB_PERF_SEL_tl_z_fetch_stall                     = 0x9b,
 DB_PERF_SEL_tl_stencil_stall                     = 0x9c,
 DB_PERF_SEL_tl_z_decompress_stall                = 0x9d,
 DB_PERF_SEL_tl_stencil_locked_stall              = 0x9e,
 DB_PERF_SEL_tl_events                            = 0x9f,
 DB_PERF_SEL_tl_summarize_squads                  = 0xa0,
 DB_PERF_SEL_tl_flush_expand_squads               = 0xa1,
 DB_PERF_SEL_tl_expand_squads                     = 0xa2,
 DB_PERF_SEL_tl_preZ_squads                       = 0xa3,
 DB_PERF_SEL_tl_postZ_squads                      = 0xa4,
 DB_PERF_SEL_tl_preZ_noop_squads                  = 0xa5,
 DB_PERF_SEL_tl_postZ_noop_squads                 = 0xa6,
 DB_PERF_SEL_tl_tile_ops                          = 0xa7,
 DB_PERF_SEL_tl_in_xfc                            = 0xa8,
 DB_PERF_SEL_tl_in_single_stencil_expand_stall    = 0xa9,
 DB_PERF_SEL_tl_in_fast_z_stall                   = 0xaa,
 DB_PERF_SEL_tl_out_xfc                           = 0xab,
 DB_PERF_SEL_tl_out_squads                        = 0xac,
 DB_PERF_SEL_zf_plane_multicycle                  = 0xad,
 DB_PERF_SEL_PostZ_Samples_passing_Z              = 0xae,
 DB_PERF_SEL_PostZ_Samples_failing_Z              = 0xaf,
 DB_PERF_SEL_PostZ_Samples_failing_S              = 0xb0,
 DB_PERF_SEL_PreZ_Samples_passing_Z               = 0xb1,
 DB_PERF_SEL_PreZ_Samples_failing_Z               = 0xb2,
 DB_PERF_SEL_PreZ_Samples_failing_S               = 0xb3,
 DB_PERF_SEL_ts_tc_update_stall                   = 0xb4,
 DB_PERF_SEL_sc_kick_start                        = 0xb5,
 DB_PERF_SEL_sc_kick_end                          = 0xb6,
 DB_PERF_SEL_clock_reg_active                     = 0xb7,
 DB_PERF_SEL_clock_main_active                    = 0xb8,
 DB_PERF_SEL_clock_mem_export_active              = 0xb9,
 DB_PERF_SEL_esr_ps_out_busy                      = 0xba,
 DB_PERF_SEL_esr_ps_lqf_busy                      = 0xbb,
 DB_PERF_SEL_esr_ps_lqf_stall                     = 0xbc,
 DB_PERF_SEL_etr_out_send                         = 0xbd,
 DB_PERF_SEL_etr_out_busy                         = 0xbe,
 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0xbf,
 DB_PERF_SEL_etr_out_cb_tile_stall                = 0xc0,
 DB_PERF_SEL_etr_out_esr_stall                    = 0xc1,
 DB_PERF_SEL_esr_ps_sqq_busy                      = 0xc2,
 DB_PERF_SEL_esr_ps_sqq_stall                     = 0xc3,
 DB_PERF_SEL_esr_eot_fwd_busy                     = 0xc4,
 DB_PERF_SEL_esr_eot_fwd_holding_squad            = 0xc5,
 DB_PERF_SEL_esr_eot_fwd_forward                  = 0xc6,
 DB_PERF_SEL_esr_sqq_zi_busy                      = 0xc7,
 DB_PERF_SEL_esr_sqq_zi_stall                     = 0xc8,
 DB_PERF_SEL_postzl_sq_pt_busy                    = 0xc9,
 DB_PERF_SEL_postzl_sq_pt_stall                   = 0xca,
 DB_PERF_SEL_postzl_se_busy                       = 0xcb,
 DB_PERF_SEL_postzl_se_stall                      = 0xcc,
 DB_PERF_SEL_postzl_partial_launch                = 0xcd,
 DB_PERF_SEL_postzl_full_launch                   = 0xce,
 DB_PERF_SEL_postzl_partial_waiting               = 0xcf,
 DB_PERF_SEL_postzl_tile_mem_stall                = 0xd0,
 DB_PERF_SEL_postzl_tile_init_stall               = 0xd1,
 DB_PEFF_SEL_prezl_tile_mem_stall                 = 0xd2,
 DB_PERF_SEL_prezl_tile_init_stall                = 0xd3,
 DB_PERF_SEL_dtt_sm_clash_stall                   = 0xd4,
 DB_PERF_SEL_dtt_sm_slot_stall                    = 0xd5,
 DB_PERF_SEL_dtt_sm_miss_stall                    = 0xd6,
 DB_PERF_SEL_mi_rdreq_busy                        = 0xd7,
 DB_PERF_SEL_mi_rdreq_stall                       = 0xd8,
 DB_PERF_SEL_mi_wrreq_busy                        = 0xd9,
 DB_PERF_SEL_mi_wrreq_stall                       = 0xda,
 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop     = 0xdb,
 DB_PERF_SEL_dkg_tile_rate_tile                   = 0xdc,
 DB_PERF_SEL_prezl_src_in_sends                   = 0xdd,
 DB_PERF_SEL_prezl_src_in_stall                   = 0xde,
 DB_PERF_SEL_prezl_src_in_squads                  = 0xdf,
 DB_PERF_SEL_prezl_src_in_squads_unrolled         = 0xe0,
 DB_PERF_SEL_prezl_src_in_tile_rate               = 0xe1,
 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled      = 0xe2,
 DB_PERF_SEL_prezl_src_out_stall                  = 0xe3,
 DB_PERF_SEL_postzl_src_in_sends                  = 0xe4,
 DB_PERF_SEL_postzl_src_in_stall                  = 0xe5,
 DB_PERF_SEL_postzl_src_in_squads                 = 0xe6,
 DB_PERF_SEL_postzl_src_in_squads_unrolled        = 0xe7,
 DB_PERF_SEL_postzl_src_in_tile_rate              = 0xe8,
 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled     = 0xe9,
 DB_PERF_SEL_postzl_src_out_stall                 = 0xea,
 DB_PERF_SEL_esr_ps_src_in_sends                  = 0xeb,
 DB_PERF_SEL_esr_ps_src_in_stall                  = 0xec,
 DB_PERF_SEL_esr_ps_src_in_squads                 = 0xed,
 DB_PERF_SEL_esr_ps_src_in_squads_unrolled        = 0xee,
 DB_PERF_SEL_esr_ps_src_in_tile_rate              = 0xef,
 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled     = 0xf0,
 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
 DB_PERF_SEL_esr_ps_src_out_stall                 = 0xf2,
 DB_PERF_SEL_depth_bounds_qtiles_culled           = 0xf3,
 DB_PERF_SEL_PreZ_Samples_failing_DB              = 0xf4,
 DB_PERF_SEL_PostZ_Samples_failing_DB             = 0xf5,
 DB_PERF_SEL_flush_compressed                     = 0xf6,
 DB_PERF_SEL_flush_plane_le4                      = 0xf7,
 DB_PERF_SEL_tiles_z_fully_summarized             = 0xf8,
 DB_PERF_SEL_tiles_stencil_fully_summarized       = 0xf9,
 DB_PERF_SEL_tiles_z_clear_on_expclear            = 0xfa,
 DB_PERF_SEL_tiles_s_clear_on_expclear            = 0xfb,
 DB_PERF_SEL_tiles_decomp_on_expclear             = 0xfc,
 DB_PERF_SEL_tiles_compressed_to_decompressed     = 0xfd,
 DB_PERF_SEL_Op_Pipe_Prez_Busy                    = 0xfe,
 DB_PERF_SEL_Op_Pipe_Postz_Busy                   = 0xff,
 DB_PERF_SEL_di_dt_stall                          = 0x100,
} PerfCounter_Vals;
typedef enum RingCounterControl {
 COUNTER_RING_SPLIT                               = 0x0,
 COUNTER_RING_0                                   = 0x1,
 COUNTER_RING_1                                   = 0x2,
} RingCounterControl;
typedef enum PixelPipeCounterId {
 PIXEL_PIPE_OCCLUSION_COUNT_0                     = 0x0,
 PIXEL_PIPE_OCCLUSION_COUNT_1                     = 0x1,
 PIXEL_PIPE_OCCLUSION_COUNT_2                     = 0x2,
 PIXEL_PIPE_OCCLUSION_COUNT_3                     = 0x3,
 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0                  = 0x4,
 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0                  = 0x5,
 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1                  = 0x6,
 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1                  = 0x7,
} PixelPipeCounterId;
typedef enum PixelPipeStride {
 PIXEL_PIPE_STRIDE_32_BITS                        = 0x0,
 PIXEL_PIPE_STRIDE_64_BITS                        = 0x1,
 PIXEL_PIPE_STRIDE_128_BITS                       = 0x2,
 PIXEL_PIPE_STRIDE_256_BITS                       = 0x3,
} PixelPipeStride;
typedef enum GB_EDC_DED_MODE {
 GB_EDC_DED_MODE_LOG                              = 0x0,
 GB_EDC_DED_MODE_HALT                             = 0x1,
 GB_EDC_DED_MODE_INT_HALT                         = 0x2,
} GB_EDC_DED_MODE;
#define GB_TILING_CONFIG_TABLE_SIZE               0x20
#define GB_TILING_CONFIG_MACROTABLE_SIZE          0x10
typedef enum GRBM_PERF_SEL {
 GRBM_PERF_SEL_COUNT                              = 0x0,
 GRBM_PERF_SEL_USER_DEFINED                       = 0x1,
 GRBM_PERF_SEL_GUI_ACTIVE                         = 0x2,
 GRBM_PERF_SEL_CP_BUSY                            = 0x3,
 GRBM_PERF_SEL_CP_COHER_BUSY                      = 0x4,
 GRBM_PERF_SEL_CP_DMA_BUSY                        = 0x5,
 GRBM_PERF_SEL_CB_BUSY                            = 0x6,
 GRBM_PERF_SEL_DB_BUSY                            = 0x7,
 GRBM_PERF_SEL_PA_BUSY                            = 0x8,
 GRBM_PERF_SEL_SC_BUSY                            = 0x9,
 GRBM_PERF_SEL_RESERVED_6                         = 0xa,
 GRBM_PERF_SEL_SPI_BUSY                           = 0xb,
 GRBM_PERF_SEL_SX_BUSY                            = 0xc,
 GRBM_PERF_SEL_TA_BUSY                            = 0xd,
 GRBM_PERF_SEL_CB_CLEAN                           = 0xe,
 GRBM_PERF_SEL_DB_CLEAN                           = 0xf,
 GRBM_PERF_SEL_RESERVED_5                         = 0x10,
 GRBM_PERF_SEL_VGT_BUSY                           = 0x11,
 GRBM_PERF_SEL_RESERVED_4                         = 0x12,
 GRBM_PERF_SEL_RESERVED_3                         = 0x13,
 GRBM_PERF_SEL_RESERVED_2                         = 0x14,
 GRBM_PERF_SEL_RESERVED_1                         = 0x15,
 GRBM_PERF_SEL_RESERVED_0                         = 0x16,
 GRBM_PERF_SEL_IA_BUSY                            = 0x17,
 GRBM_PERF_SEL_IA_NO_DMA_BUSY                     = 0x18,
 GRBM_PERF_SEL_GDS_BUSY                           = 0x19,
 GRBM_PERF_SEL_BCI_BUSY                           = 0x1a,
 GRBM_PERF_SEL_RLC_BUSY                           = 0x1b,
 GRBM_PERF_SEL_TC_BUSY                            = 0x1c,
 GRBM_PERF_SEL_CPG_BUSY                           = 0x1d,
 GRBM_PERF_SEL_CPC_BUSY                           = 0x1e,
 GRBM_PERF_SEL_CPF_BUSY                           = 0x1f,
 GRBM_PERF_SEL_WD_BUSY                            = 0x20,
 GRBM_PERF_SEL_WD_NO_DMA_BUSY                     = 0x21,
} GRBM_PERF_SEL;
typedef enum GRBM_SE0_PERF_SEL {
 GRBM_SE0_PERF_SEL_COUNT                          = 0x0,
 GRBM_SE0_PERF_SEL_USER_DEFINED                   = 0x1,
 GRBM_SE0_PERF_SEL_CB_BUSY                        = 0x2,
 GRBM_SE0_PERF_SEL_DB_BUSY                        = 0x3,
 GRBM_SE0_PERF_SEL_SC_BUSY                        = 0x4,
 GRBM_SE0_PERF_SEL_RESERVED_1                     = 0x5,
 GRBM_SE0_PERF_SEL_SPI_BUSY                       = 0x6,
 GRBM_SE0_PERF_SEL_SX_BUSY                        = 0x7,
 GRBM_SE0_PERF_SEL_TA_BUSY                        = 0x8,
 GRBM_SE0_PERF_SEL_CB_CLEAN                       = 0x9,
 GRBM_SE0_PERF_SEL_DB_CLEAN                       = 0xa,
 GRBM_SE0_PERF_SEL_RESERVED_0                     = 0xb,
 GRBM_SE0_PERF_SEL_PA_BUSY                        = 0xc,
 GRBM_SE0_PERF_SEL_VGT_BUSY                       = 0xd,
 GRBM_SE0_PERF_SEL_BCI_BUSY                       = 0xe,
} GRBM_SE0_PERF_SEL;
typedef enum GRBM_SE1_PERF_SEL {
 GRBM_SE1_PERF_SEL_COUNT                          = 0x0,
 GRBM_SE1_PERF_SEL_USER_DEFINED                   = 0x1,
 GRBM_SE1_PERF_SEL_CB_BUSY                        = 0x2,
 GRBM_SE1_PERF_SEL_DB_BUSY                        = 0x3,
 GRBM_SE1_PERF_SEL_SC_BUSY                        = 0x4,
 GRBM_SE1_PERF_SEL_RESERVED_1                     = 0x5,
 GRBM_SE1_PERF_SEL_SPI_BUSY                       = 0x6,
 GRBM_SE1_PERF_SEL_SX_BUSY                        = 0x7,
 GRBM_SE1_PERF_SEL_TA_BUSY                        = 0x8,
 GRBM_SE1_PERF_SEL_CB_CLEAN                       = 0x9,
 GRBM_SE1_PERF_SEL_DB_CLEAN                       = 0xa,
 GRBM_SE1_PERF_SEL_RESERVED_0                     = 0xb,
 GRBM_SE1_PERF_SEL_PA_BUSY                        = 0xc,
 GRBM_SE1_PERF_SEL_VGT_BUSY                       = 0xd,
 GRBM_SE1_PERF_SEL_BCI_BUSY                       = 0xe,
} GRBM_SE1_PERF_SEL;
typedef enum GRBM_SE2_PERF_SEL {
 GRBM_SE2_PERF_SEL_COUNT                          = 0x0,
 GRBM_SE2_PERF_SEL_USER_DEFINED                   = 0x1,
 GRBM_SE2_PERF_SEL_CB_BUSY                        = 0x2,
 GRBM_SE2_PERF_SEL_DB_BUSY                        = 0x3,
 GRBM_SE2_PERF_SEL_SC_BUSY                        = 0x4,
 GRBM_SE2_PERF_SEL_RESERVED_1                     = 0x5,
 GRBM_SE2_PERF_SEL_SPI_BUSY                       = 0x6,
 GRBM_SE2_PERF_SEL_SX_BUSY                        = 0x7,
 GRBM_SE2_PERF_SEL_TA_BUSY                        = 0x8,
 GRBM_SE2_PERF_SEL_CB_CLEAN                       = 0x9,
 GRBM_SE2_PERF_SEL_DB_CLEAN                       = 0xa,
 GRBM_SE2_PERF_SEL_RESERVED_0                     = 0xb,
 GRBM_SE2_PERF_SEL_PA_BUSY                        = 0xc,
 GRBM_SE2_PERF_SEL_VGT_BUSY                       = 0xd,
 GRBM_SE2_PERF_SEL_BCI_BUSY                       = 0xe,
} GRBM_SE2_PERF_SEL;
typedef enum GRBM_SE3_PERF_SEL {
 GRBM_SE3_PERF_SEL_COUNT                          = 0x0,
 GRBM_SE3_PERF_SEL_USER_DEFINED                   = 0x1,
 GRBM_SE3_PERF_SEL_CB_BUSY                        = 0x2,
 GRBM_SE3_PERF_SEL_DB_BUSY                        = 0x3,
 GRBM_SE3_PERF_SEL_SC_BUSY                        = 0x4,
 GRBM_SE3_PERF_SEL_RESERVED_1                     = 0x5,
 GRBM_SE3_PERF_SEL_SPI_BUSY                       = 0x6,
 GRBM_SE3_PERF_SEL_SX_BUSY                        = 0x7,
 GRBM_SE3_PERF_SEL_TA_BUSY                        = 0x8,
 GRBM_SE3_PERF_SEL_CB_CLEAN                       = 0x9,
 GRBM_SE3_PERF_SEL_DB_CLEAN                       = 0xa,
 GRBM_SE3_PERF_SEL_RESERVED_0                     = 0xb,
 GRBM_SE3_PERF_SEL_PA_BUSY                        = 0xc,
 GRBM_SE3_PERF_SEL_VGT_BUSY                       = 0xd,
 GRBM_SE3_PERF_SEL_BCI_BUSY                       = 0xe,
} GRBM_SE3_PERF_SEL;
typedef enum SU_PERFCNT_SEL {
 PERF_PAPC_PASX_REQ                               = 0x0,
 PERF_PAPC_PASX_DISABLE_PIPE                      = 0x1,
 PERF_PAPC_PASX_FIRST_VECTOR                      = 0x2,
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