/* * Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE.
*/
/****************************************************************************/ /*Portion I: Definitions shared between VBIOS and Driver */ /****************************************************************************/
#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios
//Maximum size of that FireGL flag string #define ATOM_FIREGL_FLAG_STRING "FGL"//Flag used to enable FireGL Support #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
#define ATOM_FAKE_DESKTOP_STRING "DSK"//Flag used to enable mobile ASIC on Desktop #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
#define ATOM_M54T_FLAG_STRING "M54T"//Flag used to enable M54T Support #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
/****************************************************************************/ // Common header for all tables (Data table, Command table). // Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. // And the pointer actually points to this header. /****************************************************************************/
typedefstruct _ATOM_COMMON_TABLE_HEADER
{
USHORT usStructureSize;
UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware //Image can't be updated, while Driver needs to carry the new table!
}ATOM_COMMON_TABLE_HEADER;
/****************************************************************************/ // Structure stores the ROM header. /****************************************************************************/ typedefstruct _ATOM_ROM_HEADER
{
ATOM_COMMON_TABLE_HEADER sHeader;
UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, //atombios should init it as "ATOM", don't change the position
USHORT usBiosRuntimeSegmentAddress;
USHORT usProtectedModeInfoOffset;
USHORT usConfigFilenameOffset;
USHORT usCRC_BlockOffset;
USHORT usBIOS_BootupMessageOffset;
USHORT usInt10Offset;
USHORT usPciBusDevInitCode;
USHORT usIoBaseAddress;
USHORT usSubsystemVendorID;
USHORT usSubsystemID;
USHORT usPCI_InfoOffset;
USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
UCHAR ucExtendedFunctionCode;
UCHAR ucReserved;
}ATOM_ROM_HEADER;
typedefstruct _ATOM_ROM_HEADER_V2_1
{
ATOM_COMMON_TABLE_HEADER sHeader;
UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, //atombios should init it as "ATOM", don't change the position
USHORT usBiosRuntimeSegmentAddress;
USHORT usProtectedModeInfoOffset;
USHORT usConfigFilenameOffset;
USHORT usCRC_BlockOffset;
USHORT usBIOS_BootupMessageOffset;
USHORT usInt10Offset;
USHORT usPciBusDevInitCode;
USHORT usIoBaseAddress;
USHORT usSubsystemVendorID;
USHORT usSubsystemID;
USHORT usPCI_InfoOffset;
USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
UCHAR ucExtendedFunctionCode;
UCHAR ucReserved;
ULONG ulPSPDirTableOffset;
}ATOM_ROM_HEADER_V2_1;
/****************************************************************************/ // Structures used in Command.mtb /****************************************************************************/ typedefstruct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
USHORT DIGxEncoderControl; //Only used by Bios
USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
USHORT GPIOPinControl; //Atomic Table, only used by Bios
USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT MemoryPLLInit; //Atomic Table, used only by Bios
USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
USHORT SetUniphyInstance; //Atomic Table, only used by Bios
USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
USHORT GetConditionalGoldenSetting; //Only used by Bios
USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1
USHORT PatchMCSetting; //only used by BIOS
USHORT MC_SEQ_Control; //only used by BIOS
USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
USHORT EnableScaler; //Atomic Table, used only by Bios
USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
USHORT GetSMUClockInfo; //Atomic Table, used only by Bios
USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
USHORT LUT_AutoFill; //Atomic Table, only used by Bios
USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK
USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
USHORT MemoryCleanUp; //Atomic Table, only used by Bios
USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT MemoryTraining; //Atomic Table, used only by Bios
USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
USHORT DPEncoderService; //Function Table,only used by Bios
USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
/****************************************************************************/ // Structures used in every command table /****************************************************************************/ typedefstruct _ATOM_TABLE_ATTRIBUTE
{ #if ATOM_BIG_ENDIAN
USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), #else
USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag #endif
}ATOM_TABLE_ATTRIBUTE;
/****************************************************************************/ // Common header for all command tables. // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. // And the pointer actually points to this header. /****************************************************************************/ typedefstruct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
{
ATOM_COMMON_TABLE_HEADER CommonHeader;
ATOM_TABLE_ATTRIBUTE TableAttribute;
}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
/****************************************************************************/ // Structures used by ComputeMemoryEnginePLLTable /****************************************************************************/
/****************************************************************************/ // Structures used by AdjustMemoryControllerTable /****************************************************************************/ typedefstruct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
{ #if ATOM_BIG_ENDIAN
ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
ULONG ulClockFreq:24; #else
ULONG ulClockFreq:24;
ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block #endif
}ATOM_ADJUST_MEMORY_CLOCK_FREQ; #define POINTER_RETURN_FLAG 0x80
typedefstruct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
{
ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
UCHAR ucAction; //0:reserved //1:Memory //2:Engine
UCHAR ucReserved; //may expand to return larger Fbdiv later
UCHAR ucFbDiv; //return value
UCHAR ucPostDiv; //return value
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
typedefstruct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
{
ULONG ulClock; //When return, [23:0] return real clock
UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
USHORT usFbDiv; //return Feedback value to be written to register
UCHAR ucPostDiv; //return post div to be written to register
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL #define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path #define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only #define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only #define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only
typedefstruct _ATOM_COMPUTE_CLOCK_FREQ
{ #if ATOM_BIG_ENDIAN
ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
ULONG ulClockFreq:24; // in unit of 10kHz #else
ULONG ulClockFreq:24; // in unit of 10kHz
ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM #endif
}ATOM_COMPUTE_CLOCK_FREQ;
// V4 are only used for APU which PLL outside GPU typedefstruct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
{ #if ATOM_BIG_ENDIAN
ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
ULONG ulClock:24; //Input= target clock, output = actual clock #else
ULONG ulClock:24; //Input= target clock, output = actual clock
ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly #endif
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
/****************************************************************************/ // Structures used by ASIC_Init.ctb /****************************************************************************/ typedefstruct _ASIC_INIT_PARAMETERS
{
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
}ASIC_INIT_PARAMETERS;
typedefstruct _ASIC_INIT_PS_ALLOCATION
{
ASIC_INIT_PARAMETERS sASICInitClocks;
SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
}ASIC_INIT_PS_ALLOCATION;
typedefstruct _DAC_LOAD_DETECTION_PS_ALLOCATION
{
DAC_LOAD_DETECTION_PARAMETERS sDacload;
ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
}DAC_LOAD_DETECTION_PS_ALLOCATION;
/****************************************************************************/ // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb /****************************************************************************/ typedefstruct _DAC_ENCODER_CONTROL_PARAMETERS
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
UCHAR ucAction; // 0: turn off encoder // 1: setup and turn on encoder // 7: ATOM_ENCODER_INIT Initialize DAC
}DAC_ENCODER_CONTROL_PARAMETERS;
// New Command for DIGxEncoderControlTable v1.5 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14 #define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP #define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table #define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table
//ucTableFormatRevision=1 //ucTableContentRevision=3 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver typedefstruct _ATOM_DIG_ENCODER_CONFIG_V3
{ #if ATOM_BIG_ENDIAN
UCHAR ucReserved1:1;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved:3;
UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz #else
UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
UCHAR ucReserved:3;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved1:1; #endif
}ATOM_DIG_ENCODER_CONFIG_V3;
typedefstruct _DIG_ENCODER_CONTROL_PARAMETERS_V3
{
USHORT usPixelClock; // in 10KHz; for bios convenient
ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
UCHAR ucAction; union{
UCHAR ucEncoderMode; // =0: DP encoder // =1: LVDS encoder // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder // =5: DP audio
UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE // =0: external DP // =0x1: internal DP2 // =0x11: internal DP1 for NutMeg/Travis DP translator
};
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
UCHAR ucReserved;
}DIG_ENCODER_CONTROL_PARAMETERS_V3;
//ucTableFormatRevision=1 //ucTableContentRevision=4 // start from NI // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver typedefstruct _ATOM_DIG_ENCODER_CONFIG_V4
{ #if ATOM_BIG_ENDIAN
UCHAR ucReserved1:1;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved:2;
UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version #else
UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
UCHAR ucReserved:2;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved1:1; #endif
}ATOM_DIG_ENCODER_CONFIG_V4;
typedefstruct _ENCODER_GENERIC_CMD_PARAMETERS_V5
{
UCHAR ucDigId; // 0~6 map to DIG0~DIG6
UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters
UCHAR ucReserved[2];
ULONG ulReserved[2];
}ENCODER_GENERIC_CMD_PARAMETERS_V5;
/****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable // LVTMATransmitterControlTable // DVOOutputControlTable /****************************************************************************/ typedefstruct _ATOM_DP_VS_MODE
{
UCHAR ucLaneSel;
UCHAR ucLaneSet;
}ATOM_DP_VS_MODE;
typedefstruct _DIG_TRANSMITTER_CONTROL_PARAMETERS
{ union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
UCHAR ucConfig; // [0]=0: 4 lane Link, // =1: 8 lane Link ( Dual Links TMDS ) // [1]=0: InCoherent mode // =1: Coherent Mode // [2] Link Select: // =0: PHY linkA if bfLane<3 // =1: PHY linkB if bfLanes<3 // =0: PHY linkA+B if bfLanes=3 // [5:4]PCIE lane Sel // =0: lane 0~3 or 0~7 // =1: lane 4~7 // =2: lane 8~11 or 8~15 // =3: lane 12~15
UCHAR ucAction; // =0: turn off encoder // =1: turn on encoder
UCHAR ucReserved[4];
}DIG_TRANSMITTER_CONTROL_PARAMETERS;
#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
// Following are used for DigTransmitterControlTable ver1.2 typedefstruct _ATOM_DIG_TRANSMITTER_CONFIG_V2
{ #if ATOM_BIG_ENDIAN
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF )
UCHAR ucReserved:1;
UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector #else
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
UCHAR ucReserved:1;
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) #endif
}ATOM_DIG_TRANSMITTER_CONFIG_V2;
// Bit3 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
typedefstruct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
{ union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucReserved[4];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
typedefstruct _ATOM_DIG_TRANSMITTER_CONFIG_V3
{ #if ATOM_BIG_ENDIAN
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF )
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector #else
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) #endif
}ATOM_DIG_TRANSMITTER_CONFIG_V3;
typedefstruct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
{ union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucLaneNum;
UCHAR ucReserved[3];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
/****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable V1.4 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=4 /****************************************************************************/ typedefstruct _ATOM_DP_VS_MODE_V4
{
UCHAR ucLaneSel; union
{
UCHAR ucLaneSet; struct { #if ATOM_BIG_ENDIAN
UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level #else
UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 #endif
};
};
}ATOM_DP_VS_MODE_V4;
typedefstruct _ATOM_DIG_TRANSMITTER_CONFIG_V4
{ #if ATOM_BIG_ENDIAN
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF )
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector #else
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) #endif
}ATOM_DIG_TRANSMITTER_CONFIG_V4;
typedefstruct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
{ union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
}; union
{
ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
UCHAR ucConfig;
};
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucLaneNum;
UCHAR ucReserved[3];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
typedefstruct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6
{
UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx union
{
UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
};
UCHAR ucLaneNum; // Lane number
ULONG ulSymClock; // Symbol Clock in 10Khz
UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
UCHAR ucReserved;
ULONG ulReserved;
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6;
/****************************************************************************/ // Structures used by ExternalEncoderControlTable V1.3 // ASIC Families: Evergreen, Llano, NI // ucTableFormatRevision=1 // ucTableContentRevision=3 /****************************************************************************/
typedefstruct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
{ union{
USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
USHORT usConnectorId; // connector id, valid when ucAction = INIT
};
UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
UCHAR ucAction; //
UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
UCHAR ucReserved;
}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
typedefstruct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2
{ // Possible value of ucAction // ATOM_TRANSMITTER_ACTION_LCD_BLON // ATOM_TRANSMITTER_ACTION_LCD_BLOFF // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL // ATOM_TRANSMITTER_ACTION_POWER_ON // ATOM_TRANSMITTER_ACTION_POWER_OFF
UCHAR ucAction;
UCHAR ucBriLevel;
USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz
}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;
/****************************************************************************/ // Structures used by BlankCRTCTable /****************************************************************************/ typedefstruct _BLANK_CRTC_PARAMETERS
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
USHORT usBlackColorRCr;
USHORT usBlackColorGY;
USHORT usBlackColorBCb;
}BLANK_CRTC_PARAMETERS; #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
/****************************************************************************/ // Structures used by EnableCRTCTable // EnableCRTCMemReqTable // UpdateCRTC_DoubleBufferRegistersTable /****************************************************************************/ typedefstruct _ENABLE_CRTC_PARAMETERS
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[2];
}ENABLE_CRTC_PARAMETERS; #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
/****************************************************************************/ // Structures used by SetCRTC_OverScanTable /****************************************************************************/ typedefstruct _SET_CRTC_OVERSCAN_PARAMETERS
{
USHORT usOverscanRight; // right
USHORT usOverscanLeft; // left
USHORT usOverscanBottom; // bottom
USHORT usOverscanTop; // top
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucPadding[3];
}SET_CRTC_OVERSCAN_PARAMETERS; #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
typedefstruct _PIXEL_CLOCK_PARAMETERS_V3
{
USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
USHORT usRefDiv; // Reference divider
USHORT usFbDiv; // feedback divider
UCHAR ucPostDiv; // post divider
UCHAR ucFracFbDiv; // fractional feedback divider
UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h union
{
UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
};
UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
}PIXEL_CLOCK_PARAMETERS_V3;
typedefstruct _PIXEL_CLOCK_PARAMETERS_V5
{
UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. union{
UCHAR ucReserved;
UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
};
USHORT usPixelClock; // target the pixel clock to drive the CRTC timing // 0 means disable PPLL/DCPLL.
USHORT usFbDiv; // feedback divider integer part.
UCHAR ucPostDiv; // post divider.
UCHAR ucRefDiv; // Reference divider
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, // indicate which graphic encoder will be used.
UCHAR ucEncoderMode; // Encoder mode:
UCHAR ucMiscInfo; // bit[0]= Force program PPLL // bit[1]= when VGA timing is used. // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp // bit[4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) // =1: other external clock source, which is pre-defined // by VBIOS depend on the feature required. // bit[7:5]: reserved.
ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
typedefstruct _CRTC_PIXEL_CLOCK_FREQ
{ #if ATOM_BIG_ENDIAN
ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case.
ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. #else
ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. #endif
}CRTC_PIXEL_CLOCK_FREQ;
typedefstruct _PIXEL_CLOCK_PARAMETERS_V6
{ union{
CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
ULONG ulDispEngClkFreq; // dispclk frequency
};
USHORT usFbDiv; // feedback divider integer part.
UCHAR ucPostDiv; // post divider.
UCHAR ucRefDiv; // Reference divider
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, // indicate which graphic encoder will be used.
UCHAR ucEncoderMode; // Encoder mode:
UCHAR ucMiscInfo; // bit[0]= Force program PPLL // bit[1]= when VGA timing is used. // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp // bit[4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) // =1: other external clock source, which is pre-defined // by VBIOS depend on the feature required. // bit[7:5]: reserved.
ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
}PIXEL_CLOCK_PARAMETERS_V6;
#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40
typedefstruct _PIXEL_CLOCK_PARAMETERS_V7
{
ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, // indicate which graphic encoder will be used.
UCHAR ucEncoderMode; // Encoder mode:
UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk ) // bit[5:4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) // =1: pcie // =2: GENLK
UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
UCHAR ucReserved[2];
ULONG ulReserved;
}PIXEL_CLOCK_PARAMETERS_V7;
//ucDeepColorRatio #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
// SetDCEClockTable input parameter for DCE11.1 typedefstruct _SET_DCE_CLOCK_PARAMETERS_V1_1
{
ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
}SET_DCE_CLOCK_PARAMETERS_V1_1;
// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above typedefstruct _SET_DCE_CLOCK_PARAMETERS_V2_1
{
ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
}SET_DCE_CLOCK_PARAMETERS_V2_1;
//ucDCEClkType #define DCE_CLOCK_TYPE_DISPCLK 0 #define DCE_CLOCK_TYPE_DPREFCLK 1 #define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable
//ucDCEClkFlag when ucDCEClkType == PIXCLK #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 #define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04
/****************************************************************************/ // Structures used by AdjustDisplayPllTable /****************************************************************************/ typedefstruct _ADJUST_DISPLAY_PLL_PARAMETERS
{
USHORT usPixelClock;
UCHAR ucTransmitterID;
UCHAR ucEncodeMode; union
{
UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
UCHAR ucConfig; //if none DVO, not defined yet
};
UCHAR ucReserved[3];
}ADJUST_DISPLAY_PLL_PARAMETERS;
typedefstruct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
{
USHORT usPixelClock; // target pixel clock
UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
UCHAR ucExtTransmitterID; // external encoder id.
UCHAR ucReserved[2];
}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
// usDispPllConfig v1.2 for RoadRunner #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
typedefstruct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
{
ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
UCHAR ucReserved[2];
}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
/****************************************************************************/ // Structures used by EnableYUVTable /****************************************************************************/ typedefstruct _ENABLE_YUV_PARAMETERS
{
UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
UCHAR ucPadding[2];
}ENABLE_YUV_PARAMETERS; #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
/****************************************************************************/ // Structures used by GetMemoryClockTable /****************************************************************************/ typedefstruct _GET_MEMORY_CLOCK_PARAMETERS
{
ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
} GET_MEMORY_CLOCK_PARAMETERS; #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
/****************************************************************************/ // Structures used by GetEngineClockTable /****************************************************************************/ typedefstruct _GET_ENGINE_CLOCK_PARAMETERS
{
ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
} GET_ENGINE_CLOCK_PARAMETERS; #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
/****************************************************************************/ // Following Structures and constant may be obsolete /****************************************************************************/ //Maxium 8 bytes,the data read in will be placed in the parameter space. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed typedefstruct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
UCHAR ucSlaveAddr; //Read from which slave
UCHAR ucLineNumber; //Read from which HW assisted line
}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
typedefstruct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
USHORT usByteOffset; //Write to which byte //Upper portion of usByteOffset is Format of data //1bytePS+offsetPS //2bytesPS+offsetPS //blockID+offsetPS //blockID+offsetID //blockID+counterID+offsetID
UCHAR ucData; //PS data1
UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
UCHAR ucSlaveAddr; //Write to which slave
UCHAR ucLineNumber; //Write from which HW assisted line
}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
typedefstruct _SET_UP_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
UCHAR ucSlaveAddr; //Write to which slave
UCHAR ucLineNumber; //Write from which HW assisted line
}SET_UP_HW_I2C_DATA_PARAMETERS;
/****************************************************************************/ // Structures used by PowerConnectorDetectionTable /****************************************************************************/ typedefstruct _POWER_CONNECTOR_DETECTION_PARAMETERS
{
UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
UCHAR ucPwrBehaviorId;
USHORT usPwrBudget; //how much power currently boot to in unit of watt
}POWER_CONNECTOR_DETECTION_PARAMETERS;
typedefstruct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
{
UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
UCHAR ucReserved;
USHORT usPwrBudget; //how much power currently boot to in unit of watt
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
/****************************LVDS SS Command Table Definitions**********************/
/****************************************************************************/ // Structures used by EnableSpreadSpectrumOnPPLLTable /****************************************************************************/ typedefstruct _ENABLE_LVDS_SS_PARAMETERS
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[3];
}ENABLE_LVDS_SS_PARAMETERS;
//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. typedefstruct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
UCHAR ucSpreadSpectrumStep; //
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucSpreadSpectrumDelay;
UCHAR ucSpreadSpectrumRange;
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
typedefstruct _SET_PIXEL_CLOCK_PS_ALLOCATION
{
PIXEL_CLOCK_PARAMETERS sPCLKInput;
ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
}SET_PIXEL_CLOCK_PS_ALLOCATION;
/****************************************************************************/ // Structures used by ### /****************************************************************************/ typedefstruct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
{
UCHAR ucEnable; // Enable or Disable External TMDS encoder
UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
UCHAR ucPadding[2];
}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
typedefstruct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
{
ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 typedefstruct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
{
ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
//ucTableFormatRevision=1 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for // bit1=0: non-coherent mode // =1: coherent mode
//========================================================================================== //Only change is here next time when changing encoder parameter definitions again! #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
typedefstruct _SET_VOLTAGE_PARAMETERS
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
UCHAR ucVoltageIndex; // An index to tell which voltage level
UCHAR ucReserved;
}SET_VOLTAGE_PARAMETERS;
typedefstruct _SET_VOLTAGE_PARAMETERS_V2
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
USHORT usVoltageLevel; // real voltage level
}SET_VOLTAGE_PARAMETERS_V2;
// used by both SetVoltageTable v1.3 and v1.4 typedefstruct _SET_VOLTAGE_PARAMETERS_V1_3
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Indicate action: Set voltage level
USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
}SET_VOLTAGE_PARAMETERS_V1_3;
//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode #define ATOM_SET_VOLTAGE 0 //Set voltage Level #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
// New Added from SI for GetVoltageInfoTable, input parameter structure typedefstruct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulReserved;
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID typedefstruct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
{
ULONG ulVotlageGpioState;
ULONG ulVoltageGPioMask;
}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID typedefstruct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
{
USHORT usVoltageLevel;
USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
ULONG ulReseved;
}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure typedefstruct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
// New in GetVoltageInfo v1.2 ucVoltageMode #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
// New Added from CI Hawaii for EVV feature typedefstruct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
{
USHORT usVoltageLevel; // real voltage level in unit of mv
USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
USHORT usTDP_Current; // TDP_Current in unit of 0.01A
USHORT usTDP_Power; // TDP_Current in unit of 0.1W
}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure typedefstruct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
ULONG ulReserved[3];
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3;
// New Added from CI Hawaii for EVV feature typedefstruct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3
{
ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
ULONG ulReserved[4];
}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3;
/****************************************************************************/ // Structures used by GetSMUClockInfo /****************************************************************************/ typedefstruct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1
{
ULONG ulDfsPllOutputFreq:24;
ULONG ucDfsDivider:8;
}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1;
/****************************************************************************/ // Structures used by TVEncoderControlTable /****************************************************************************/ typedefstruct _TV_ENCODER_CONTROL_PARAMETERS
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
UCHAR ucAction; // 0: turn off encoder // 1: setup and turn on encoder
}TV_ENCODER_CONTROL_PARAMETERS;
typedefstruct _TV_ENCODER_CONTROL_PS_ALLOCATION
{
TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
}TV_ENCODER_CONTROL_PS_ALLOCATION;
/****************************************************************************/ // Structure used in Data.mtb /****************************************************************************/ typedefstruct _ATOM_MASTER_LIST_OF_DATA_TABLES
{
USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
USHORT StandardVESA_Timing; // Only used by Bios
USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
USHORT PaletteData; // Only used by BIOS
USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
USHORT SMU_Info; // Shared by various SW components,latest version 1.1
USHORT SupportedDevicesInfo; // Will be obsolete from R600
USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
USHORT VESA_ToInternalModeLUT; // Only used by Bios
USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600
USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
USHORT GPUVirtualizationInfo; // Will be obsolete from R600
USHORT SaveRestoreInfo; // Only used by Bios
USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
USHORT XTMDS_Info; // Will be obsolete from R600
USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
USHORT Object_Header; // Shared by various SW components,latest version 1.1
USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
USHORT MC_InitParameter; // Only used by command table
USHORT ASIC_VDDC_Info; // Will be obsolete from R600
USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
USHORT TV_VideoMode; // Only used by command table
USHORT VRAM_Info; // Only used by command table, latest version 1.3
USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
USHORT IntegratedSystemInfo; // Shared by various SW components
USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
USHORT ServiceInfo;
}ATOM_MASTER_LIST_OF_DATA_TABLES;
/****************************************************************************/ // Structure used in MultimediaCapabilityInfoTable /****************************************************************************/ typedefstruct _ATOM_MULTIMEDIA_CAPABILITY_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulSignature; // HW info table signature string "$ATI"
UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
UCHAR ucVideoPortInfo; // Provides the video port capabilities
UCHAR ucHostPortInfo; // Provides host port configuration information
}ATOM_MULTIMEDIA_CAPABILITY_INFO;
/****************************************************************************/ // Structure used in MultimediaConfigInfoTable /****************************************************************************/ typedefstruct _ATOM_MULTIMEDIA_CONFIG_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulSignature; // MM info table signature sting "$MMT"
UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
}ATOM_MULTIMEDIA_CONFIG_INFO;
/****************************************************************************/ // Structures used in FirmwareInfoTable /****************************************************************************/
// usBIOSCapability Defintion: // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; // Others: Reserved #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
typedefstruct _ATOM_FIRMWARE_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucPadding[3]; //Don't use them
ULONG aulReservedForBIOS[3]; //Don't use them
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO;
typedefstruct _ATOM_FIRMWARE_INFO_V1_2
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
UCHAR ucPadding[2]; //Don't use them
ULONG aulReservedForBIOS[2]; //Don't use them
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO_V1_2;
typedefstruct _ATOM_FIRMWARE_INFO_V1_3
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
UCHAR ucPadding[2]; //Don't use them
ULONG aulReservedForBIOS; //Don't use them
ULONG ul3DAccelerationEngineClock;//In 10Khz unit
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO_V1_3;
typedefstruct _ATOM_FIRMWARE_INFO_V1_4
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
USHORT usBootUpVDDCVoltage; //In MV unit
USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
ULONG ul3DAccelerationEngineClock;//In 10Khz unit
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO_V1_4;
//the structure below to be used from Cypress typedefstruct _ATOM_FIRMWARE_INFO_V2_1
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulReserved1;
ULONG ulReserved2;
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
UCHAR ucReserved1; //Was ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
USHORT usBootUpVDDCVoltage; //In MV unit
USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
ULONG ulReserved4; //Was ulAsicMaximumVoltage
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usCoreReferenceClock; //In 10Khz unit
USHORT usMemoryReferenceClock; //In 10Khz unit
USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
UCHAR ucMemoryModule_ID; //Indicate what is the board design
UCHAR ucReserved4[3];
}ATOM_FIRMWARE_INFO_V2_1;
//the structure below to be used from NI //ucTableFormatRevision=2 //ucTableContentRevision=2
typedefstruct _ATOM_FIRMWARE_INFO_V2_2
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulSPLL_OutputFreq; //In 10Khz unit
ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
UCHAR ucReserved3; //Was ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
USHORT usBootUpVDDCVoltage; //In MV unit
USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
ULONG ulReserved4; //Was ulAsicMaximumVoltage
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
UCHAR ucRemoteDisplayConfig;
UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usCoreReferenceClock; //In 10Khz unit
USHORT usMemoryReferenceClock; //In 10Khz unit
USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
UCHAR ucMemoryModule_ID; //Indicate what is the board design
UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level.
UCHAR ucReserved9;
USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
USHORT usBootUpVDDGFXVoltage; //In unit of mv;
ULONG ulReserved10[3]; // New added comparing to previous version
}ATOM_FIRMWARE_INFO_V2_2;
// definition of ucRemoteDisplayConfig #define REMOTE_DISPLAY_DISABLE 0x00 #define REMOTE_DISPLAY_ENABLE 0x01
/****************************************************************************/ // Structures used in IntegratedSystemInfoTable /****************************************************************************/ #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 #define IGP_CAP_FLAG_AC_CARD 0x4 #define IGP_CAP_FLAG_SDVO_CARD 0x8 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
typedefstruct _ATOM_INTEGRATED_SYSTEM_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulBootUpEngineClock; //in 10kHz unit
ULONG ulBootUpMemoryClock; //in 10kHz unit
ULONG ulMaxSystemMemoryClock; //in 10kHz unit
ULONG ulMinSystemMemoryClock; //in 10kHz unit
UCHAR ucNumberOfCyclesInPeriodHi;
UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
USHORT usReserved1;
USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
ULONG ulReserved[2];
USHORT usFSBClock; //In MHz unit
USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card //Bit[4]==1: P/2 mode, ==0: P/1 mode
USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
USHORT usK8MemoryClock; //in MHz unit
USHORT usK8SyncStartDelay; //in 0.01 us unit
USHORT usK8DataReturnTime; //in 0.01 us unit
UCHAR ucMaxNBVoltage;
UCHAR ucMinNBVoltage;
UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
UCHAR ucMaxNBVoltageHigh;
UCHAR ucMinNBVoltageHigh;
}ATOM_INTEGRATED_SYSTEM_INFO;
/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0
usFSBClock: For Intel IGP,it's FSB Freq For AMD IGP,it's HT Link Speed
usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
VC:Voltage Control ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
*/
/* The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
SW components can access the IGP system infor structure in the same way as before
*/
typedefstruct _ATOM_INTEGRATED_SYSTEM_INFO_V2
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulBootUpEngineClock; //in 10kHz unit
ULONG ulReserved1[2]; //must be 0x0 for the reserved
ULONG ulBootUpUMAClock; //in 10kHz unit
ULONG ulBootUpSidePortClock; //in 10kHz unit
ULONG ulMinSidePortClock; //in 10kHz unit
ULONG ulReserved2[6]; //must be 0x0 for the reserved
ULONG ulSystemConfig; //see explanation below
ULONG ulBootUpReqDisplayVector;
ULONG ulOtherDisplayMisc;
ULONG ulDDISlot1Config;
ULONG ulDDISlot2Config;
UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
UCHAR ucUMAChannelNumber;
UCHAR ucDockingPinBit;
UCHAR ucDockingPinPolarity;
ULONG ulDockingPinCFGInfo;
ULONG ulCPUCapInfo;
USHORT usNumberOfCyclesInPeriod;
USHORT usMaxNBVoltage;
USHORT usMinNBVoltage;
USHORT usBootUpNBVoltage;
ULONG ulHTLinkFreq; //in 10Khz
USHORT usMinHTLinkWidth;
USHORT usMaxHTLinkWidth;
USHORT usUMASyncStartDelay;
USHORT usUMADataReturnTime;
USHORT usLinkStatusZeroTime;
USHORT usDACEfuse; //for storing badgap value (for RS880 only)
ULONG ulHighVoltageHTLinkFreq; // in 10Khz
ULONG ulLowVoltageHTLinkFreq; // in 10Khz
USHORT usMaxUpStreamHTLinkWidth;
USHORT usMaxDownStreamHTLinkWidth;
USHORT usMinUpStreamHTLinkWidth;
USHORT usMinDownStreamHTLinkWidth;
USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
ULONG ulReserved3[96]; //must be 0x0
}ATOM_INTEGRATED_SYSTEM_INFO_V2;
/* ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
ulSystemConfig: Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state =0: system boots up at driver control state. Power state depends on PowerPlay table. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. Bit[3]=1: Only one power state(Performance) will be supported. =0: Multiple power states supported from PowerPlay table. Bit[4]=1: CLMC is supported and enabled on current system. =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. =0: Voltage settings is determined by powerplay table. Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. Bit[8]=1: CDLF is supported and enabled on current system. =0: CDLF is not supported or enabled on current system. Bit[9]=1: DLL Shut Down feature is enabled on current system. =0: DLL Shut Down feature is not enabled or supported on current system.
ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
[15:8] - Lane configuration attribute; [23:16]- Connector type, possible value: CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D CONNECTOR_OBJECT_ID_HDMI_TYPE_A CONNECTOR_OBJECT_ID_DISPLAYPORT CONNECTOR_OBJECT_ID_eDP [31:24]- Reserved
ulDDISlot2Config: Same as Slot1. ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. For IGP, Hypermemory is the only memory type showed in CCC.
ucUMAChannelNumber: how many channels for the UMA;
ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ucDockingPinBit: which bit in this register to read the pin status; ucDockingPinPolarity:Polarity of the pin when docked;
ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
ulHTLinkFreq: Bootup HT link Frequency in 10Khz. usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup. usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup.
usUMASyncStartDelay: Memory access latency, required for watermark calculation usUMADataReturnTime: Memory access latency, required for watermark calculation usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHTLinkFreq(bootup frequency). ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHighVoltageHTLinkFreq.
usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. usMaxDownStreamHTLinkWidth: same as above. usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. usMinDownStreamHTLinkWidth: same as above.
*/
// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR typedefstruct _ATOM_INTEGRATED_SYSTEM_INFO_V5
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulBootUpEngineClock; //in 10kHz unit
ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
ULONG ulBootUpUMAClock; //in 10kHz unit
ULONG ulReserved1[8]; //must be 0x0 for the reserved
ULONG ulBootUpReqDisplayVector;
ULONG ulOtherDisplayMisc;
ULONG ulReserved2[4]; //must be 0x0 for the reserved
ULONG ulSystemConfig; //TBD
ULONG ulCPUCapInfo; //TBD
USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
USHORT usBootUpNBVoltage; //boot up NB voltage
UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
ULONG ulReserved3[4]; //must be 0x0 for the reserved
ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
ULONG ulDDISlot2Config;
ULONG ulDDISlot3Config;
ULONG ulDDISlot4Config;
ULONG ulReserved4[4]; //must be 0x0 for the reserved
UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
UCHAR ucUMAChannelNumber;
USHORT usReserved;
ULONG ulReserved5[4]; //must be 0x0 for the reserved
ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
ULONG ulReserved6[61]; //must be 0x0
}ATOM_INTEGRATED_SYSTEM_INFO_V5;
// usDeviceSupport: // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported // Bit 2 = 0 - no TV1 support= 1- TV1 is supported // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported // Bit 8 = 0 - no CV support= 1- CV is supported // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported // //
/****************************************************************************/ // Structure used in MclkSS_InfoTable /****************************************************************************/ // ucI2C_ConfigID // [7:0] - I2C LINE Associate ID // = 0 - no I2C // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) // = 0, [6:0]=SW assisted I2C ID // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use // = 2, HW engine for Multimedia use // = 3-7 Reserved for future I2C engines // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
/****************************************************************************/ // Common Structure used in other structures /****************************************************************************/
/****************************************************************************/ // Structure used in LVDS_InfoTable // * Need a document to describe this table /****************************************************************************/ #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 #define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040
//ucTableFormatRevision=1 //ucTableContentRevision=1 typedefstruct _ATOM_LVDS_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_DTD_FORMAT sLCDTiming;
USHORT usModePatchTableOffset;
USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
USHORT usOffDelayInMs;
UCHAR ucPowerSequenceDigOntoDEin10Ms;
UCHAR ucPowerSequenceDEtoBLOnin10Ms;
UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
UCHAR ucPanelDefaultRefreshRate;
UCHAR ucPanelIdentification;
UCHAR ucSS_Id;
}ATOM_LVDS_INFO;
//ucTableFormatRevision=1 //ucTableContentRevision=2 typedefstruct _ATOM_LVDS_INFO_V12
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_DTD_FORMAT sLCDTiming;
USHORT usExtInfoTableOffset;
USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
USHORT usOffDelayInMs;
UCHAR ucPowerSequenceDigOntoDEin10Ms;
UCHAR ucPowerSequenceDEtoBLOnin10Ms;
UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
UCHAR ucPanelDefaultRefreshRate;
UCHAR ucPanelIdentification;
UCHAR ucSS_Id;
USHORT usLCDVenderID;
USHORT usLCDProductID;
UCHAR ucLCDPanel_SpecialHandlingCap;
UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
UCHAR ucReserved[2];
}ATOM_LVDS_INFO_V12;
//Definitions for ucLCDPanel_SpecialHandlingCap:
//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_READ_EDID 0x1
//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2
//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. #define LCDPANEL_CAP_eDP 0x4
//Color Bit Depth definition in EDID V1.4 @BYTE 14h //Bit 6 5 4 // 0 0 0 - Color bit depth is undefined // 0 0 1 - 6 Bits per Primary Color // 0 1 0 - 8 Bits per Primary Color // 0 1 1 - 10 Bits per Primary Color // 1 0 0 - 12 Bits per Primary Color // 1 0 1 - 14 Bits per Primary Color // 1 1 0 - 16 Bits per Primary Color // 1 1 1 - Reserved
/****************************************************************************/ // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=3 /****************************************************************************/ typedefstruct _ATOM_LCD_INFO_V13
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_DTD_FORMAT sLCDTiming;
USHORT usExtInfoTableOffset; union
{
USHORT usSupportedRefreshRate;
ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport;
};
ULONG ulReserved0;
UCHAR ucLCD_Misc; // Reorganized in V13 // Bit0: {=0:single, =1:dual}, // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, // Bit3:2: {Grey level} // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
UCHAR ucPanelDefaultRefreshRate;
UCHAR ucPanelIdentification;
UCHAR ucSS_Id;
USHORT usLCDVenderID;
USHORT usLCDProductID;
UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) // Bit7-3: Reserved
UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
UCHAR uceDPToLVDSRxId;
UCHAR ucLcdReservd;
ULONG ulReserved[2];
}ATOM_LCD_INFO_V13;
//Color Bit Depth definition in EDID V1.4 @BYTE 14h //Bit 6 5 4 // 0 0 0 - Color bit depth is undefined // 0 0 1 - 6 Bits per Primary Color // 0 1 0 - 8 Bits per Primary Color // 0 1 1 - 10 Bits per Primary Color // 1 0 0 - 12 Bits per Primary Color // 1 0 1 - 14 Bits per Primary Color // 1 1 0 - 16 Bits per Primary Color // 1 1 1 - Reserved
//Definitions for ucLCDPanel_SpecialHandlingCap:
//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
//uceDPToLVDSRxId #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init
//!! If the record below exits, it shoud always be the first record for easy use in command table!!! // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. typedefstruct _ATOM_LCD_MODE_CONTROL_CAP
{
UCHAR ucRecordType;
USHORT usLCDCap;
}ATOM_LCD_MODE_CONTROL_CAP;
/****************************Spread Spectrum Info Table Definitions **********************/
//ucTableFormatRevision=1 //ucTableContentRevision=2 typedefstruct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
UCHAR ucSS_Step;
UCHAR ucSS_Delay;
UCHAR ucSS_Id;
UCHAR ucRecommendedRef_Div;
UCHAR ucSS_Range; //it was reserved for V11
}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
#define ATOM_MAX_SS_ENTRY 16 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
typedefstruct _ATOM_DPCD_INFO
{
UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
}ATOM_DPCD_INFO;
#define ATOM_DPCD_MAX_LANE_MASK 0x1F
/**************************************************************************/ // VRAM usage and their defintions
// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). //#ifndef VESA_MEMORY_IN_64K_BLOCK //#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) //#endif
#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes #define ATOM_HWICON_INFOTABLE_SIZE 32 #define MAX_DTD_MODE_IN_VRAM 6 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) //20 bytes for Encoder Type and DPCD in STD EDID area #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
/***********************************************************************************/ // Structure used in VRAM_UsageByFirmwareTable // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm // at running time. // note2: From RV770, the memory is more than 32bit addressable, so we will change // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware // (in offset to start of memory address) is KB aligned instead of byte aligned. // Note3: /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
If (ulStartAddrUsedByFirmware!=0) FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose else //Non VGA case if (FB_Size<=2Gb) FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; else FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
// change verion to 1.5, when allow driver to allocate the vram area for command table access. typedefstruct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
{
ULONG ulStartAddrUsedByFirmware;
USHORT usFirmwareUseInKb;
USHORT usFBUsedByDrvInKb;
}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
/****************************************************************************/ // Structure used in GPIO_Pin_LUTTable /****************************************************************************/ typedefstruct _ATOM_GPIO_PIN_ASSIGNMENT
{
USHORT usGpioPin_AIndex;
UCHAR ucGpioPinBitShift;
UCHAR ucGPIO_ID;
}ATOM_GPIO_PIN_ASSIGNMENT;
//ucGPIO_ID pre-define id for multiple usage // GPIO use to control PCIE_VDDC in certain SLT board #define PCIE_VDDC_CONTROL_GPIO_PINID 56
//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable #define PP_AC_DC_SWITCH_GPIO_PINID 60 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable #define VDDC_VRHOT_GPIO_PINID 61 //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled #define VDDC_PCC_GPIO_PINID 62 // Only used on certain SLT/PA board to allow utility to cut Efuse. #define EFUSE_CUT_ENABLE_GPIO_PINID 63 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= #define DRAM_SELF_REFRESH_GPIO_PINID 64 // Thermal interrupt output->system thermal chip GPIO pin #define THERMAL_INT_OUTPUT_GPIO_PINID 65
// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode //Line 3 out put 5V. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
//Line 3 out put 2.2V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
//Line 3 out put 0V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
typedefstruct _ATOM_COMPONENT_VIDEO_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usMask_PinRegisterIndex;
USHORT usEN_PinRegisterIndex;
USHORT usY_PinRegisterIndex;
USHORT usA_PinRegisterIndex;
UCHAR ucBitShift;
UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
ATOM_DTD_FORMAT sReserved; // must be zeroed out
UCHAR ucMiscInfo;
UCHAR uc480i;
UCHAR uc480p;
UCHAR uc720p;
UCHAR uc1080i;
UCHAR ucLetterBoxMode;
UCHAR ucReserved[3];
UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
}ATOM_COMPONENT_VIDEO_INFO;
typedefstruct _ATOM_OBJECT //each object has this structure
{
USHORT usObjectID;
USHORT usSrcDstTableOffset;
USHORT usRecordOffset; //this pointing to a bunch of records defined below
USHORT usReserved;
}ATOM_OBJECT;
typedefstruct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
{
UCHAR ucNumberOfObjects;
UCHAR ucPadding[3];
ATOM_OBJECT asObjects[];
}ATOM_OBJECT_TABLE;
typedefstruct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
{
UCHAR ucNumberOfSrc;
USHORT usSrcObjectID[1];
UCHAR ucNumberOfDst;
USHORT usDstObjectID[1];
}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
//Two definitions below are for OPM on MXM module designs
//ucChannelMapping are defined as following //for DP connector, eDP, DP to VGA/LVDS //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 typedefstruct _ATOM_DP_CONN_CHANNEL_MAPPING
{ #if ATOM_BIG_ENDIAN
UCHAR ucDP_Lane3_Source:2;
UCHAR ucDP_Lane2_Source:2;
UCHAR ucDP_Lane1_Source:2;
UCHAR ucDP_Lane0_Source:2; #else
UCHAR ucDP_Lane0_Source:2;
UCHAR ucDP_Lane1_Source:2;
UCHAR ucDP_Lane2_Source:2;
UCHAR ucDP_Lane3_Source:2; #endif
}ATOM_DP_CONN_CHANNEL_MAPPING;
//for DVI/HDMI, in dual link case, both links have to have same mapping. //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 typedefstruct _ATOM_DVI_CONN_CHANNEL_MAPPING
{ #if ATOM_BIG_ENDIAN
UCHAR ucDVI_CLK_Source:2;
UCHAR ucDVI_DATA0_Source:2;
UCHAR ucDVI_DATA1_Source:2;
UCHAR ucDVI_DATA2_Source:2; #else
UCHAR ucDVI_DATA2_Source:2;
UCHAR ucDVI_DATA1_Source:2;
UCHAR ucDVI_DATA0_Source:2;
UCHAR ucDVI_CLK_Source:2; #endif
}ATOM_DVI_CONN_CHANNEL_MAPPING;
typedefstruct _EXT_DISPLAY_PATH
{
USHORT usDeviceTag; //A bit vector to show what devices are supported
USHORT usDeviceACPIEnum; //16bit device ACPI id.
USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
USHORT usExtEncoderObjId; //external encoder object id union{
UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
};
UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
USHORT usCaps;
USHORT usReserved;
}EXT_DISPLAY_PATH;
typedefstruct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
UCHAR uc3DStereoPinId; // use for eDP panel
UCHAR ucRemoteDisplayConfig;
UCHAR uceDPToLVDSRxId;
UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value
UCHAR Reserved[3]; // for potential expansion
}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
//Related definitions, all records are different but they have a common header typedefstruct _ATOM_COMMON_RECORD_HEADER
{
UCHAR ucRecordType; //An emun to indicate the record type
UCHAR ucRecordSize; //The size of the whole record in byte
}ATOM_COMMON_RECORD_HEADER;
#define ATOM_I2C_RECORD_TYPE 1 #define ATOM_HPD_INT_RECORD_TYPE 2 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 #define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22
//Must be updated when new record type is added,equal to that record definition! #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE
typedefstruct _ATOM_I2C_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
ATOM_I2C_ID_CONFIG sucI2cId;
UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
}ATOM_I2C_RECORD;
typedefstruct _ATOM_HPD_INT_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
UCHAR ucPlugged_PinState;
}ATOM_HPD_INT_RECORD;
typedefstruct _ATOM_CONNECTOR_DEVICE_TAG
{
ULONG ulACPIDeviceEnum; //Reserved for now
USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
USHORT usPadding;
}ATOM_CONNECTOR_DEVICE_TAG;
typedefstruct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucNumberOfDevice;
UCHAR ucReserved;
ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
typedefstruct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucConfigGPIOID;
UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
UCHAR ucFlowinGPIPID;
UCHAR ucExtInGPIPID;
}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
typedefstruct _ATOM_ENCODER_FPGA_CONTROL_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucCTL1GPIO_ID;
UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
UCHAR ucCTL2GPIO_ID;
UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
UCHAR ucCTL3GPIO_ID;
UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
UCHAR ucCTLFPGA_IN_ID;
UCHAR ucPadding[3];
}ATOM_ENCODER_FPGA_CONTROL_RECORD;
typedefstruct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
typedefstruct _ATOM_JTAG_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucTMSGPIO_ID;
UCHAR ucTMSGPIOState; //Set to 1 when it's active high
UCHAR ucTCKGPIO_ID;
UCHAR ucTCKGPIOState; //Set to 1 when it's active high
UCHAR ucTDOGPIO_ID;
UCHAR ucTDOGPIOState; //Set to 1 when it's active high
UCHAR ucTDIGPIO_ID;
UCHAR ucTDIGPIOState; //Set to 1 when it's active high
UCHAR ucPadding[2];
}ATOM_JTAG_RECORD;
//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually typedefstruct _ATOM_GPIO_PIN_CONTROL_PAIR
{
UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
}ATOM_GPIO_PIN_CONTROL_PAIR;
typedefstruct _ATOM_OBJECT_GPIO_CNTL_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucFlags; // Future expnadibility
UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
ATOM_GPIO_PIN_CONTROL_PAIR asGpio[]; // the real gpio pin pair determined by number of pins ucNumberOfPins
}ATOM_OBJECT_GPIO_CNTL_RECORD;
//Definitions for GPIO pin state #define GPIO_PIN_TYPE_INPUT 0x00 #define GPIO_PIN_TYPE_OUTPUT 0x10 #define GPIO_PIN_TYPE_HW_CONTROL 0x20
//For GPIO_PIN_TYPE_OUTPUT the following is defined #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
// Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9
typedefstruct _ATOM_ENCODER_DVO_CF_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
ULONG ulStrengthControl; // DVOA strength control for CF
UCHAR ucPadding[2];
}ATOM_ENCODER_DVO_CF_RECORD;
// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN #define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not. #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. #define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board.
typedefstruct _ATOM_ENCODER_CAP_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader; union {
USHORT usEncoderCap; struct { #if ATOM_BIG_ENDIAN
USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. #else
USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
USHORT usReserved:14; // Bit1-15 may be defined for other capability in future #endif
};
};
}ATOM_ENCODER_CAP_RECORD;
// Used after SI typedefstruct _ATOM_ENCODER_CAP_RECORD_V2
{
ATOM_COMMON_RECORD_HEADER sheader; union {
USHORT usEncoderCap; struct { #if ATOM_BIG_ENDIAN
USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable #else
USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
USHORT usReserved:12; // Bit4-15 may be defined for other capability in future #endif
};
};
}ATOM_ENCODER_CAP_RECORD_V2;
// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
typedefstruct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
UCHAR ucMuxControlPin;
UCHAR ucMuxState[2]; //for alligment purpose
}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
typedefstruct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
{
ATOM_COMMON_RECORD_HEADER sheader;
UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
typedefstruct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
{
ATOM_COMMON_RECORD_HEADER sheader;
ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
typedefstruct _ATOM_OBJECT_LINK_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader;
USHORT usObjectID; //could be connector, encorder or other object in object.h
}ATOM_OBJECT_LINK_RECORD;
typedefstruct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD
{
ATOM_COMMON_RECORD_HEADER sheader; // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
UCHAR ucMaxTmdsClkRateIn2_5Mhz;
UCHAR ucReserved;
} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD;
/****************************************************************************/ // Structure used in XXXX /****************************************************************************/ typedefstruct _ATOM_VOLTAGE_INFO_HEADER
{
USHORT usVDDCBaseLevel; //In number of 50mv unit
USHORT usReserved; //For possible extension table offset
UCHAR ucNumOfVoltageEntries;
UCHAR ucBytesPerVoltageEntry;
UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
UCHAR ucDefaultVoltageEntry;
UCHAR ucVoltageControlI2cLine;
UCHAR ucVoltageControlAddress;
UCHAR ucVoltageControlOffset;
}ATOM_VOLTAGE_INFO_HEADER;
typedefstruct _ATOM_VOLTAGE_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_VOLTAGE_INFO_HEADER viHeader;
UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
}ATOM_VOLTAGE_INFO;
typedefstruct _ATOM_VOLTAGE_FORMULA
{
USHORT usVoltageBaseLevel; // In number of 1mv unit
USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
UCHAR ucReserved;
UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
}ATOM_VOLTAGE_FORMULA;
typedefstruct _VOLTAGE_LUT_ENTRY
{
USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
USHORT usVoltageValue; // The corresponding Voltage Value, in mV
}VOLTAGE_LUT_ENTRY;
typedefstruct _ATOM_VOLTAGE_FORMULA_V2
{
UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
UCHAR ucReserved[3];
VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
}ATOM_VOLTAGE_FORMULA_V2;
typedefstruct _ATOM_VOLTAGE_CONTROL
{
UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
UCHAR ucVoltageControlI2cLine;
UCHAR ucVoltageControlAddress;
UCHAR ucVoltageControlOffset;
USHORT usGpioPin_AIndex; //GPIO_PAD register index
UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
UCHAR ucReserved;
}ATOM_VOLTAGE_CONTROL;
typedefstruct _ATOM_VOLTAGE_OBJECT
{
UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
UCHAR ucSize; //Size of Object
ATOM_VOLTAGE_CONTROL asControl; //describ how to control
ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
}ATOM_VOLTAGE_OBJECT;
typedefstruct _ATOM_VOLTAGE_OBJECT_V2
{
UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
UCHAR ucSize; //Size of Object
ATOM_VOLTAGE_CONTROL asControl; //describ how to control
ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
}ATOM_VOLTAGE_OBJECT_V2;
typedefstruct _ATOM_VOLTAGE_OBJECT_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
}ATOM_VOLTAGE_OBJECT_INFO;
typedefstruct _ATOM_VOLTAGE_OBJECT_INFO_V2
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
}ATOM_VOLTAGE_OBJECT_INFO_V2;
typedefstruct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
USHORT usSize; //Size of Object
}ATOM_VOLTAGE_OBJECT_HEADER_V3;
// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_EVV 8 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
typedefstruct _VOLTAGE_LUT_ENTRY_V2
{
ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
USHORT usVoltageValue; // The corresponding Voltage Value, in mV
}VOLTAGE_LUT_ENTRY_V2;
typedefstruct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
{
USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
USHORT usVoltageId;
USHORT usLeakageId; // The corresponding Voltage Value, in mV
}LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
typedefstruct _ATOM_I2C_VOLTAGE_OBJECT_V3
{
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
UCHAR ucVoltageControlI2cLine;
UCHAR ucVoltageControlAddress;
UCHAR ucVoltageControlOffset;
UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
UCHAR ulReserved[3];
VOLTAGE_LUT_ENTRY asVolI2cLut[]; // end with 0xff
}ATOM_I2C_VOLTAGE_OBJECT_V3;
typedefstruct _ATOM_GPIO_VOLTAGE_OBJECT_V3
{
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
UCHAR ucPhaseDelay; // phase delay in unit of micro second
UCHAR ucReserved;
ULONG ulGpioMaskVal; // GPIO Mask value
VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[];
}ATOM_GPIO_VOLTAGE_OBJECT_V3;
typedefstruct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
{
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12
UCHAR ucLeakageCntlId; // default is 0
UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
UCHAR ucReserved[2];
ULONG ulMaxVoltageLevel;
LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[];
}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
typedefstruct _ATOM_SVID2_VOLTAGE_OBJECT_V3
{
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 // 14:7 - PSI0_VID // 6 - PSI0_EN // 5 - PSI1 // 4:2 - load line slope trim. // 1:0 - offset trim,
USHORT usLoadLine_PSI; // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
ULONG ulReserved;
}ATOM_SVID2_VOLTAGE_OBJECT_V3;
typedefstruct _ATOM_EVV_DPM_INFO
{
ULONG ulDPMSclk; // DPM state SCLK
USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv
UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable
UCHAR ucDPMState; // DPMState0~7
} ATOM_EVV_DPM_INFO;
typedefstruct _ATOM_VOLTAGE_OBJECT_INFO_V3_1
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control
}ATOM_VOLTAGE_OBJECT_INFO_V3_1;
typedefstruct _ATOM_ASIC_PROFILE_VOLTAGE
{
UCHAR ucProfileId;
UCHAR ucReserved;
USHORT usSize;
USHORT usEfuseSpareStartAddr;
USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
}ATOM_ASIC_PROFILE_VOLTAGE;
typedefstruct _ATOM_ASIC_PROFILING_INFO_V2_1
{
ATOM_COMMON_TABLE_HEADER asHeader;
UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
UCHAR ucElbVDDC_Num;
USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
UCHAR ucElbVDDCI_Num;
USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
}ATOM_ASIC_PROFILING_INFO_V2_1;
//Here is parameter to convert Efuse value to Measure value //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 typedefstruct _EFUSE_LOGISTIC_FUNC_PARAM
{
USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
UCHAR ucEfuseLength; // Efuse bits length,
ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
}EFUSE_LOGISTIC_FUNC_PARAM;
//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) typedefstruct _EFUSE_LINEAR_FUNC_PARAM
{
USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
UCHAR ucEfuseLength; // Efuse bits length,
ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
ULONG ulEfuseMin; // Min
}EFUSE_LINEAR_FUNC_PARAM;
typedefstruct _ATOM_POWER_SOURCE_OBJECT
{
UCHAR ucPwrSrcId; // Power source
UCHAR ucPwrSensorType; // GPIO, I2C or none
UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
UCHAR ucPwrSensActiveState; // high active or low active
UCHAR ucReserve[3]; // reserve
USHORT usSensPwr; // in unit of watt
}ATOM_POWER_SOURCE_OBJECT;
typedefstruct _ATOM_CLK_VOLT_CAPABILITY
{
ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
}ATOM_CLK_VOLT_CAPABILITY;
typedefstruct _ATOM_CLK_VOLT_CAPABILITY_V2
{
USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv,
ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
}ATOM_CLK_VOLT_CAPABILITY_V2;
typedefstruct _ATOM_AVAILABLE_SCLK_LIST
{
ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
}ATOM_AVAILABLE_SCLK_LIST;
// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
// not used any more #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08
/********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V6 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement.
ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_CRT2_SUPPORT 0x0010 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 ulOtherDisplayMisc: Other display related flags, not defined yet. ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[3]=0: Enable HW AUX mode detection logic =1: Disable HW AUX mode dettion logic ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional.
2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional.
ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State usNBP1Voltage: VID for voltage on NB P1 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
**********************************************************************************************************************/
// this Table is used for Liano/Ontario APU typedefstruct _ATOM_FUSION_SYSTEM_INFO_V1
{
ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;
ULONG ulPowerplayTable[128];
}ATOM_FUSION_SYSTEM_INFO_V1;
typedefstruct _ATOM_TDP_CONFIG_BITS
{ #if ATOM_BIG_ENDIAN
ULONG uReserved:2;
ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
ULONG uCTDP_Value:14; // Override value in tens of milli watts
ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) #else
ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
ULONG uCTDP_Value:14; // Override value in tens of milli watts
ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
ULONG uReserved:2; #endif
}ATOM_TDP_CONFIG_BITS;
/********************************************************************************************************************** ATOM_FUSION_SYSTEM_INFO_V1 Description sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
**********************************************************************************************************************/
// ulGPUCapInfo #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 #define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS 0x10 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000
//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000
/********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement.
ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS bit[3]=0: VBIOS fast boot is disable =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) =1: DP mode use single PLL mode bit[3]=0: Enable AUX HW mode detection logic =1: Disable AUX HW mode detection logic
ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional.
2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional.
ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State usNBP1Voltage: VID for voltage on NB P1 State usNBP2Voltage: VID for voltage on NB P2 State usNBP3Voltage: VID for voltage on NB P3 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.
/********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002
ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS bit[3]=0: VBIOS fast boot is disable =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional.
2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional.
ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. Bit[3]=0: GNB DPM is disabled =1: GNB DPM is enabled ulCPUCapInfo: TBD
usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. ucUMAChannelNumber: System memory channel numbers.
strVBIOSMsg[40]: VBIOS boot up customized message string
sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.
usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded sExtDispConnInfo: Display connector information table provided to VBIOS
// ulGPUCapInfo #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08 #define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS 0x10 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available #define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000 //ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. #define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000
typedefstruct _CAMERA_MODULE_INFO
{
UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
UCHAR strModuleName[8];
DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor
} CAMERA_MODULE_INFO;
// this Table is used for Kaveri/Kabini APU typedefstruct _ATOM_FUSION_SYSTEM_INFO_V2
{
ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
}ATOM_FUSION_SYSTEM_INFO_V2;
typedefstruct _ATOM_FUSION_SYSTEM_INFO_V3
{
ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable
}ATOM_FUSION_SYSTEM_INFO_V3;
#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800
/**************************************************************************/ // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design //Memory SS Info Table //Define Memory Clock SS chip ID #define ICS91719 1 #define ICS91720 2
//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol typedefstruct _ATOM_I2C_DATA_RECORD
{
UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
UCHAR ucI2CData[]; //I2C data in bytes, should be less than 16 bytes usually
}ATOM_I2C_DATA_RECORD;
//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information typedefstruct _ATOM_I2C_DEVICE_SETUP_INFO
{
ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
UCHAR ucSSChipID; //SS chip being used
UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
UCHAR ucNumOfI2CDataRecords; //number of data block
ATOM_I2C_DATA_RECORD asI2CData[];
}ATOM_I2C_DEVICE_SETUP_INFO;
typedefstruct _ATOM_ASIC_SS_ASSIGNMENT
{
ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
UCHAR ucClockIndication; //Indicate which clock source needs SS
UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
UCHAR ucReserved[2];
}ATOM_ASIC_SS_ASSIGNMENT;
//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. //SS is not required or enabled if a match is not found. #define ASIC_INTERNAL_MEMORY_SS 1 #define ASIC_INTERNAL_ENGINE_SS 2 #define ASIC_INTERNAL_UVD_SS 3 #define ASIC_INTERNAL_SS_ON_TMDS 4 #define ASIC_INTERNAL_SS_ON_HDMI 5 #define ASIC_INTERNAL_SS_ON_LVDS 6 #define ASIC_INTERNAL_SS_ON_DP 7 #define ASIC_INTERNAL_SS_ON_DCPLL 8 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 #define ASIC_INTERNAL_VCE_SS 10 #define ASIC_INTERNAL_GPUPLL_SS 11
typedefstruct _ATOM_ASIC_SS_ASSIGNMENT_V2
{
ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
UCHAR ucClockIndication; //Indicate which clock source needs SS
UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
UCHAR ucReserved[2];
}ATOM_ASIC_SS_ASSIGNMENT_V2;
typedefstruct _ATOM_ASIC_INTERNAL_SS_INFO_V2
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[]; //this is point only.
}ATOM_ASIC_INTERNAL_SS_INFO_V2;
typedefstruct _ATOM_ASIC_SS_ASSIGNMENT_V3
{
ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
UCHAR ucClockIndication; //Indicate which clock source needs SS
UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
UCHAR ucReserved[2];
}ATOM_ASIC_SS_ASSIGNMENT_V3;
#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L //Below two definitions are not supported in pplib, but in the old powerplay in DAL #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
/****************************************************************************/ //Portion II: Definitinos only used in Driver /****************************************************************************/
typedefstruct _GPIO_PIN_CONTROL_PARAMETERS
{
UCHAR ucGPIO_ID; //return value, read from GPIO pins
UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
}GPIO_PIN_CONTROL_PARAMETERS;
typedefstruct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
{
USHORT usHight; // Image Hight
USHORT usWidth; // Image Width
UCHAR ucSurface; // Surface 1 or 2
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
typedefstruct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
{
ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
typedefstruct _MEMORY_CLEAN_UP_PARAMETERS
{
USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
USHORT usMemorySize; //8Kb blocks aligned
}MEMORY_CLEAN_UP_PARAMETERS;
typedefstruct _ATOM_TV_MODE
{
UCHAR ucVMode_Num; //Video mode number
UCHAR ucTV_Mode_Num; //Internal TV mode number
}ATOM_TV_MODE;
typedefstruct _ATOM_BIOS_INT_TVSTD_MODE
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
}ATOM_BIOS_INT_TVSTD_MODE;
typedefstruct _ATOM_TV_MODE_SCALER_PTR
{
USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
UCHAR ucTV_Mode_Num;
}ATOM_TV_MODE_SCALER_PTR;
typedefstruct _ATOM_STANDARD_VESA_TIMING
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
}ATOM_STANDARD_VESA_TIMING;
typedefstruct _ATOM_INIT_REG_INDEX_FORMAT{
USHORT usRegIndex; // MC register index
UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
}ATOM_INIT_REG_INDEX_FORMAT;
typedefstruct _ATOM_INIT_REG_BLOCK{
USHORT usRegIndexTblSize; //size of asRegIndexBuf
USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
}ATOM_INIT_REG_BLOCK;
#define END_OF_REG_INDEX_BLOCK 0x0ffff #define END_OF_REG_DATA_BLOCK 0x00000000 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS #define CLOCK_RANGE_HIGHEST 0x00ffffff
#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF typedefstruct _ATOM_VRAM_MODULE_V1
{
ULONG ulReserved;
USHORT usEMRSValue;
USHORT usMRSValue;
USHORT usReserved;
UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
UCHAR ucRow; // Number of Row,in power of 2;
UCHAR ucColumn; // Number of Column,in power of 2;
UCHAR ucBank; // Nunber of Bank;
UCHAR ucRank; // Number of Rank, in power of 2
UCHAR ucChannelNum; // Number of channel;
UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
UCHAR ucReserved[2];
}ATOM_VRAM_MODULE_V1;
typedefstruct _ATOM_VRAM_MODULE_V2
{
ULONG ulReserved;
ULONG ulFlags; // To enable/disable functionalities based on memory type
ULONG ulEngineClock; // Override of default engine clock for particular memory type
ULONG ulMemoryClock; // Override of default memory clock for particular memory type
USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
USHORT usEMRSValue;
USHORT usMRSValue;
USHORT usReserved;
UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
UCHAR ucRow; // Number of Row,in power of 2;
UCHAR ucColumn; // Number of Column,in power of 2;
UCHAR ucBank; // Nunber of Bank;
UCHAR ucRank; // Number of Rank, in power of 2
UCHAR ucChannelNum; // Number of channel;
UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
UCHAR ucRefreshRateFactor;
UCHAR ucReserved[3];
}ATOM_VRAM_MODULE_V2;
typedefstruct _ATOM_MEMORY_TIMING_FORMAT
{
ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing union{
USHORT usMRS; // mode register
USHORT usDDR3_MR0;
}; union{
USHORT usEMRS; // extended mode register
USHORT usDDR3_MR1;
};
UCHAR ucCL; // CAS latency
UCHAR ucWL; // WRITE Latency
UCHAR uctRAS; // tRAS
UCHAR uctRC; // tRC
UCHAR uctRFC; // tRFC
UCHAR uctRCDR; // tRCDR
UCHAR uctRCDW; // tRCDW
UCHAR uctRP; // tRP
UCHAR uctRRD; // tRRD
UCHAR uctWR; // tWR
UCHAR uctWTR; // tWTR
UCHAR uctPDIX; // tPDIX
UCHAR uctFAW; // tFAW
UCHAR uctAOND; // tAOND union
{ struct {
UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
UCHAR ucReserved;
};
USHORT usDDR3_MR2;
};
}ATOM_MEMORY_TIMING_FORMAT;
typedefstruct _ATOM_MEMORY_FORMAT
{
ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock union{
USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
USHORT usDDR3_Reserved; // Not used for DDR3 memory
}; union{
USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
USHORT usDDR3_MR3; // Used for DDR3 memory
};
UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
UCHAR ucRow; // Number of Row,in power of 2;
UCHAR ucColumn; // Number of Column,in power of 2;
UCHAR ucBank; // Nunber of Bank;
UCHAR ucRank; // Number of Rank, in power of 2
UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock
}ATOM_MEMORY_FORMAT;
typedefstruct _ATOM_VRAM_MODULE_V3
{
ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
USHORT usSize; // size of ATOM_VRAM_MODULE_V3
USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
UCHAR ucChannelNum; // board dependent parameter:Number of channel;
UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
UCHAR ucFlag; // To enable/disable functionalities based on memory type
ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
}ATOM_VRAM_MODULE_V3;
typedefstruct _ATOM_VRAM_MODULE_V4
{
ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
USHORT usReserved;
UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
UCHAR ucChannelNum; // Number of channels present in this module config
UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
UCHAR ucFlag; // To enable/disable functionalities based on memory type
UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
UCHAR ucVREFI; // board dependent parameter
UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
UCHAR ucReserved[3];
//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level union{
USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
USHORT usDDR3_Reserved;
}; union{
USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
USHORT usDDR3_MR3; // Used for DDR3 memory
};
UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
UCHAR ucReserved2[2];
ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
}ATOM_VRAM_MODULE_V4;
typedefstruct _ATOM_VRAM_MODULE_V5
{
ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
USHORT usReserved;
UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
UCHAR ucChannelNum; // Number of channels present in this module config
UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
UCHAR ucFlag; // To enable/disable functionalities based on memory type
UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
UCHAR ucVREFI; // board dependent parameter
UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
UCHAR ucReserved[3];
//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
}ATOM_VRAM_MODULE_V5;
typedefstruct _ATOM_VRAM_MODULE_V6
{
ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
USHORT usReserved;
UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
UCHAR ucChannelNum; // Number of channels present in this module config
UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
UCHAR ucFlag; // To enable/disable functionalities based on memory type
UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
UCHAR ucVREFI; // board dependent parameter
UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
UCHAR ucReserved[3];
//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
}ATOM_VRAM_MODULE_V6;
typedefstruct _ATOM_VRAM_MODULE_V7
{ // Design Specific Values
ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
USHORT usEnableChannels; // bit vector which indicate which channels are enabled
UCHAR ucExtMemoryID; // Current memory module ID
UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
UCHAR ucChannelNum; // Number of mem. channels supported in this module
UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
UCHAR ucVREFI; // Not used.
UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
USHORT usSEQSettingOffset;
UCHAR ucReserved; // Memory Module specific values
USHORT usEMRS2Value; // EMRS2/MR2 Value.
USHORT usEMRS3Value; // EMRS3/MR3 Value.
UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth char strMemPNString[20]; // part number end with '0'.
}ATOM_VRAM_MODULE_V7;
typedefstruct _ATOM_VRAM_MODULE_V8
{ // Design Specific Values
ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
USHORT usEnableChannels; // bit vector which indicate which channels are enabled
UCHAR ucExtMemoryID; // Current memory module ID
UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
UCHAR ucChannelNum; // Number of mem. channels supported in this module
UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
UCHAR ucVREFI; // Not used.
USHORT usReserved; // Not used
USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
UCHAR ucMcTunningSetId; // MC phy registers set per.
UCHAR ucRowNum; // Memory Module specific values
USHORT usEMRS2Value; // EMRS2/MR2 Value.
USHORT usEMRS3Value; // EMRS3/MR3 Value.
UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
ULONG ulChannelMapCfg1; // channel mapping for channel8~15
ULONG ulBankMapCfg;
ULONG ulReserved; char strMemPNString[20]; // part number end with '0'.
}ATOM_VRAM_MODULE_V8;
typedefstruct _ATOM_VRAM_INFO_V2
{
ATOM_COMMON_TABLE_HEADER sHeader;
UCHAR ucNumOfVRAMModule;
ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
}ATOM_VRAM_INFO_V2;
typedefstruct _ATOM_VRAM_INFO_V3
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
USHORT usRerseved;
UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
UCHAR ucNumOfVRAMModule;
ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
}ATOM_VRAM_INFO_V3;
#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
typedefstruct _ATOM_VRAM_INFO_V4
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
USHORT usRerseved;
UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
UCHAR ucReservde[4];
UCHAR ucNumOfVRAMModule;
ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
}ATOM_VRAM_INFO_V4;
typedefstruct _ATOM_VRAM_INFO_HEADER_V2_1
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
USHORT usReserved[3];
UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
UCHAR ucReserved;
ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
}ATOM_VRAM_INFO_HEADER_V2_1;
typedefstruct _ATOM_VRAM_INFO_HEADER_V2_2
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set
USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping
USHORT usReserved1;
UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
}ATOM_VRAM_INFO_HEADER_V2_2;
typedefstruct _VESA_MODE_INFO_BLOCK
{ // Mandatory information for all VBE revisions
USHORT ModeAttributes; // dw ? ; mode attributes
UCHAR WinAAttributes; // db ? ; window A attributes
UCHAR WinBAttributes; // db ? ; window B attributes
USHORT WinGranularity; // dw ? ; window granularity
USHORT WinSize; // dw ? ; window size
USHORT WinASegment; // dw ? ; window A start segment
USHORT WinBSegment; // dw ? ; window B start segment
ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
USHORT BytesPerScanLine;// dw ? ; bytes per scan line
//; Mandatory information for VBE 1.2 and above
USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
UCHAR XCharSize; // db ? ; character cell width in pixels
UCHAR YCharSize; // db ? ; character cell height in pixels
UCHAR NumberOfPlanes; // db ? ; number of memory planes
UCHAR BitsPerPixel; // db ? ; bits per pixel
UCHAR NumberOfBanks; // db ? ; number of banks
UCHAR MemoryModel; // db ? ; memory model type
UCHAR BankSize; // db ? ; bank size in KB
UCHAR NumberOfImagePages;// db ? ; number of images
UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
//; Direct Color fields(required for direct/6 and YUV/7 memory models)
UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
//; Mandatory information for VBE 2.0 and above
ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
ULONG Reserved_1; // dd 0 ; reserved - always set to 0
USHORT Reserved_2; // dw 0 ; reserved - always set to 0
//; Mandatory information for VBE 3.0 and above
USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
UCHAR Reserved; // db 190 dup (0)
} VESA_MODE_INFO_BLOCK;
#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
/****************************************************************************/ // Structures used by HW_Misc_OperationTable /****************************************************************************/ typedefstruct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
{
UCHAR ucCmd; // Input: To tell which action to take
UCHAR ucReserved[3];
ULONG ulReserved;
}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
typedefstruct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
{
UCHAR ucReturnCode; // Output: Return value base on action was taken
UCHAR ucReserved[3];
ULONG ulReserved;
}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
// DIGTransmitterInfoTable structure used to program UNIPHY settings typedefstruct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
}DIG_TRANSMITTER_INFO_HEADER_V3_1;
typedefstruct _DIG_TRANSMITTER_INFO_HEADER_V3_2{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
}DIG_TRANSMITTER_INFO_HEADER_V3_2;
typedefstruct _DIG_TRANSMITTER_INFO_HEADER_V3_3{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock
USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock
USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock
USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock
}DIG_TRANSMITTER_INFO_HEADER_V3_3;
typedefstruct _GFX_HAVESTING_PARAMETERS {
UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
UCHAR ucReserved; //reserved
UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
} GFX_HAVESTING_PARAMETERS;
/****************************************************************************/ //Portion VI: Definitinos for vbios MC scratch registers that driver used /****************************************************************************/
/****************************************************************************/ //Portion VII: Definitinos being oboselete /****************************************************************************/
//========================================================================================== //Remove the definitions below when driver is ready! typedefstruct _ATOM_DAC_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usMaxFrequency; // in 10kHz unit
USHORT usReserved;
}ATOM_DAC_INFO;
typedefstruct _ATOM_MISC_CONTROL_INFO
{
USHORT usFrequency;
UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
UCHAR ucPLL_DutyCycle; // PLL duty cycle control
UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
}ATOM_MISC_CONTROL_INFO;
typedefstruct _ATOM_ENCODER_ANALOG_ATTRIBUTE
{
UCHAR ucTVStandard; //Same as TV standards defined above,
UCHAR ucPadding[1];
}ATOM_ENCODER_ANALOG_ATTRIBUTE;
typedefstruct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
{
UCHAR ucAttribute; //Same as other digital encoder attributes defined above
UCHAR ucPadding[1];
}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
typedefstruct _DVO_ENCODER_CONTROL_PS_ALLOCATION
{
DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
}DVO_ENCODER_CONTROL_PS_ALLOCATION;
typedefstruct _ATOM_XTMDS_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
USHORT usSingleLinkMaxFrequency;
ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
UCHAR ucXtransimitterID;
UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters // due to design. This ID is used to alert driver that the sequence is not "standard"!
UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
}ATOM_XTMDS_INFO;
#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
//ucTableFormatRevision=1 //ucTableContentRevision=1 typedefstruct _ATOM_POWERMODE_INFO
{
ULONG ulMiscInfo; //The power level should be arranged in ascending order
ULONG ulReserved1; // must set to 0
ULONG ulReserved2; // must set to 0
USHORT usEngineClock;
USHORT usMemoryClock;
UCHAR ucVoltageDropIndex; // index to GPIO table
UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
UCHAR ucMinTemperature;
UCHAR ucMaxTemperature;
UCHAR ucNumPciELanes; // number of PCIE lanes
}ATOM_POWERMODE_INFO;
//ucTableFormatRevision=2 //ucTableContentRevision=1 typedefstruct _ATOM_POWERMODE_INFO_V2
{
ULONG ulMiscInfo; //The power level should be arranged in ascending order
ULONG ulMiscInfo2;
ULONG ulEngineClock;
ULONG ulMemoryClock;
UCHAR ucVoltageDropIndex; // index to GPIO table
UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
UCHAR ucMinTemperature;
UCHAR ucMaxTemperature;
UCHAR ucNumPciELanes; // number of PCIE lanes
}ATOM_POWERMODE_INFO_V2;
//ucTableFormatRevision=2 //ucTableContentRevision=2 typedefstruct _ATOM_POWERMODE_INFO_V3
{
ULONG ulMiscInfo; //The power level should be arranged in ascending order
ULONG ulMiscInfo2;
ULONG ulEngineClock;
ULONG ulMemoryClock;
UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
UCHAR ucMinTemperature;
UCHAR ucMaxTemperature;
UCHAR ucNumPciELanes; // number of PCIE lanes
UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
}ATOM_POWERMODE_INFO_V3;
//New device naming, remove them when both DAL/VBIOS is ready #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
//These two lines will be removed for sure in a few days, will follow up with Michael V. #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
#pragmapack() // BIOS data must use byte alignment
#pragmapack(1)
typedefstruct _ATOM_HOLE_INFO
{
USHORT usOffset; // offset of the hole ( from the start of the binary )
USHORT usLength; // length of the hole ( in bytes )
}ATOM_HOLE_INFO;
typedefstruct _ATOM_SERVICE_DESCRIPTION
{
UCHAR ucRevision; // Holes set revision
UCHAR ucAlgorithm; // Hash algorithm
UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
UCHAR ucReserved;
USHORT usSigOffset; // Signature offset ( from the start of the binary )
USHORT usSigLength; // Signature length
}ATOM_SERVICE_DESCRIPTION;
typedefstruct _ATOM_SERVICE_INFO
{
ATOM_COMMON_TABLE_HEADER asHeader;
ATOM_SERVICE_DESCRIPTION asDescr;
UCHAR ucholesNo; // number of holes that follow
ATOM_HOLE_INFO holes[1]; // array of hole descriptions
}ATOM_SERVICE_INFO;
#pragmapack() // BIOS data must use byte alignment
// // AMD ACPI Table // #pragmapack(1)
typedefstruct {
ULONG Signature;
ULONG TableLength; //Length
UCHAR Revision;
UCHAR Checksum;
UCHAR OemId[6];
UCHAR OemTableId[8]; //UINT64 OemTableId;
ULONG OemRevision;
ULONG CreatorId;
ULONG CreatorRevision;
} AMD_ACPI_DESCRIPTION_HEADER; /* //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h typedef struct { UINT32 Signature; //0x0 UINT32 Length; //0x4 UINT8 Revision; //0x8 UINT8 Checksum; //0x9 UINT8 OemId[6]; //0xA UINT64 OemTableId; //0x10 UINT32 OemRevision; //0x18 UINT32 CreatorId; //0x1C UINT32 CreatorRevision; //0x20 }EFI_ACPI_DESCRIPTION_HEADER;
*/ typedefstruct {
AMD_ACPI_DESCRIPTION_HEADER SHeader;
UCHAR TableUUID[16]; //0x24
ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
ULONG Reserved[4]; //0x3C
}UEFI_ACPI_VFCT;
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