/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#if !defined (_soc21_ENUM_HEADER)
#define _soc21_ENUM_HEADER
#ifndef _DRIVER_BUILD
#ifndef GL_ZERO
#define GL__ZERO BLEND_ZERO
#define GL__ONE BLEND_ONE
#define GL__SRC_COLOR BLEND_SRC_COLOR
#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
#define GL__DST_COLOR BLEND_DST_COLOR
#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
#define GL__SRC_ALPHA BLEND_SRC_ALPHA
#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
#define GL__DST_ALPHA BLEND_DST_ALPHA
#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
#endif
#endif
/*******************************************************
* Chip Enums
*******************************************************/
/*
* DSM_DATA_SEL enum
*/
typedef enum DSM_DATA_SEL {
DSM_DATA_SEL_DISABLE = 0x00000000,
DSM_DATA_SEL_0 = 0x00000001,
DSM_DATA_SEL_1 = 0x00000002,
DSM_DATA_SEL_BOTH = 0x00000003,
} DSM_DATA_SEL;
/*
* DSM_ENABLE_ERROR_INJECT enum
*/
typedef enum DSM_ENABLE_ERROR_INJECT {
DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
} DSM_ENABLE_ERROR_INJECT;
/*
* DSM_SELECT_INJECT_DELAY enum
*/
typedef enum DSM_SELECT_INJECT_DELAY {
DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
} DSM_SELECT_INJECT_DELAY;
/*
* DSM_SINGLE_WRITE enum
*/
typedef enum DSM_SINGLE_WRITE {
DSM_SINGLE_WRITE_DIS = 0x00000000,
DSM_SINGLE_WRITE_EN = 0x00000001,
} DSM_SINGLE_WRITE;
/*
* ENUM_NUM_SIMD_PER_CU enum
*/
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x00000002,
} ENUM_NUM_SIMD_PER_CU;
/*
* GATCL1RequestType enum
*/
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x00000000,
GATCL1_TYPE_SHOOTDOWN = 0x00000001,
GATCL1_TYPE_BYPASS = 0x00000002,
} GATCL1RequestType;
/*
* GL0V_CACHE_POLICIES enum
*/
typedef enum GL0V_CACHE_POLICIES {
GL0V_CACHE_POLICY_MISS_LRU = 0x00000000,
GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001,
GL0V_CACHE_POLICY_HIT_LRU = 0x00000002,
GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003,
} GL0V_CACHE_POLICIES;
/*
* GL1_CACHE_POLICIES enum
*/
typedef enum GL1_CACHE_POLICIES {
GL1_CACHE_POLICY_MISS_LRU = 0x00000000,
GL1_CACHE_POLICY_MISS_EVICT = 0x00000001,
GL1_CACHE_POLICY_HIT_LRU = 0x00000002,
GL1_CACHE_POLICY_HIT_EVICT = 0x00000003,
} GL1_CACHE_POLICIES;
/*
* GL1_CACHE_STORE_POLICIES enum
*/
typedef enum GL1_CACHE_STORE_POLICIES {
GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000,
} GL1_CACHE_STORE_POLICIES;
/*
* GL2_CACHE_POLICIES enum
*/
typedef enum GL2_CACHE_POLICIES {
GL2_CACHE_POLICY_LRU = 0x00000000,
GL2_CACHE_POLICY_STREAM = 0x00000001,
GL2_CACHE_POLICY_NOA = 0x00000002,
GL2_CACHE_POLICY_BYPASS = 0x00000003,
} GL2_CACHE_POLICIES;
/*
* Hdp_SurfaceEndian enum
*/
typedef enum Hdp_SurfaceEndian {
HDP_ENDIAN_NONE = 0x00000000,
HDP_ENDIAN_8IN16 = 0x00000001,
HDP_ENDIAN_8IN32 = 0x00000002,
HDP_ENDIAN_8IN64 = 0x00000003,
} Hdp_SurfaceEndian;
/*
* MTYPE enum
*/
typedef enum MTYPE {
MTYPE_C_RW_US = 0x00000000,
MTYPE_RESERVED_1 = 0x00000001,
MTYPE_C_RO_S = 0x00000002,
MTYPE_UC = 0x00000003,
MTYPE_C_RW_S = 0x00000004,
MTYPE_RESERVED_5 = 0x00000005,
MTYPE_C_RO_US = 0x00000006,
MTYPE_RESERVED_7 = 0x00000007,
} MTYPE;
/*
* PERFMON_COUNTER_MODE enum
*/
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
PERFMON_COUNTER_MODE_MAX = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
} PERFMON_COUNTER_MODE;
/*
* PERFMON_SPM_MODE enum
*/
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
} PERFMON_SPM_MODE;
/*
* RMI_CID enum
*/
typedef enum RMI_CID {
RMI_CID_CC = 0x00000000,
RMI_CID_FC = 0x00000001,
RMI_CID_CM = 0x00000002,
RMI_CID_DC = 0x00000003,
RMI_CID_Z = 0x00000004,
RMI_CID_S = 0x00000005,
RMI_CID_TILE = 0x00000006,
RMI_CID_ZPCPSD = 0x00000007,
} RMI_CID;
/*
* ReadPolicy enum
*/
typedef enum ReadPolicy {
CACHE_LRU_RD = 0x00000000,
CACHE_STREAM_RD = 0x00000001,
CACHE_NOA = 0x00000002,
RESERVED_RDPOLICY = 0x00000003,
} ReadPolicy;
/*
* SDMA_PERFMON_SEL enum
*/
typedef enum SDMA_PERFMON_SEL {
SDMA_PERFMON_SEL_CYCLE = 0x00000000,
SDMA_PERFMON_SEL_IDLE = 0x00000001,
SDMA_PERFMON_SEL_REG_IDLE = 0x00000002,
SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003,
SDMA_PERFMON_SEL_RB_FULL = 0x00000004,
SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005,
SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006,
SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007,
SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008,
SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009,
SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a,
SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b,
SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c,
SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d,
SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e,
SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010,
SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011,
SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012,
SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013,
SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014,
SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015,
SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016,
SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017,
SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a,
SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b,
SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c,
SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d,
SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e,
SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f,
SDMA_PERFMON_SEL_INT_IDLE = 0x00000020,
SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021,
SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022,
SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023,
SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024,
SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025,
SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027,
SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028,
SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029,
SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a,
SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b,
SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c,
SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d,
SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030,
SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033,
SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034,
SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035,
SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036,
SDMA_PERFMON_SEL_GFX_SELECT = 0x00000037,
SDMA_PERFMON_SEL_RLC0_SELECT = 0x00000038,
SDMA_PERFMON_SEL_RLC1_SELECT = 0x00000039,
SDMA_PERFMON_SEL_PAGE_SELECT = 0x0000003a,
SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b,
SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c,
SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d,
SDMA_PERFMON_SEL_DOORBELL = 0x0000003e,
SDMA_PERFMON_SEL_F32_L1_WR_VLD = 0x0000003f,
SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040,
SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041,
SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042,
SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044,
SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047,
SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048,
SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049,
SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a,
SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b,
SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c,
SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d,
SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e,
SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f,
SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050,
SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051,
SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052,
SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053,
SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054,
SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055,
SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056,
SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057,
SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058,
SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d,
SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e,
SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f,
SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060,
SDMA_PERFMON_SEL_GCR_SEND = 0x00000061,
SDMA_PERFMON_SEL_GCR_RTN = 0x00000062,
SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
} SDMA_PERFMON_SEL;
/*
* SDMA_PERF_SEL enum
*/
typedef enum SDMA_PERF_SEL {
SDMA_PERF_SEL_CYCLE = 0x00000000,
SDMA_PERF_SEL_IDLE = 0x00000001,
SDMA_PERF_SEL_REG_IDLE = 0x00000002,
SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
SDMA_PERF_SEL_RB_FULL = 0x00000004,
SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
SDMA_PERF_SEL_DOORBELL = 0x0000003c,
SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041,
SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042,
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044,
SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047,
SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048,
SDMA_PERF_SEL_UTCL2_FREE = 0x00000049,
SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a,
SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b,
SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c,
SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d,
SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e,
SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f,
SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050,
SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051,
SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052,
SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053,
SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054,
SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055,
SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056,
SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057,
SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058,
SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d,
SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e,
SDMA_PERF_SEL_TLBI_SEND = 0x0000005f,
SDMA_PERF_SEL_TLBI_RTN = 0x00000060,
SDMA_PERF_SEL_GCR_SEND = 0x00000061,
SDMA_PERF_SEL_GCR_RTN = 0x00000062,
SDMA_PERF_SEL_CGCG_FENCE = 0x00000063,
SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064,
SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065,
SDMA_PERF_SEL_F32_CH_WR_REQ = 0x00000066,
SDMA_PERF_SEL_F32_CH_WR_RET = 0x00000067,
SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 0x00000068,
SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 0x00000069,
SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a,
SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b,
SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c,
SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d,
SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e,
SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f,
SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070,
SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071,
SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072,
SDMA_PERF_SEL_CMD_OP_START = 0x00000073,
SDMA_PERF_SEL_CMD_OP_END = 0x00000074,
SDMA_PERF_SEL_CE_BUSY = 0x00000075,
SDMA_PERF_SEL_CE_BUSY_START = 0x00000076,
SDMA_PERF_SEL_CE_BUSY_END = 0x00000077,
SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000078,
SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000079,
SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x0000007a,
SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b,
SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c,
SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d,
SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e,
} SDMA_PERF_SEL;
/*
* TCC_CACHE_POLICIES enum
*/
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x00000000,
TCC_CACHE_POLICY_STREAM = 0x00000001,
} TCC_CACHE_POLICIES;
/*
* TCC_MTYPE enum
*/
typedef enum TCC_MTYPE {
MTYPE_NC = 0x00000000,
MTYPE_WC = 0x00000001,
MTYPE_CC = 0x00000002,
} TCC_MTYPE;
/*
* UTCL0FaultType enum
*/
typedef enum UTCL0FaultType {
UTCL0_XNACK_SUCCESS = 0x00000000,
UTCL0_XNACK_RETRY = 0x00000001,
UTCL0_XNACK_PRT = 0x00000002,
UTCL0_XNACK_NO_RETRY = 0x00000003,
} UTCL0FaultType;
/*
* UTCL0RequestType enum
*/
typedef enum UTCL0RequestType {
UTCL0_TYPE_NORMAL = 0x00000000,
UTCL0_TYPE_SHOOTDOWN = 0x00000001,
UTCL0_TYPE_BYPASS = 0x00000002,
} UTCL0RequestType;
/*
* UTCL1FaultType enum
*/
typedef enum UTCL1FaultType {
UTCL1_XNACK_SUCCESS = 0x00000000,
UTCL1_XNACK_RETRY = 0x00000001,
UTCL1_XNACK_PRT = 0x00000002,
UTCL1_XNACK_NO_RETRY = 0x00000003,
} UTCL1FaultType;
/*
* UTCL1RequestType enum
*/
typedef enum UTCL1RequestType {
UTCL1_TYPE_NORMAL = 0x00000000,
UTCL1_TYPE_SHOOTDOWN = 0x00000001,
UTCL1_TYPE_BYPASS = 0x00000002,
} UTCL1RequestType;
/*
* VMEMCMD_RETURN_ORDER enum
*/
typedef enum VMEMCMD_RETURN_ORDER {
VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000,
VMEMCMD_RETURN_IN_ORDER = 0x00000001,
VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002,
} VMEMCMD_RETURN_ORDER;
/*
* WritePolicy enum
*/
typedef enum WritePolicy {
CACHE_LRU_WR = 0x00000000,
CACHE_STREAM = 0x00000001,
CACHE_NOA_WR = 0x00000002,
CACHE_BYPASS = 0x00000003,
} WritePolicy;
/*******************************************************
* CNVC_CFG Enums
*******************************************************/
/*
* CNVC_BYPASS enum
*/
typedef enum CNVC_BYPASS {
CNVC_BYPASS_DISABLE = 0x00000000,
CNVC_BYPASS_EN = 0x00000001,
} CNVC_BYPASS;
/*
* CNVC_COEF_FORMAT_ENUM enum
*/
typedef enum CNVC_COEF_FORMAT_ENUM {
CNVC_FIX_S2_13 = 0x00000000,
CNVC_FIX_S3_12 = 0x00000001,
} CNVC_COEF_FORMAT_ENUM;
/*
* CNVC_ENABLE enum
*/
typedef enum CNVC_ENABLE {
CNVC_DIS = 0x00000000,
CNVC_EN = 0x00000001,
} CNVC_ENABLE;
/*
* CNVC_PENDING enum
*/
typedef enum CNVC_PENDING {
CNVC_NOT_PENDING = 0x00000000,
CNVC_YES_PENDING = 0x00000001,
} CNVC_PENDING;
/*
* COLOR_KEYER_MODE enum
*/
typedef enum COLOR_KEYER_MODE {
FORCE_00 = 0x00000000,
FORCE_FF = 0x00000001,
RANGE_00 = 0x00000002,
RANGE_FF = 0x00000003,
} COLOR_KEYER_MODE;
/*
* DENORM_TRUNCATE enum
*/
typedef enum DENORM_TRUNCATE {
CNVC_ROUND = 0x00000000,
CNVC_TRUNCATE = 0x00000001,
} DENORM_TRUNCATE;
/*
* FORMAT_CROSSBAR enum
*/
typedef enum FORMAT_CROSSBAR {
FORMAT_CROSSBAR_R = 0x00000000,
FORMAT_CROSSBAR_G = 0x00000001,
FORMAT_CROSSBAR_B = 0x00000002,
} FORMAT_CROSSBAR;
/*
* PIX_EXPAND_MODE enum
*/
typedef enum PIX_EXPAND_MODE {
PIX_DYNAMIC_EXPANSION = 0x00000000,
PIX_ZERO_EXPANSION = 0x00000001,
} PIX_EXPAND_MODE;
/*
* PRE_CSC_MODE_ENUM enum
*/
typedef enum PRE_CSC_MODE_ENUM {
PRE_CSC_BYPASS = 0x00000000,
PRE_CSC_SET_A = 0x00000001,
PRE_CSC_SET_B = 0x00000002,
} PRE_CSC_MODE_ENUM;
/*
* PRE_DEGAM_MODE enum
*/
typedef enum PRE_DEGAM_MODE {
PRE_DEGAM_BYPASS = 0x00000000,
PRE_DEGAM_ENABLE = 0x00000001,
} PRE_DEGAM_MODE;
/*
* PRE_DEGAM_SELECT enum
*/
typedef enum PRE_DEGAM_SELECT {
PRE_DEGAM_SRGB = 0x00000000,
PRE_DEGAM_GAMMA_22 = 0x00000001,
PRE_DEGAM_GAMMA_24 = 0x00000002,
PRE_DEGAM_GAMMA_26 = 0x00000003,
PRE_DEGAM_BT2020 = 0x00000004,
PRE_DEGAM_BT2100PQ = 0x00000005,
PRE_DEGAM_BT2100HLG = 0x00000006,
} PRE_DEGAM_SELECT;
/*
* SURFACE_PIXEL_FORMAT enum
*/
typedef enum SURFACE_PIXEL_FORMAT {
ARGB1555 = 0x00000001,
RGBA5551 = 0x00000002,
RGB565 = 0x00000003,
BGR565 = 0x00000004,
ARGB4444 = 0x00000005,
RGBA4444 = 0x00000006,
ARGB8888 = 0x00000008,
RGBA8888 = 0x00000009,
ARGB2101010 = 0x0000000a,
RGBA1010102 = 0x0000000b,
AYCrCb8888 = 0x0000000c,
YCrCbA8888 = 0x0000000d,
ACrYCb8888 = 0x0000000e,
CrYCbA8888 = 0x0000000f,
ARGB16161616_10MSB = 0x00000010,
RGBA16161616_10MSB = 0x00000011,
ARGB16161616_10LSB = 0x00000012,
RGBA16161616_10LSB = 0x00000013,
ARGB16161616_12MSB = 0x00000014,
RGBA16161616_12MSB = 0x00000015,
ARGB16161616_12LSB = 0x00000016,
RGBA16161616_12LSB = 0x00000017,
ARGB16161616_FLOAT = 0x00000018,
RGBA16161616_FLOAT = 0x00000019,
ARGB16161616_UNORM = 0x0000001a,
RGBA16161616_UNORM = 0x0000001b,
ARGB16161616_SNORM = 0x0000001c,
RGBA16161616_SNORM = 0x0000001d,
AYCrCb16161616_10MSB = 0x00000020,
AYCrCb16161616_10LSB = 0x00000021,
YCrCbA16161616_10MSB = 0x00000022,
YCrCbA16161616_10LSB = 0x00000023,
ACrYCb16161616_10MSB = 0x00000024,
ACrYCb16161616_10LSB = 0x00000025,
CrYCbA16161616_10MSB = 0x00000026,
CrYCbA16161616_10LSB = 0x00000027,
AYCrCb16161616_12MSB = 0x00000028,
AYCrCb16161616_12LSB = 0x00000029,
YCrCbA16161616_12MSB = 0x0000002a,
YCrCbA16161616_12LSB = 0x0000002b,
ACrYCb16161616_12MSB = 0x0000002c,
ACrYCb16161616_12LSB = 0x0000002d,
CrYCbA16161616_12MSB = 0x0000002e,
CrYCbA16161616_12LSB = 0x0000002f,
Y8_CrCb88_420_PLANAR = 0x00000040,
Y8_CbCr88_420_PLANAR = 0x00000041,
Y10_CrCb1010_420_PLANAR = 0x00000042,
Y10_CbCr1010_420_PLANAR = 0x00000043,
Y12_CrCb1212_420_PLANAR = 0x00000044,
Y12_CbCr1212_420_PLANAR = 0x00000045,
YCrYCb8888_422_PACKED = 0x00000048,
YCbYCr8888_422_PACKED = 0x00000049,
CrYCbY8888_422_PACKED = 0x0000004a,
CbYCrY8888_422_PACKED = 0x0000004b,
YCrYCb10101010_422_PACKED = 0x0000004c,
YCbYCr10101010_422_PACKED = 0x0000004d,
CrYCbY10101010_422_PACKED = 0x0000004e,
CbYCrY10101010_422_PACKED = 0x0000004f,
YCrYCb12121212_422_PACKED = 0x00000050,
YCbYCr12121212_422_PACKED = 0x00000051,
CrYCbY12121212_422_PACKED = 0x00000052,
CbYCrY12121212_422_PACKED = 0x00000053,
RGB111110_FIX = 0x00000070,
BGR101111_FIX = 0x00000071,
ACrYCb2101010 = 0x00000072,
CrYCbA1010102 = 0x00000073,
RGBE = 0x00000074,
RGB111110_FLOAT = 0x00000076,
BGR101111_FLOAT = 0x00000077,
MONO_8 = 0x00000078,
MONO_10MSB = 0x00000079,
MONO_10LSB = 0x0000007a,
MONO_12MSB = 0x0000007b,
MONO_12LSB = 0x0000007c,
MONO_16 = 0x0000007d,
} SURFACE_PIXEL_FORMAT;
/*
* XNORM enum
*/
typedef enum XNORM {
XNORM_A = 0x00000000,
XNORM_B = 0x00000001,
} XNORM;
/*******************************************************
* CNVC_CUR Enums
*******************************************************/
/*
* CUR_ENABLE enum
*/
typedef enum CUR_ENABLE {
CUR_DIS = 0x00000000,
CUR_EN = 0x00000001,
} CUR_ENABLE;
/*
* CUR_EXPAND_MODE enum
*/
typedef enum CUR_EXPAND_MODE {
CUR_DYNAMIC_EXPANSION = 0x00000000,
CUR_ZERO_EXPANSION = 0x00000001,
} CUR_EXPAND_MODE;
/*
* CUR_INV_CLAMP enum
*/
typedef enum CUR_INV_CLAMP {
CUR_CLAMP_DIS = 0x00000000,
CUR_CLAMP_EN = 0x00000001,
} CUR_INV_CLAMP;
/*
* CUR_MODE enum
*/
typedef enum CUR_MODE {
MONO_2BIT = 0x00000000,
COLOR_24BIT_1BIT_AND = 0x00000001,
COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
COLOR_64BIT_FP_PREMULT = 0x00000004,
COLOR_64BIT_FP_UNPREMULT = 0x00000005,
} CUR_MODE;
/*
* CUR_PENDING enum
*/
typedef enum CUR_PENDING {
CUR_NOT_PENDING = 0x00000000,
CUR_YES_PENDING = 0x00000001,
} CUR_PENDING;
/*
* CUR_ROM_EN enum
*/
typedef enum CUR_ROM_EN {
CUR_FP_NO_ROM = 0x00000000,
CUR_FP_USE_ROM = 0x00000001,
} CUR_ROM_EN;
/*******************************************************
* DSCL Enums
*******************************************************/
/*
* COEF_RAM_SELECT_RD enum
*/
typedef enum COEF_RAM_SELECT_RD {
COEF_RAM_SELECT_BACK = 0x00000000,
COEF_RAM_SELECT_CURRENT = 0x00000001,
} COEF_RAM_SELECT_RD;
/*
* DSCL_MODE_SEL enum
*/
typedef enum DSCL_MODE_SEL {
DSCL_MODE_SCALING_444_BYPASS = 0x00000000,
DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004,
DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005,
DSCL_MODE_DSCL_BYPASS = 0x00000006,
} DSCL_MODE_SEL;
/*
* LB_ALPHA_EN enum
*/
typedef enum LB_ALPHA_EN {
LB_ALPHA_DISABLE = 0x00000000,
LB_ALPHA_ENABLE = 0x00000001,
} LB_ALPHA_EN;
/*
* LB_INTERLEAVE_EN enum
*/
typedef enum LB_INTERLEAVE_EN {
LB_INTERLEAVE_DISABLE = 0x00000000,
LB_INTERLEAVE_ENABLE = 0x00000001,
} LB_INTERLEAVE_EN;
/*
* LB_MEMORY_CONFIG enum
*/
typedef enum LB_MEMORY_CONFIG {
LB_MEMORY_CONFIG_0 = 0x00000000,
LB_MEMORY_CONFIG_1 = 0x00000001,
LB_MEMORY_CONFIG_2 = 0x00000002,
LB_MEMORY_CONFIG_3 = 0x00000003,
} LB_MEMORY_CONFIG;
/*
* OBUF_BYPASS_SEL enum
*/
typedef enum OBUF_BYPASS_SEL {
OBUF_BYPASS_DIS = 0x00000000,
OBUF_BYPASS_EN = 0x00000001,
} OBUF_BYPASS_SEL;
/*
* OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
*/
typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
OBUF_FULL_RECOUT = 0x00000000,
OBUF_HALF_RECOUT = 0x00000001,
} OBUF_IS_HALF_RECOUT_WIDTH_SEL;
/*
* OBUF_USE_FULL_BUFFER_SEL enum
*/
typedef enum OBUF_USE_FULL_BUFFER_SEL {
OBUF_RECOUT = 0x00000000,
OBUF_FULL = 0x00000001,
} OBUF_USE_FULL_BUFFER_SEL;
/*
* SCL_2TAP_HARDCODE enum
*/
typedef enum SCL_2TAP_HARDCODE {
SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000,
SCL_COEF_2TAP_HARDCODE_ON = 0x00000001,
} SCL_2TAP_HARDCODE;
/*
* SCL_ALPHA_COEF enum
*/
typedef enum SCL_ALPHA_COEF {
SCL_ALPHA_COEF_FIRST = 0x00000000,
SCL_ALPHA_COEF_SECOND = 0x00000001,
} SCL_ALPHA_COEF;
/*
* SCL_AUTOCAL_MODE enum
*/
typedef enum SCL_AUTOCAL_MODE {
AUTOCAL_MODE_OFF = 0x00000000,
AUTOCAL_MODE_AUTOSCALE = 0x00000001,
AUTOCAL_MODE_AUTOCENTER = 0x00000002,
AUTOCAL_MODE_AUTOREPLICATE = 0x00000003,
} SCL_AUTOCAL_MODE;
/*
* SCL_BOUNDARY enum
*/
typedef enum SCL_BOUNDARY {
SCL_BOUNDARY_EDGE = 0x00000000,
SCL_BOUNDARY_BLACK = 0x00000001,
} SCL_BOUNDARY;
/*
* SCL_CHROMA_COEF enum
*/
typedef enum SCL_CHROMA_COEF {
SCL_CHROMA_COEF_FIRST = 0x00000000,
SCL_CHROMA_COEF_SECOND = 0x00000001,
} SCL_CHROMA_COEF;
/*
* SCL_COEF_FILTER_TYPE_SEL enum
*/
typedef enum SCL_COEF_FILTER_TYPE_SEL {
SCL_COEF_LUMA_VERT_FILTER = 0x00000000,
SCL_COEF_LUMA_HORZ_FILTER = 0x00000001,
SCL_COEF_CHROMA_VERT_FILTER = 0x00000002,
SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
} SCL_COEF_FILTER_TYPE_SEL;
/*
* SCL_COEF_RAM_SEL enum
*/
typedef enum SCL_COEF_RAM_SEL {
SCL_COEF_RAM_SEL_0 = 0x00000000,
SCL_COEF_RAM_SEL_1 = 0x00000001,
} SCL_COEF_RAM_SEL;
/*
* SCL_SHARP_EN enum
*/
typedef enum SCL_SHARP_EN {
SCL_SHARP_DISABLE = 0x00000000,
SCL_SHARP_ENABLE = 0x00000001,
} SCL_SHARP_EN;
/*******************************************************
* CM Enums
*******************************************************/
/*
* CMC_3DLUT_30BIT_ENUM enum
*/
typedef enum CMC_3DLUT_30BIT_ENUM {
CMC_3DLUT_36BIT = 0x00000000,
CMC_3DLUT_30BIT = 0x00000001,
} CMC_3DLUT_30BIT_ENUM;
/*
* CMC_3DLUT_RAM_SEL enum
*/
typedef enum CMC_3DLUT_RAM_SEL {
CMC_RAM0_ACCESS = 0x00000000,
CMC_RAM1_ACCESS = 0x00000001,
CMC_RAM2_ACCESS = 0x00000002,
CMC_RAM3_ACCESS = 0x00000003,
} CMC_3DLUT_RAM_SEL;
/*
* CMC_3DLUT_SIZE_ENUM enum
*/
typedef enum CMC_3DLUT_SIZE_ENUM {
CMC_3DLUT_17CUBE = 0x00000000,
CMC_3DLUT_9CUBE = 0x00000001,
} CMC_3DLUT_SIZE_ENUM;
/*
* CMC_LUT_2_CONFIG_ENUM enum
*/
typedef enum CMC_LUT_2_CONFIG_ENUM {
CMC_LUT_2CFG_NO_MEMORY = 0x00000000,
CMC_LUT_2CFG_MEMORY_A = 0x00000001,
CMC_LUT_2CFG_MEMORY_B = 0x00000002,
} CMC_LUT_2_CONFIG_ENUM;
/*
* CMC_LUT_2_MODE_ENUM enum
*/
typedef enum CMC_LUT_2_MODE_ENUM {
CMC_LUT_2_MODE_BYPASS = 0x00000000,
CMC_LUT_2_MODE_RAMA_LUT = 0x00000001,
CMC_LUT_2_MODE_RAMB_LUT = 0x00000002,
} CMC_LUT_2_MODE_ENUM;
/*
* CMC_LUT_NUM_SEG enum
*/
typedef enum CMC_LUT_NUM_SEG {
CMC_SEGMENTS_1 = 0x00000000,
CMC_SEGMENTS_2 = 0x00000001,
CMC_SEGMENTS_4 = 0x00000002,
CMC_SEGMENTS_8 = 0x00000003,
CMC_SEGMENTS_16 = 0x00000004,
CMC_SEGMENTS_32 = 0x00000005,
CMC_SEGMENTS_64 = 0x00000006,
CMC_SEGMENTS_128 = 0x00000007,
} CMC_LUT_NUM_SEG;
/*
* CMC_LUT_RAM_SEL enum
*/
typedef enum CMC_LUT_RAM_SEL {
CMC_RAMA_ACCESS = 0x00000000,
CMC_RAMB_ACCESS = 0x00000001,
} CMC_LUT_RAM_SEL;
/*
* CM_BYPASS enum
*/
typedef enum CM_BYPASS {
NON_BYPASS = 0x00000000,
BYPASS_EN = 0x00000001,
} CM_BYPASS;
/*
* CM_COEF_FORMAT_ENUM enum
*/
typedef enum CM_COEF_FORMAT_ENUM {
FIX_S2_13 = 0x00000000,
FIX_S3_12 = 0x00000001,
} CM_COEF_FORMAT_ENUM;
/*
* CM_DATA_SIGNED enum
*/
typedef enum CM_DATA_SIGNED {
UNSIGNED = 0x00000000,
SIGNED = 0x00000001,
} CM_DATA_SIGNED;
/*
* CM_EN enum
*/
typedef enum CM_EN {
CM_DISABLE = 0x00000000,
CM_ENABLE = 0x00000001,
} CM_EN;
/*
* CM_GAMMA_LUT_MODE_ENUM enum
*/
typedef enum CM_GAMMA_LUT_MODE_ENUM {
BYPASS = 0x00000000,
RESERVED_1 = 0x00000001,
RAM_LUT = 0x00000002,
RESERVED_3 = 0x00000003,
} CM_GAMMA_LUT_MODE_ENUM;
/*
* CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
*/
typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
ENABLE_PWL = 0x00000000,
DISABLE_PWL = 0x00000001,
} CM_GAMMA_LUT_PWL_DISABLE_ENUM;
/*
* CM_GAMMA_LUT_SEL_ENUM enum
*/
typedef enum CM_GAMMA_LUT_SEL_ENUM {
RAMA = 0x00000000,
RAMB = 0x00000001,
} CM_GAMMA_LUT_SEL_ENUM;
/*
* CM_GAMUT_REMAP_MODE_ENUM enum
*/
typedef enum CM_GAMUT_REMAP_MODE_ENUM {
BYPASS_GAMUT = 0x00000000,
GAMUT_COEF = 0x00000001,
GAMUT_COEF_B = 0x00000002,
} CM_GAMUT_REMAP_MODE_ENUM;
/*
* CM_LUT_2_CONFIG_ENUM enum
*/
typedef enum CM_LUT_2_CONFIG_ENUM {
LUT_2CFG_NO_MEMORY = 0x00000000,
LUT_2CFG_MEMORY_A = 0x00000001,
LUT_2CFG_MEMORY_B = 0x00000002,
} CM_LUT_2_CONFIG_ENUM;
/*
* CM_LUT_2_MODE_ENUM enum
*/
typedef enum CM_LUT_2_MODE_ENUM {
LUT_2_MODE_BYPASS = 0x00000000,
LUT_2_MODE_RAMA_LUT = 0x00000001,
LUT_2_MODE_RAMB_LUT = 0x00000002,
} CM_LUT_2_MODE_ENUM;
/*
* CM_LUT_4_CONFIG_ENUM enum
*/
typedef enum CM_LUT_4_CONFIG_ENUM {
LUT_4CFG_NO_MEMORY = 0x00000000,
LUT_4CFG_ROM_A = 0x00000001,
LUT_4CFG_ROM_B = 0x00000002,
LUT_4CFG_MEMORY_A = 0x00000003,
LUT_4CFG_MEMORY_B = 0x00000004,
} CM_LUT_4_CONFIG_ENUM;
/*
* CM_LUT_4_MODE_ENUM enum
*/
typedef enum CM_LUT_4_MODE_ENUM {
LUT_4_MODE_BYPASS = 0x00000000,
LUT_4_MODE_ROMA_LUT = 0x00000001,
LUT_4_MODE_ROMB_LUT = 0x00000002,
LUT_4_MODE_RAMA_LUT = 0x00000003,
LUT_4_MODE_RAMB_LUT = 0x00000004,
} CM_LUT_4_MODE_ENUM;
/*
* CM_LUT_CONFIG_MODE enum
*/
typedef enum CM_LUT_CONFIG_MODE {
DIFFERENT_RGB = 0x00000000,
ALL_USE_R = 0x00000001,
} CM_LUT_CONFIG_MODE;
/*
* CM_LUT_NUM_SEG enum
*/
typedef enum CM_LUT_NUM_SEG {
SEGMENTS_1 = 0x00000000,
SEGMENTS_2 = 0x00000001,
SEGMENTS_4 = 0x00000002,
SEGMENTS_8 = 0x00000003,
SEGMENTS_16 = 0x00000004,
SEGMENTS_32 = 0x00000005,
SEGMENTS_64 = 0x00000006,
SEGMENTS_128 = 0x00000007,
} CM_LUT_NUM_SEG;
/*
* CM_LUT_RAM_SEL enum
*/
typedef enum CM_LUT_RAM_SEL {
RAMA_ACCESS = 0x00000000,
RAMB_ACCESS = 0x00000001,
} CM_LUT_RAM_SEL;
/*
* CM_LUT_READ_COLOR_SEL enum
*/
typedef enum CM_LUT_READ_COLOR_SEL {
BLUE_LUT = 0x00000000,
GREEN_LUT = 0x00000001,
RED_LUT = 0x00000002,
} CM_LUT_READ_COLOR_SEL;
/*
* CM_LUT_READ_DBG enum
*/
typedef enum CM_LUT_READ_DBG {
DISABLE_DEBUG = 0x00000000,
ENABLE_DEBUG = 0x00000001,
} CM_LUT_READ_DBG;
/*
* CM_PENDING enum
*/
typedef enum CM_PENDING {
CM_NOT_PENDING = 0x00000000,
CM_YES_PENDING = 0x00000001,
} CM_PENDING;
/*
* CM_POST_CSC_MODE_ENUM enum
*/
typedef enum CM_POST_CSC_MODE_ENUM {
BYPASS_POST_CSC = 0x00000000,
COEF_POST_CSC = 0x00000001,
COEF_POST_CSC_B = 0x00000002,
} CM_POST_CSC_MODE_ENUM;
/*
* CM_WRITE_BASE_ONLY enum
*/
typedef enum CM_WRITE_BASE_ONLY {
WRITE_BOTH = 0x00000000,
WRITE_BASE_ONLY = 0x00000001,
} CM_WRITE_BASE_ONLY;
/*******************************************************
* DPP_TOP Enums
*******************************************************/
/*
* CRC_CUR_SEL enum
*/
typedef enum CRC_CUR_SEL {
CRC_CUR_0 = 0x00000000,
CRC_CUR_1 = 0x00000001,
} CRC_CUR_SEL;
/*
* CRC_INTERLACE_SEL enum
*/
typedef enum CRC_INTERLACE_SEL {
CRC_INTERLACE_0 = 0x00000000,
CRC_INTERLACE_1 = 0x00000001,
CRC_INTERLACE_2 = 0x00000002,
CRC_INTERLACE_3 = 0x00000003,
} CRC_INTERLACE_SEL;
/*
* CRC_IN_CUR_SEL enum
*/
typedef enum CRC_IN_CUR_SEL {
CRC_IN_CUR_0 = 0x00000000,
CRC_IN_CUR_1 = 0x00000001,
CRC_IN_CUR_2 = 0x00000002,
CRC_IN_CUR_3 = 0x00000003,
} CRC_IN_CUR_SEL;
/*
* CRC_IN_PIX_SEL enum
*/
typedef enum CRC_IN_PIX_SEL {
CRC_IN_PIX_0 = 0x00000000,
CRC_IN_PIX_1 = 0x00000001,
CRC_IN_PIX_2 = 0x00000002,
CRC_IN_PIX_3 = 0x00000003,
CRC_IN_PIX_4 = 0x00000004,
CRC_IN_PIX_5 = 0x00000005,
CRC_IN_PIX_6 = 0x00000006,
CRC_IN_PIX_7 = 0x00000007,
} CRC_IN_PIX_SEL;
/*
* CRC_SRC_SEL enum
*/
typedef enum CRC_SRC_SEL {
CRC_SRC_0 = 0x00000000,
CRC_SRC_1 = 0x00000001,
CRC_SRC_2 = 0x00000002,
CRC_SRC_3 = 0x00000003,
} CRC_SRC_SEL;
/*
* CRC_STEREO_SEL enum
*/
typedef enum CRC_STEREO_SEL {
CRC_STEREO_0 = 0x00000000,
CRC_STEREO_1 = 0x00000001,
CRC_STEREO_2 = 0x00000002,
CRC_STEREO_3 = 0x00000003,
} CRC_STEREO_SEL;
/*
* TEST_CLK_SEL enum
*/
typedef enum TEST_CLK_SEL {
TEST_CLK_SEL_0 = 0x00000000,
TEST_CLK_SEL_1 = 0x00000001,
TEST_CLK_SEL_2 = 0x00000002,
TEST_CLK_SEL_3 = 0x00000003,
TEST_CLK_SEL_4 = 0x00000004,
TEST_CLK_SEL_5 = 0x00000005,
TEST_CLK_SEL_6 = 0x00000006,
TEST_CLK_SEL_7 = 0x00000007,
} TEST_CLK_SEL;
/*******************************************************
* DC_PERFMON Enums
*******************************************************/
/*
* PERFCOUNTER_ACTIVE enum
*/
typedef enum PERFCOUNTER_ACTIVE {
PERFCOUNTER_IS_IDLE = 0x00000000,
PERFCOUNTER_IS_ACTIVE = 0x00000001,
} PERFCOUNTER_ACTIVE;
/*
* PERFCOUNTER_CNT0_STATE enum
*/
typedef enum PERFCOUNTER_CNT0_STATE {
PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT0_STATE_START = 0x00000001,
PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT0_STATE;
/*
* PERFCOUNTER_CNT1_STATE enum
*/
typedef enum PERFCOUNTER_CNT1_STATE {
PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT1_STATE_START = 0x00000001,
PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT1_STATE;
/*
* PERFCOUNTER_CNT2_STATE enum
*/
typedef enum PERFCOUNTER_CNT2_STATE {
PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT2_STATE_START = 0x00000001,
PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT2_STATE;
/*
* PERFCOUNTER_CNT3_STATE enum
*/
typedef enum PERFCOUNTER_CNT3_STATE {
PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT3_STATE_START = 0x00000001,
PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT3_STATE;
/*
* PERFCOUNTER_CNT4_STATE enum
*/
typedef enum PERFCOUNTER_CNT4_STATE {
PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT4_STATE_START = 0x00000001,
PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT4_STATE;
/*
* PERFCOUNTER_CNT5_STATE enum
*/
typedef enum PERFCOUNTER_CNT5_STATE {
PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT5_STATE_START = 0x00000001,
PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT5_STATE;
/*
* PERFCOUNTER_CNT6_STATE enum
*/
typedef enum PERFCOUNTER_CNT6_STATE {
PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT6_STATE_START = 0x00000001,
PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT6_STATE;
/*
* PERFCOUNTER_CNT7_STATE enum
*/
typedef enum PERFCOUNTER_CNT7_STATE {
PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT7_STATE_START = 0x00000001,
PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT7_STATE;
/*
* PERFCOUNTER_CNTL_SEL enum
*/
typedef enum PERFCOUNTER_CNTL_SEL {
PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
} PERFCOUNTER_CNTL_SEL;
/*
* PERFCOUNTER_CNTOFF_START_DIS enum
*/
typedef enum PERFCOUNTER_CNTOFF_START_DIS {
PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
} PERFCOUNTER_CNTOFF_START_DIS;
/*
* PERFCOUNTER_COUNTED_VALUE_TYPE enum
*/
typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
} PERFCOUNTER_COUNTED_VALUE_TYPE;
/*
* PERFCOUNTER_CVALUE_SEL enum
*/
typedef enum PERFCOUNTER_CVALUE_SEL {
PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
} PERFCOUNTER_CVALUE_SEL;
/*
* PERFCOUNTER_HW_CNTL_SEL enum
*/
typedef enum PERFCOUNTER_HW_CNTL_SEL {
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
} PERFCOUNTER_HW_CNTL_SEL;
/*
* PERFCOUNTER_HW_STOP1_SEL enum
*/
typedef enum PERFCOUNTER_HW_STOP1_SEL {
PERFCOUNTER_HW_STOP1_0 = 0x00000000,
PERFCOUNTER_HW_STOP1_1 = 0x00000001,
} PERFCOUNTER_HW_STOP1_SEL;
/*
* PERFCOUNTER_HW_STOP2_SEL enum
*/
typedef enum PERFCOUNTER_HW_STOP2_SEL {
PERFCOUNTER_HW_STOP2_0 = 0x00000000,
PERFCOUNTER_HW_STOP2_1 = 0x00000001,
} PERFCOUNTER_HW_STOP2_SEL;
/*
* PERFCOUNTER_INC_MODE enum
*/
typedef enum PERFCOUNTER_INC_MODE {
PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
PERFCOUNTER_INC_MODE_LSB = 0x00000002,
PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
} PERFCOUNTER_INC_MODE;
/*
* PERFCOUNTER_INT_EN enum
*/
typedef enum PERFCOUNTER_INT_EN {
PERFCOUNTER_INT_DISABLE = 0x00000000,
PERFCOUNTER_INT_ENABLE = 0x00000001,
} PERFCOUNTER_INT_EN;
/*
* PERFCOUNTER_INT_TYPE enum
*/
typedef enum PERFCOUNTER_INT_TYPE {
PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
} PERFCOUNTER_INT_TYPE;
/*
* PERFCOUNTER_OFF_MASK enum
*/
typedef enum PERFCOUNTER_OFF_MASK {
PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
} PERFCOUNTER_OFF_MASK;
/*
* PERFCOUNTER_RESTART_EN enum
*/
typedef enum PERFCOUNTER_RESTART_EN {
PERFCOUNTER_RESTART_DISABLE = 0x00000000,
PERFCOUNTER_RESTART_ENABLE = 0x00000001,
} PERFCOUNTER_RESTART_EN;
/*
* PERFCOUNTER_RUNEN_MODE enum
*/
typedef enum PERFCOUNTER_RUNEN_MODE {
PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
} PERFCOUNTER_RUNEN_MODE;
/*
* PERFCOUNTER_STATE_SEL0 enum
*/
typedef enum PERFCOUNTER_STATE_SEL0 {
PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL0;
/*
* PERFCOUNTER_STATE_SEL1 enum
*/
typedef enum PERFCOUNTER_STATE_SEL1 {
PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL1;
/*
* PERFCOUNTER_STATE_SEL2 enum
*/
typedef enum PERFCOUNTER_STATE_SEL2 {
PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL2;
/*
* PERFCOUNTER_STATE_SEL3 enum
*/
typedef enum PERFCOUNTER_STATE_SEL3 {
PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL3;
/*
* PERFCOUNTER_STATE_SEL4 enum
*/
typedef enum PERFCOUNTER_STATE_SEL4 {
PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL4;
/*
* PERFCOUNTER_STATE_SEL5 enum
*/
typedef enum PERFCOUNTER_STATE_SEL5 {
PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL5;
/*
* PERFCOUNTER_STATE_SEL6 enum
*/
typedef enum PERFCOUNTER_STATE_SEL6 {
PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL6;
/*
* PERFCOUNTER_STATE_SEL7 enum
*/
typedef enum PERFCOUNTER_STATE_SEL7 {
PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL7;
/*
* PERFMON_CNTOFF_AND_OR enum
*/
typedef enum PERFMON_CNTOFF_AND_OR {
PERFMON_CNTOFF_OR = 0x00000000,
PERFMON_CNTOFF_AND = 0x00000001,
} PERFMON_CNTOFF_AND_OR;
/*
* PERFMON_CNTOFF_INT_EN enum
*/
typedef enum PERFMON_CNTOFF_INT_EN {
PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
} PERFMON_CNTOFF_INT_EN;
/*
* PERFMON_CNTOFF_INT_TYPE enum
*/
typedef enum PERFMON_CNTOFF_INT_TYPE {
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
} PERFMON_CNTOFF_INT_TYPE;
/*
* PERFMON_STATE enum
*/
typedef enum PERFMON_STATE {
PERFMON_STATE_RESET = 0x00000000,
PERFMON_STATE_START = 0x00000001,
PERFMON_STATE_FREEZE = 0x00000002,
PERFMON_STATE_HW = 0x00000003,
} PERFMON_STATE;
/*******************************************************
* HUBP Enums
*******************************************************/
/*
* BIGK_FRAGMENT_SIZE enum
*/
typedef enum BIGK_FRAGMENT_SIZE {
VM_PG_SIZE_4KB = 0x00000000,
VM_PG_SIZE_8KB = 0x00000001,
VM_PG_SIZE_16KB = 0x00000002,
VM_PG_SIZE_32KB = 0x00000003,
VM_PG_SIZE_64KB = 0x00000004,
VM_PG_SIZE_128KB = 0x00000005,
VM_PG_SIZE_256KB = 0x00000006,
VM_PG_SIZE_512KB = 0x00000007,
VM_PG_SIZE_1024KB = 0x00000008,
VM_PG_SIZE_2048KB = 0x00000009,
} BIGK_FRAGMENT_SIZE;
/*
* CHUNK_SIZE enum
*/
typedef enum CHUNK_SIZE {
CHUNK_SIZE_1KB = 0x00000000,
CHUNK_SIZE_2KB = 0x00000001,
CHUNK_SIZE_4KB = 0x00000002,
CHUNK_SIZE_8KB = 0x00000003,
CHUNK_SIZE_16KB = 0x00000004,
CHUNK_SIZE_32KB = 0x00000005,
CHUNK_SIZE_64KB = 0x00000006,
} CHUNK_SIZE;
/*
* COMPAT_LEVEL enum
*/
typedef enum COMPAT_LEVEL {
ADDR_GEN_ZERO = 0x00000000,
ADDR_GEN_ONE = 0x00000001,
ADDR_GEN_TWO = 0x00000002,
ADDR_RESERVED = 0x00000003,
} COMPAT_LEVEL;
/*
* DPTE_GROUP_SIZE enum
*/
typedef enum DPTE_GROUP_SIZE {
DPTE_GROUP_SIZE_64B = 0x00000000,
DPTE_GROUP_SIZE_128B = 0x00000001,
DPTE_GROUP_SIZE_256B = 0x00000002,
DPTE_GROUP_SIZE_512B = 0x00000003,
DPTE_GROUP_SIZE_1024B = 0x00000004,
DPTE_GROUP_SIZE_2048B = 0x00000005,
} DPTE_GROUP_SIZE;
/*
* FORCE_ONE_ROW_FOR_FRAME enum
*/
typedef enum FORCE_ONE_ROW_FOR_FRAME {
FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000,
FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001,
} FORCE_ONE_ROW_FOR_FRAME;
/*
* HUBP_BLANK_EN enum
*/
typedef enum HUBP_BLANK_EN {
HUBP_BLANK_SW_DEASSERT = 0x00000000,
HUBP_BLANK_SW_ASSERT = 0x00000001,
} HUBP_BLANK_EN;
/*
* HUBP_IN_BLANK enum
*/
typedef enum HUBP_IN_BLANK {
HUBP_IN_ACTIVE = 0x00000000,
HUBP_IN_VBLANK = 0x00000001,
} HUBP_IN_BLANK;
/*
* HUBP_MEASURE_WIN_MODE_DCFCLK enum
*/
typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000,
HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001,
HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002,
HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003,
} HUBP_MEASURE_WIN_MODE_DCFCLK;
/*
* HUBP_NO_OUTSTANDING_REQ enum
*/
typedef enum HUBP_NO_OUTSTANDING_REQ {
OUTSTANDING_REQ = 0x00000000,
NO_OUTSTANDING_REQ = 0x00000001,
} HUBP_NO_OUTSTANDING_REQ;
/*
* HUBP_SOFT_RESET enum
*/
typedef enum HUBP_SOFT_RESET {
HUBP_SOFT_RESET_ON = 0x00000000,
HUBP_SOFT_RESET_OFF = 0x00000001,
} HUBP_SOFT_RESET;
/*
* HUBP_TTU_DISABLE enum
*/
typedef enum HUBP_TTU_DISABLE {
HUBP_TTU_ENABLED = 0x00000000,
HUBP_TTU_DISABLED = 0x00000001,
} HUBP_TTU_DISABLE;
/*
* HUBP_VREADY_AT_OR_AFTER_VSYNC enum
*/
typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
VREADY_BEFORE_VSYNC = 0x00000000,
VREADY_AT_OR_AFTER_VSYNC = 0x00000001,
} HUBP_VREADY_AT_OR_AFTER_VSYNC;
/*
* HUBP_VTG_SEL enum
*/
typedef enum HUBP_VTG_SEL {
VTG_SEL_0 = 0x00000000,
VTG_SEL_1 = 0x00000001,
VTG_SEL_2 = 0x00000002,
VTG_SEL_3 = 0x00000003,
VTG_SEL_4 = 0x00000004,
VTG_SEL_5 = 0x00000005,
} HUBP_VTG_SEL;
/*
* H_MIRROR_EN enum
*/
typedef enum H_MIRROR_EN {
HW_MIRRORING_DISABLE = 0x00000000,
HW_MIRRORING_ENABLE = 0x00000001,
} H_MIRROR_EN;
/*
* LEGACY_PIPE_INTERLEAVE enum
*/
typedef enum LEGACY_PIPE_INTERLEAVE {
LEGACY_PIPE_INTERLEAVE_256B = 0x00000000,
LEGACY_PIPE_INTERLEAVE_512B = 0x00000001,
} LEGACY_PIPE_INTERLEAVE;
/*
* META_CHUNK_SIZE enum
*/
typedef enum META_CHUNK_SIZE {
META_CHUNK_SIZE_1KB = 0x00000000,
META_CHUNK_SIZE_2KB = 0x00000001,
META_CHUNK_SIZE_4KB = 0x00000002,
META_CHUNK_SIZE_8KB = 0x00000003,
} META_CHUNK_SIZE;
/*
* META_LINEAR enum
*/
typedef enum META_LINEAR {
META_SURF_TILED = 0x00000000,
META_SURF_LINEAR = 0x00000001,
} META_LINEAR;
/*
* MIN_CHUNK_SIZE enum
*/
typedef enum MIN_CHUNK_SIZE {
NO_MIN_CHUNK_SIZE = 0x00000000,
MIN_CHUNK_SIZE_256B = 0x00000001,
MIN_CHUNK_SIZE_512B = 0x00000002,
MIN_CHUNK_SIZE_1024B = 0x00000003,
} MIN_CHUNK_SIZE;
/*
* MIN_META_CHUNK_SIZE enum
*/
typedef enum MIN_META_CHUNK_SIZE {
NO_MIN_META_CHUNK_SIZE = 0x00000000,
MIN_META_CHUNK_SIZE_64B = 0x00000001,
MIN_META_CHUNK_SIZE_128B = 0x00000002,
MIN_META_CHUNK_SIZE_256B = 0x00000003,
} MIN_META_CHUNK_SIZE;
/*
* PIPE_ALIGNED enum
*/
typedef enum PIPE_ALIGNED {
PIPE_UNALIGNED_SURF = 0x00000000,
PIPE_ALIGNED_SURF = 0x00000001,
} PIPE_ALIGNED;
/*
* PTE_BUFFER_MODE enum
*/
typedef enum PTE_BUFFER_MODE {
PTE_BUFFER_MODE_0 = 0x00000000,
PTE_BUFFER_MODE_1 = 0x00000001,
} PTE_BUFFER_MODE;
/*
* PTE_ROW_HEIGHT_LINEAR enum
*/
typedef enum PTE_ROW_HEIGHT_LINEAR {
PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000,
PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001,
PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002,
PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003,
PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004,
PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005,
PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006,
PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007,
} PTE_ROW_HEIGHT_LINEAR;
/*
* ROTATION_ANGLE enum
*/
typedef enum ROTATION_ANGLE {
ROTATE_0_DEGREES = 0x00000000,
ROTATE_90_DEGREES = 0x00000001,
ROTATE_180_DEGREES = 0x00000002,
ROTATE_270_DEGREES = 0x00000003,
} ROTATION_ANGLE;
/*
* SWATH_HEIGHT enum
*/
typedef enum SWATH_HEIGHT {
SWATH_HEIGHT_1L = 0x00000000,
SWATH_HEIGHT_2L = 0x00000001,
SWATH_HEIGHT_4L = 0x00000002,
SWATH_HEIGHT_8L = 0x00000003,
SWATH_HEIGHT_16L = 0x00000004,
} SWATH_HEIGHT;
/*
* USE_MALL_FOR_CURSOR enum
*/
typedef enum USE_MALL_FOR_CURSOR {
USE_MALL_FOR_CURSOR_0 = 0x00000000,
USE_MALL_FOR_CURSOR_1 = 0x00000001,
} USE_MALL_FOR_CURSOR;
/*
* USE_MALL_FOR_PSTATE_CHANGE enum
*/
typedef enum USE_MALL_FOR_PSTATE_CHANGE {
USE_MALL_FOR_PSTATE_CHANGE_0 = 0x00000000,
USE_MALL_FOR_PSTATE_CHANGE_1 = 0x00000001,
} USE_MALL_FOR_PSTATE_CHANGE;
/*
* USE_MALL_FOR_STATIC_SCREEN enum
*/
typedef enum USE_MALL_FOR_STATIC_SCREEN {
USE_MALL_FOR_STATIC_SCREEN_0 = 0x00000000,
USE_MALL_FOR_STATIC_SCREEN_1 = 0x00000001,
} USE_MALL_FOR_STATIC_SCREEN;
/*
* VMPG_SIZE enum
*/
typedef enum VMPG_SIZE {
VMPG_SIZE_4KB = 0x00000000,
VMPG_SIZE_64KB = 0x00000001,
} VMPG_SIZE;
/*
* VM_GROUP_SIZE enum
*/
typedef enum VM_GROUP_SIZE {
VM_GROUP_SIZE_64B = 0x00000000,
VM_GROUP_SIZE_128B = 0x00000001,
VM_GROUP_SIZE_256B = 0x00000002,
VM_GROUP_SIZE_512B = 0x00000003,
VM_GROUP_SIZE_1024B = 0x00000004,
VM_GROUP_SIZE_2048B = 0x00000005,
} VM_GROUP_SIZE;
/*******************************************************
* HUBPREQ Enums
*******************************************************/
/*
* DFQ_MIN_FREE_ENTRIES enum
*/
typedef enum DFQ_MIN_FREE_ENTRIES {
DFQ_MIN_FREE_ENTRIES_0 = 0x00000000,
DFQ_MIN_FREE_ENTRIES_1 = 0x00000001,
DFQ_MIN_FREE_ENTRIES_2 = 0x00000002,
DFQ_MIN_FREE_ENTRIES_3 = 0x00000003,
DFQ_MIN_FREE_ENTRIES_4 = 0x00000004,
DFQ_MIN_FREE_ENTRIES_5 = 0x00000005,
DFQ_MIN_FREE_ENTRIES_6 = 0x00000006,
DFQ_MIN_FREE_ENTRIES_7 = 0x00000007,
} DFQ_MIN_FREE_ENTRIES;
/*
* DFQ_NUM_ENTRIES enum
*/
typedef enum DFQ_NUM_ENTRIES {
DFQ_NUM_ENTRIES_0 = 0x00000000,
DFQ_NUM_ENTRIES_1 = 0x00000001,
DFQ_NUM_ENTRIES_2 = 0x00000002,
DFQ_NUM_ENTRIES_3 = 0x00000003,
DFQ_NUM_ENTRIES_4 = 0x00000004,
DFQ_NUM_ENTRIES_5 = 0x00000005,
DFQ_NUM_ENTRIES_6 = 0x00000006,
DFQ_NUM_ENTRIES_7 = 0x00000007,
DFQ_NUM_ENTRIES_8 = 0x00000008,
} DFQ_NUM_ENTRIES;
/*
* DFQ_SIZE enum
*/
typedef enum DFQ_SIZE {
DFQ_SIZE_0 = 0x00000000,
DFQ_SIZE_1 = 0x00000001,
DFQ_SIZE_2 = 0x00000002,
DFQ_SIZE_3 = 0x00000003,
DFQ_SIZE_4 = 0x00000004,
DFQ_SIZE_5 = 0x00000005,
DFQ_SIZE_6 = 0x00000006,
DFQ_SIZE_7 = 0x00000007,
} DFQ_SIZE;
/*
* DMDATA_VM_DONE enum
*/
typedef enum DMDATA_VM_DONE {
DMDATA_VM_IS_NOT_DONE = 0x00000000,
DMDATA_VM_IS_DONE = 0x00000001,
} DMDATA_VM_DONE;
/*
* EXPANSION_MODE enum
*/
typedef enum EXPANSION_MODE {
EXPANSION_MODE_ZERO = 0x00000000,
EXPANSION_MODE_CONSERVATIVE = 0x00000001,
EXPANSION_MODE_OPTIMAL = 0x00000002,
} EXPANSION_MODE;
/*
* FLIP_RATE enum
*/
typedef enum FLIP_RATE {
FLIP_RATE_0 = 0x00000000,
FLIP_RATE_1 = 0x00000001,
FLIP_RATE_2 = 0x00000002,
FLIP_RATE_3 = 0x00000003,
FLIP_RATE_4 = 0x00000004,
FLIP_RATE_5 = 0x00000005,
FLIP_RATE_6 = 0x00000006,
FLIP_RATE_7 = 0x00000007,
} FLIP_RATE;
/*
* INT_MASK enum
*/
typedef enum INT_MASK {
INT_DISABLED = 0x00000000,
INT_ENABLED = 0x00000001,
} INT_MASK;
/*
* PIPE_IN_FLUSH_URGENT enum
*/
typedef enum PIPE_IN_FLUSH_URGENT {
PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000,
PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001,
} PIPE_IN_FLUSH_URGENT;
/*
* PRQ_MRQ_FLUSH_URGENT enum
*/
typedef enum PRQ_MRQ_FLUSH_URGENT {
PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000,
PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001,
} PRQ_MRQ_FLUSH_URGENT;
/*
* ROW_TTU_MODE enum
*/
typedef enum ROW_TTU_MODE {
END_OF_ROW_MODE = 0x00000000,
WATERMARK_MODE = 0x00000001,
} ROW_TTU_MODE;
/*
* SURFACE_DCC enum
*/
typedef enum SURFACE_DCC {
SURFACE_IS_NOT_DCC = 0x00000000,
SURFACE_IS_DCC = 0x00000001,
} SURFACE_DCC;
/*
* SURFACE_DCC_IND_128B enum
*/
typedef enum SURFACE_DCC_IND_128B {
SURFACE_DCC_IS_NOT_IND_128B = 0x00000000,
SURFACE_DCC_IS_IND_128B = 0x00000001,
} SURFACE_DCC_IND_128B;
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